System Management Bus (Smbus); System Fan - ADLINK Technology CoreModule 745 Reference Manual

Chapter 3
Table 3-13 describes the pin signals of the Utility interface, which uses a 5-pin, single-row header with
0.100" (2.54mm) pitch.
Table 3-13. Utility Interface Pin Signals (J23)
Pin # Signal
1 /PWR_BTN*
2 GND
3 /RESET SW*
4 5V
5 SPKR_CONN
Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.

System Management Bus (SMBus)

The ICH8-M chip contains a host SMBus port. The host port allows the CPU access to the SMBus slaves
through header, J20. The SMBus slaves include the SODIMM EPROM, Clock Buffer, Clock Generator, and
the Gb Ethernet Controller.
on the SMBus. Table 3-15
with 0.049" (2 mm) pitch.
Table 3-14. SMBus Reserved Addresses
Component
SODIMM EPROM
Clock Generator
Clock Buffer
Gb Ethernet Controller
Table 3-15. SMBus Pin Signals (J20)
Pin # Signal
1 SMB_CLK
2 GND
3 SMB_DATA
4 VSM
5 /SMB_ALERT*
Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.

System Fan

Table 3-16 lists the pin signals of the optional System Fan header, which provides 3 pins with 0.079" (2mm)
pitch.
Table 3-16. Optional System Fan Pin Signals (J22)
Pin # Signal
1 VCC
2 NC
3 GND
Note: The shaded table cells denote power or ground.
CoreModule 745
Description
External Power Button (Pins 1-2)
Ground
External Reset Switch signal (Pins 2-3)
+5 Volts Power
Speaker Output (Pins 4-5)
Table 3-14 lists the device names and corresponding reserved binary addresses
lists the SMBus pin signals, which are routed through a 5-pin, single-row header
Address Binary
1010,000x
1101,001x
1101,110x
1100,001x
Description
SMBus Clock
Ground
SMBus Data
+3.3V standby voltage
SMBus Alert
Description
+5.0 volts DC +/- 5%
Not Connected
Ground
Reference Manual
b
b
b
b
Hardware
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