Page 1 XMC4500 Microcontroller Series for Industrial Applications XMC4000 Family ® ® Cortex 32-bit processor core Reference Manual V1.6 2016-07 M i c r o c o n t r o l l e r s...
Page 2 Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life.
Page 3 XMC4500 Microcontroller Series for Industrial Applications XMC4000 Family ® ® Cortex 32-bit processor core Reference Manual V1.6 2016-07 M i c r o c o n t r o l l e r s...
Page 4 – SYSTEM_TIME_HIGHER_WORD_SECONDS 15-296, – TIMESTAMP_STATUS 15-299, – BUS_MODE 15-332 • Revised “Interconnects” section 26-1 Adjusted text style only to match Infineon standard. Previous Versions: V1.4, 2014-04 Page Subjects Reference Manual V1.6, 2016-07 Subject to Agreement on the Use of Product Information...
Page 5 17-227ff. • Added hints on the signal usage to Interconnect tables 26-1 “Startup Modes” chapter enhanced for readability. 27-12 Added Infineon JTAG ID code information to table in DEBUG chapter. Previous Versions: V1.2, 2012-12 V1.1, 2012-07 V1.0, 2012-02 Page Subjects Reference Manual V1.6, 2016-07...
Page 6 • Added note on driver mode on hardwired pins (HIB_IOs and TMS). 27-12 Revised the ROM table section in DEBUG chapter. Trademarks C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG. ® ® ® , ARM Powered and AMBA are registered trademarks of ARM, Limited.
Page 7 Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Reference Manual V1.6, 2016-07...
Page 8: Table Of Contents
XMC4500 XMC4000 Family Table of Contents Table of Contents Introduction ..........1-1 Overview .
Page 9: Table 7-4 Table
XMC4500 XMC4000 Family Table of Contents 2.6.2 Fault Escalation and Hard Faults ......2-38 2.6.3 Fault Status Registers and Fault Address Registers .
Page 10: Table 8-1 Table
XMC4500 XMC4000 Family Table of Contents 4.4.2 DMA Service Request Source Selection ..... . 4-10 Event Request Unit (ERU) ........4-15 4.5.1 Event Request Select Unit (ERS) .
Page 11: Table 8-3 Table
XMC4500 XMC4000 Family Table of Contents 5.4.6 Programing Examples ........5-34 5.4.6.1 Single-block Transfer .
Page 12: Table 8-5 Table
XMC4500 XMC4000 Family Table of Contents Memory Regions ......... . . 7-3 Memory Map .
Page 13: Table 8-7 Table
XMC4500 XMC4000 Family Table of Contents 8.5.3.2 PFOPER “Operation Error” ......8-26 8.5.3.3 PROER “Protection Error”...
Page 14: Table 8-9 Table
XMC4500 XMC4000 Family Table of Contents 10.1 Overview ..........10-1 10.1.1 Features .
Page 15: Table 8-11 Table
XMC4500 XMC4000 Family Table of Contents 11.3.3 Hibernate Domain Operating Modes ......11-17 11.3.4 Embedded Voltage Regulator (EVR) ......11-19 11.3.5 Power-on Reset .
Page 16: Table 9-2 Table
XMC4500 XMC4000 Family Table of Contents 11.9.1 Power-Up ..........11-52 11.9.2 Power-on Reset Release .
Page 17: Table 9-4 Table
XMC4500 XMC4000 Family Table of Contents 13.4 Data Transfer Modes ........13-6 13.5 Read/ Write Operation .
Page 18: Table 10-2 Table
XMC4500 XMC4000 Family Table of Contents 14.7 External Bus Arbitration ........14-24 14.7.1 External Bus Modes .
Page 19: Table 10-4 Table
XMC4500 XMC4000 Family Table of Contents 14.11.11 Critical Word First Read Accesses ......14-59 14.11.12 Example Burst Flash Access Cycle ......14-59 14.11.13 External Cycle Control via the WAIT Input .
Page 20: Table 11-2 Table
XMC4500 XMC4000 Family Table of Contents 15.1 Overview ..........15-1 15.1.1 ETH Core Features .
Page 21: Table 11-6 Table
XMC4500 XMC4000 Family Table of Contents 15.2.11.4 Time Stamp Error Margin ......15-91 15.2.11.5 Frequency Range of Reference Timing Clock .
Page 22: Table 12-1 Table
XMC4500 XMC4000 Family Table of Contents 16.4.1 Host Initialization ........16-12 16.4.2 Host Connection .
Page 23: Table 12-3 Table
XMC4500 XMC4000 Family Table of Contents 16.6.3.3 NAK and NYET Handling With Internal DMA ....16-41 16.6.3.4 Handling Interrupts ........16-43 16.6.4 Interrupt IN Transactions in Buffer DMA Mode .
Page 24: Table 12-5 Table
XMC4500 XMC4000 Family Table of Contents 16.8.6 Programming IN Endpoint Features ......16-79 16.8.6.1 Setting IN Endpoint NAK ....... 16-79 16.8.6.2 IN Endpoint Disable .
Page 25: Table 12-7 Table
XMC4500 XMC4000 Family Table of Contents 16.10.6 Periodic IN (Interrupt and Isochronous) Data Transfers ..16-138 16.10.7 Periodic IN Data Transfers Using the Periodic Transfer Interrupt . 16-140 16.10.8 Interrupt OUT Data Transfers Using Periodic Transfer Interrupt . . 16-146 16.11 Device Programming in Scatter-Gather DMA Mode .
Page 26: Table 12-9 Table
XMC4500 XMC4000 Family Table of Contents 16.12.4 B-Device Host Negotiation Protocol ..... . . 16-217 16.13 Clock Gating Programming Model ......16-218 16.13.1 Host Mode Suspend and Resume With Clock Gating .
Page 27: Table 13-2 Table
XMC4500 XMC4000 Family Table of Contents 17.2.2.6 Protocol-specific Events and Interrupts ....17-22 17.2.3 Operating the Input Stages ....... 17-22 17.2.3.1 General Input Structure .
Page 28: Table 13-6 Table
XMC4500 XMC4000 Family Table of Contents 17.3.3.4 Collision Detection ........17-60 17.3.3.5 Pulse Shaping .
Page 29 XMC4500 XMC4000 Family Table of Contents 17.4.4.2 End-of-Frame Control ....... . . 17-96 17.4.5 SSC Protocol Registers .
Page 30 XMC4500 XMC4000 Family Table of Contents 17.6.1.4 Connection of External Audio Components ....17-136 17.6.2 Operating the IIS ........17-137 17.6.2.1 Frame Length and Word Length Configuration .
Page 31 XMC4500 XMC4000 Family Table of Contents 17.11.6.1 Fractional Divider Register ......17-177 17.11.6.2 Baud Rate Generator Register .
Page 32: Table 16-1 Table
XMC4500 XMC4000 Family Table of Contents 18.3.3.5 CAN Node Interrupts ........18-21 18.3.4 Message Object List Structure .
Page 33: Table 16-3 Table
XMC4500 XMC4000 Family Table of Contents 18.8.2.3 Connections to USIC Inputs ......18-123 Versatile Analog-to-Digital Converter (VADC) ....19-1 19.1 Overview .
Page 34: Table 16-5 Table
XMC4500 XMC4000 Family Table of Contents 19.13.4 Arbitration and Source Registers ......19-68 19.13.5 Channel Control Registers .
Page 35: Table 16-7 Table
XMC4500 XMC4000 Family Table of Contents 21.1.1 Features ..........21-1 21.1.2 Block Diagram .
Page 36: Table 17-1 Table
XMC4500 XMC4000 Family Table of Contents 22.2.4 Starting/Stopping the Timer ....... 22-12 22.2.5 Counting Modes .
Page 37: Table 17-3 Table
XMC4500 XMC4000 Family Table of Contents 22.8.2 CCU41 Pins ......... . 22-136 22.8.3 CCU42 pins .
Page 38: Table 17-5 Table
XMC4500 XMC4000 Family Table of Contents 23.2.14.3 PWM Dither ......... 23-79 23.2.14.4 Capture Mode Usage .
Page 39: Table 17-7 Table
XMC4500 XMC4000 Family Table of Contents 24.5.3 Power ..........24-34 24.6 Initialization and System Dependencies .
Page 40 XMC4500 XMC4000 Family Table of Contents 26.2.1 Reset Types and Corresponding Boot Modes ....26-3 26.2.2 Initial Boot Sequence ........26-4 26.2.3 Boot Mode Selection .
Page 41 XMC4500 XMC4000 Family Table of Contents 27.6.1 Internal pull-up and pull-down on JTAG pins ....27-15 27.6.2 Debug Connector ........27-16 Reference Manual L-34 V1.6, 2016-07...
Page 42 Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions of those documents. Related Documentation The following documents are referenced: ®...
Page 43 XMC4500 XMC4000 Family About this Document • Portions of ETH, USB and GPDMA chapter Copyright © 2009, 2010 by Synopsys, Inc. All rights reserved. Used with permission. Text Conventions This document uses the following naming conventions: • Functional units of the device are given in plain UPPER CASE. For example: “The USIC0 unit supports…”.
Page 44 XMC4500 XMC4000 Family About this Document 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is 1,000,000 • Data format quantities are defined as follows: – Byte = 8-bit quantity –...
Page 45 XMC4500 XMC4000 Family About this Document Table 2 Register Access Modes (cont’d) Symbol Description Indicates that an access to this address range generates a Bus Error. Indicates that no Bus Error is generated when accessing this address range. Reserved Bits Register bit fields named Reserved or 0 indicate unimplemented functions with the following behavior: •...
Page 46 XMC4500 XMC4000 Family About this Document Event Request Unit Ethernet Unit Flexible CRC Engine Flash Command State Machine Flash Interface and Control Module Floating Point Unit GPDMA General Purpose Direct Memory Access GPIO General Purpose Input/Output Human-Machine Interface HRPWM High Resolution PWM Inter Integrated Circuit (also known as I Inter-IC Sound Interface Input / Output...
Page 47 XMC4500 XMC4000 Family About this Document Real Time Clock System Control Unit SDMMC Secure Digital / Multi Media Card (Interface) SDRAM Synchronous Dynamic Random Access Memory Special Function Register Serial Peripheral Interface SRAM Static RAM Service Request Synchronous Serial Channel Startup Software UART Universal Asynchronous Receiver Transmitter...
Page 48: Introduction
XMC4500 XMC4000 Family Introduction Introduction Reference Manual V1.6, 2016-07 Subject to Agreement on the Use of Product Information...
Page 49: Overview
Overview The XMC4500 series devices combine the extended functionality and performance of the ARM Cortex-M4 core with powerful on-chip peripheral subsystems and on-chip memory units. The following key features are available in the XMC4500 series devices: CPU Subsystem • CPU Core –...
Page 50 XMC4500 XMC4000 Family Introduction Communication Peripherals • Ethernet MAC module capable of 10/100 Mbit/s transfer rates • Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY • Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with three nodes, 64 message objects, data rate up to 1 Mbit/s •...
Page 51: Block Diagram
Note: For details about package availability for a particular derivative please check the datasheet. For information on available delivery options for assembly support and general package see http://www.infineon.com/packages 1.1.1 Block Diagram The diagram below shows the functional blocks and their basic connectivity within the XMC4500 System.
Page 52: Cpu Subsystem
XMC4500 XMC4000 Family Introduction CPU Subsystem The XMC4500 system core consists of the CPU (including FPU and MPU) and the memory interface blocks for program and data memories (including PMU). Central Processing Unit (CPU) The Cortex-M4 processor is built on a high-performance processor core with a 3-stage pipelined Harvard architecture, making it ideal for demanding embedded applications.
Page 53: On-Chip Memories
XMC4500 XMC4000 Family Introduction Direct Memory Access (GPDMA) The GPDMA is a highly configurable DMA controller that allows high-speed data transfers between peripherals and memories. Complex data transfers can be done with minimal intervention of the processor, keeping the CPU resources free for other operations.
Page 54: Communication Peripherals
XMC4500 XMC4000 Family Introduction Code RAM (PSRAM) The Code RAM is intended for user code or Operating System data storage. The memory is accessed via the Bus Matrix and provides zero-wait-state access for the CPU for code execution or data access. System RAM (DSRAM1) The System RAM is intended for general user data storage.
Page 55 XMC4500 XMC4000 Family Introduction • ROMs, EPROMs • NOR and NAND flash devices • Static RAMs and PSRAMs • PC133/100 compatible SDRAM • Burst FLASH Ethernet MAC (ETH) The Ethernet MAC (ETH) is a major communication peripheral that supports 10/100 Mbit/s data transfer rates in compliance with the IEEE 802.3-2002 standard. The ETH may be used to implement Internet connected applications using IPv4 and IPv6.
Page 56: Analog Frontend Peripherals
XMC4500 XMC4000 Family Introduction for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer. Analog Frontend Peripherals The XMC4500 hosts a number of interfaces to connect to the analog world. Analog to Digital Converter (VADC) The Versatile Analog-to-Digital Converter module consists of four independent kernel groups which operate according to the successive approximation principle (SAR).
Page 57: Industrial Control Peripherals
XMC4500 XMC4000 Family Introduction channels. Additionally an offset can be added and the amplitude can be scaled. Several time trigger sources are possible. Industrial Control Peripherals Core components needed for motion and motor control, power conversion and other time based applications. Capture/Compare Unit 4 (CCU4) The CCU4 peripheral is a major component for systems that need general purpose timers for signal monitoring/conditioning and Pulse Width Modulation (PWM) signal...
Page 58 XMC4500 XMC4000 Family Introduction the On-Chip Debug Support system can be controlled by the CPU, e.g. by a monitor program. Reference Manual 1-10 V1.6, 2016-07 Architectural Overview, V1.1 Subject to Agreement on the Use of Product Information...
Page 59 XMC4500 XMC4000 Family CPU Subsystem CPU Subsystem Reference Manual V1.6, 2016-07 Subject to Agreement on the Use of Product Information...
Page 60: Central Processing Unit (Cpu)
XMC4500 XMC4000 Family Central Processing Unit (CPU) Central Processing Unit (CPU) The XMC4500 features the ARM Cortex-M4 processor. A high performance 32-bit processor designed for the microcontroller market. This CPU offers significant benefits to users, including: • outstanding processing performance combined with fast interrupt handling •...
Page 61: Features
XMC4500 XMC4000 Family Central Processing Unit (CPU) NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs.
Page 62 XMC4500 XMC4000 Family Central Processing Unit (CPU) Memory Protection Unit The MPU improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region. Debug Solution The XMC4500 implements a complete hardware debug solution. •...
Page 63: Programmers Model
XMC4500 XMC4000 Family Central Processing Unit (CPU) System Level Interfaces ® The Cortex-M4 processor provides a code, data and system interface using AMBA technology to provide high speed, low latency accesses. Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks.
Page 64: Table 6-3 Table
XMC4500 XMC4000 Family Central Processing Unit (CPU) location. The processor implements two stacks, the main stack and the process stack, with a pointer for each held in independent registers, see Stack Pointer on Page 2-8. In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see CONTROL register on Page 2-15.
Page 65: Core Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.2.3 Core Registers Low registers General-purpose registers High registers ‡ ‡ ‡ Stack Pointer SP (R13) Banked version of SP Link Register LR (R14) Program Counter PC (R15) Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI...
Page 66: Table 2-2 Table
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-2 Core register set summary (cont’d) Name Type Required Reset value Description privilege Privileged 01000000 Program Status Register on Page 2-9 ASPR Either Unknown Application Program Status Register on Page 2-9 IPSR Privileged 00000000 Interrupt Program Status...
Page 67 XMC4500 XMC4000 Family Central Processing Unit (CPU) Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: • 0 = Main Stack Pointer (MSP). This is the reset value. •...
Page 68 XMC4500 XMC4000 Family Central Processing Unit (CPU) Program Counter Reset Value: 0000 0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE Field Bits...
Page 69 XMC4500 XMC4000 Family Central Processing Unit (CPU) APSR Application Program Status Register Reset Value: XXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N Z C V Q GE[3:0] rw rw rw rw rw...
Page 70 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description ISR_NUMBER [8:0] Number of the current exception Thread mode Reserved HardFault MemManage BusFault UsageFault Reserved Reserved Reserved Reserved SVCall Reserved for Debug Reserved PendSV SysTick IRQ0 IRQ111 Values > 127 undefined.
Page 71 XMC4500 XMC4000 Family Central Processing Unit (CPU) EPSR Execution Program Status Register Reset Value: 0100 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICI/IT T ICI/IT Field...
Page 72 XMC4500 XMC4000 Family Central Processing Unit (CPU) • restoration from the stacked xPSR value on an exception return • bit[0] of the vector value on an exception entry or reset. Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See Lockup on Page 2-39 for more information.
Page 73 XMC4500 XMC4000 Family Central Processing Unit (CPU) Fault Mask Register The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). See the register summary in Table 2-2 Page 2-6 for its attributes. FAULTMASK Fault Mask Register Reset Value: 0000 0000 Field Bits Type Description...
Page 74 XMC4500 XMC4000 Family Central Processing Unit (CPU) BASEPRI Base Priority Mask Register Reset Value: 0000 0000 BASEPRI Field Bits Type Description BASEPRI [7:0] Priority mask bits no effect others, defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI.
Page 75 XMC4500 XMC4000 Family Central Processing Unit (CPU) CONTROL CONTROL register Reset Value: 0000 0000 nPRI Field Bits Type Description nPRIV Thread mode privilege level Privileged Unprivileged SPSEL Currently active stack pointer In Handler mode this bit reads as zero and ignores writes.
Page 76: Exceptions And Interrupts
XMC4500 XMC4000 Family Central Processing Unit (CPU) By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either: • use the MSR instruction to set the Active stack pointer bit to 1. •...
Page 77: Cmsis Functions
XMC4500 XMC4000 Family Central Processing Unit (CPU) CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals.
Page 78 XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-4 CMSIS functions to generate some Cortex-M4 instructions (cont’d) Instruction CMSIS function REVSH uint32_t __REVSH(uint32_t int value) RBIT uint32_t __RBIT(uint32_t int value) void __SEV(void) void __WFE(void) void __WFI(void) The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 2-5 CMSIS functions to access the special registers...
Page 79: Memory Model
XMC4500 XMC4000 Family Central Processing Unit (CPU) Memory Model This section describes the processor memory map and the behavior of memory accesses. The processor has a fixed default memory map that provides up to 4GB of addressable memory. The memory map is: 0xFFFFFFFF Vendor-specific 511MB...
Page 80: Memory System Ordering Of Memory Accesses
XMC4500 XMC4000 Family Central Processing Unit (CPU) attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: Normal The processor can re-order transactions for efficiency, or perform speculative reads. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.
Page 81: Behavior Of Memory Accesses
XMC4500 XMC4000 Family Central Processing Unit (CPU) Strongly- Normal Device ordered access access access Normal access Device access < < Strongly-ordered access - < < < Figure 2-4 Ordering of Memory Accesses Where: • “-” Means that the memory system does not guarantee the ordering of the accesses. •...
Page 82: Software Ordering Of Memory Accesses
XMC4500 XMC4000 Family Central Processing Unit (CPU) 1) See Memory regions, types and attributes on Page 2-20 for more information. The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously.
Page 83: Memory Endianness
XMC4500 XMC4000 Family Central Processing Unit (CPU) MPU programming Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions. 2.3.5 Memory Endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero.
Page 84 XMC4500 XMC4000 Family Central Processing Unit (CPU) A Store-Exclusive instruction Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: 0 it indicates that the thread or process gained exclusive access to the memory, and the write succeeds, 1 it indicates that the thread or process did not gain exclusive access to the memory, and no write was performed.
Page 85: Programming Hints For The Synchronization Primitives
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.3.7 Programming Hints for the Synchronization Primitives ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for generation of these instructions: Table 2-7 CMSIS functions for exclusive access instructions Instruction CMSIS function LDREX...
Page 86: Exception Types
XMC4500 XMC4000 Family Central Processing Unit (CPU) Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active An exception that is being serviced by the processor but has not completed.
Page 87 XMC4500 XMC4000 Family Central Processing Unit (CPU) BusFault A BusFault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. UsageFault A UsageFault is an exception that occurs because of a fault related to instruction execution.
Page 88: Exception Handlers
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-8 Properties of the different exception types (cont’d) Exception Exception Priority Vector Activation number number type address or offset BusFault Configurable 0x00000014 Synchronous when precise, asynchronous when imprecise UsageFault Configurable 0x00000018 Synchronous 7-10 Reserved SVCall...
Page 89: Vector Table
XMC4500 XMC4000 Family Central Processing Unit (CPU) Interrupt Service Interrupts IRQ0 to IRQ111 are the exceptions handled by ISRs. Routines (ISRs) Fault handlers HardFault, MemManage fault, UsageFault, and BusFault are fault exceptions handled by the fault handlers. System handlers NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system handlers.
Page 90: Exception Priorities
XMC4500 XMC4000 Family Central Processing Unit (CPU) On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000400 to 0x3FFFFC00, see Vector Table Offset Register on Page 2-63.
Page 91: Exception Entry And Return
XMC4500 XMC4000 Family Central Processing Unit (CPU) For information about splitting the interrupt priority fields into group priority and subpriority, see Application Interrupt and Reset Control Register on Page 2-64. 2.5.7 Exception Entry and Return Descriptions of exception handling use the following terms: Preemption When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority...
Page 92 XMC4500 XMC4000 Family Central Processing Unit (CPU) Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.
Page 93 XMC4500 XMC4000 Family Central Processing Unit (CPU) • the processor is in Thread mode • the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers, see Exception mask registers on Page...
Page 94 XMC4500 XMC4000 Family Central Processing Unit (CPU) Pre-IRQ top of stack {aligner} FPSCR Pre-IRQ top of stack {aligner} Decreasing memory address IRQ top of stack IRQ top of stack Exception frame with Exception frame without floating-point storage floating-point storage Figure 2-7 Exception stack frame Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
Page 95: Fault Handling
XMC4500 XMC4000 Family Central Processing Unit (CPU) If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. Exception return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:...
Page 96: Fault Types
XMC4500 XMC4000 Family Central Processing Unit (CPU) – an instruction fetch or vector table load – a data access. • an internally-detected error such as an undefined instruction • attempting to execute an instruction from a memory region marked as Non- Executable (XN).
Page 97: Fault Escalation And Hard Faults
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-10 Faults (cont’d) Fault Handler Bit name Fault status register Bus error: BusFault during exception STKERR BusFault Status stacking Register on Page 2-74 during exception UNSTKERR unstacking during instruction IBUSERR prefetch during lazy floating-point LSPERR state preservation Precise data bus error...
Page 98: Fault Status Registers And Fault Address Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) • A fault handler causes the same kind of fault as the one it is servicing. This escalation to HardFault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. •...
Page 99: Power Management
XMC4500 XMC4000 Family Central Processing Unit (CPU) • an NMI occurs • it is halted by a debugger Note: If lockup state occurs from the NMI handler a subsequent NMI does not cause the processor to leave lockup state. Power Management The Cortex-M4 processor sleep modes reduce power consumption: •...
Page 100: Wakeup From Sleep Mode
XMC4500 XMC4000 Family Central Processing Unit (CPU) asserted, or a processor in the system has executed an SEV instruction, see SEV on page 3-166. Software cannot access this register directly. Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of all exception handlers it returns to Thread mode and immediately enters sleep mode.
Page 101: System Control Block
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.7.4 Power Management Programming Hints ISO/IEC C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following functions for these instructions: void __WFE(void) // Wait for Event void __WFI(void) // Wait for Interrupt Private Peripherals The following sections are the reference material for the ARM Cortex-M4 core peripherals.
Page 102: System Control Block Design Hints And Tips
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.8.2.1 System control block design hints and tips Ensure software uses aligned accesses of the correct size to access the system control block registers: • except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses •...
Page 103: Level-Sensitive And Pulse Interrupts
XMC4500 XMC4000 Family Central Processing Unit (CPU) • Grouping of priority values into group priority and subpriority fields. • Interrupt tail-chaining. • An external Non-maskable interrupt (NMI) The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead.
Page 104: Nvic Design Hints And Tips
XMC4500 XMC4000 Family Central Processing Unit (CPU) – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR.
Page 105: Memory Protection Unit (Mpu)
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-13 CMSIS functions for NVIC control (cont’d) CMSIS interrupt control function Description Cortex-M Portable Disables IRQn. void NVIC_DisableIRQ( IRQn_t IRQn) Return IRQ-Number (true) if uint32_t NVIC_GetPendingIRQ( IRQn is pending. IRQn_t IRQn) Set IRQn pending. void NVIC_SetPendingIRQ( IRQn_t IRQn) Clear IRQn pending.
Page 106 XMC4500 XMC4000 Family Central Processing Unit (CPU) The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines: • eight separate memory regions, 0-7 • a background region When memory regions overlap, a memory access is affected by the attributes of the region with the highest number.
Page 107: Mpu Access Permission Attributes
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.8.5.1 MPU Access Permission Attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault.
Page 108 XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-16 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7. Table 2-16 Cache policy for memory attribute encoding Encoding, AA or BB Corresponding cache policy Non-cacheable Write back, write and read allocate Write through, no write allocate...
Page 109: Mpu Mismatch
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-18 AP encoding (cont’d) AP[2:0] Privileged Unprivileged Description permissions permissions Unpredictable Unpredictable Reserved No access Reads by privileged software only Read only, by privileged or unprivileged software Read only, by privileged or unprivileged software 2.8.5.2 MPU Mismatch...
Page 110 XMC4500 XMC4000 Family Central Processing Unit (CPU) R0,=MPU_RNR 0xE000ED98, region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ;...
Page 111 XMC4500 XMC4000 Family Central Processing Unit (CPU) STM R0, {R1-R3} ; Region Number, address, attribute, size and enable You can do this in two words for pre-packed information. This means that the MPU_RBAR contains the required region number and had the VALID bit set to 1, see MPU Region Base Address Register on Page 2-96.
Page 112: Mpu Design Hints And Tips
XMC4500 XMC4000 Family Central Processing Unit (CPU) Region 2, with Offset from subregions base address 512KB 448KB 384KB 320KB 256KB Region 1 192KB 128KB Disabled subregion 64KB Disabled subregion Base address of both regions Figure 2-8 Example of SRD use 2.8.5.4 MPU Design Hints and Tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a...
Page 113: Enabling The Fpu
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.8.6.1 Enabling the FPU The FPU is disabled from reset. You must enable it before you can use any floating-point instructions. The Example shows an example code sequence for enabling the FPU in both privileged and user modes.
Page 114: Table 2-6 Table
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-19 Registers Overview (cont’d) Register Register Long Name Offset Access Mode Description Short Name Address Read Write Configuration and PV, 32 PV, 32 Page 2-68 Control Register SHPR1 System Handler Priority PV, 32 PV, 32 Page 2-71 Register 1 SHPR2...
Page 115 XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-19 Registers Overview (cont’d) Register Register Long Name Offset Access Mode Description Short Name Address Read Write SYST_CALIB SysTick Calibration PV, 32 - Page 2-86 Value Register NVIC NVIC_ISER0- Interrupt Set-enable PV, 32 PV, 32 Page 2-87 NVIC_ISER3 Registers...
Page 116 XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-19 Registers Overview (cont’d) Register Register Long Name Offset Access Mode Description Short Name Address Read Write MPU_RBAR_A2 Alias of RBAR, see PV, 32 PV, 32 Page 2-96 MPU Region Base Address Register MPU_RASR_A2 Alias of RASR, see PV, 32 PV, 32...
Page 117: Scs Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.9.1 SCS Registers Auxiliary Control Register The ACTLR provides disable bits for the following processor functions: • IT folding • write buffer use for accesses to the default memory map • interruption of multi-cycle instructions. By default this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally require modification.
Page 118 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description DISDEFWBUF Disable write buffer When set to 1, disables write buffer use during default memory map accesses. This causes all BusFaults to be precise BusFaults but decreases performance because any store to memory must complete before the processor can execute the next instruction.
Page 119 XMC4500 XMC4000 Family Central Processing Unit (CPU) CPUID Base Register The CPUID register contains the processor part number, version, and implementation information. CPUID Reset Value: 410F C241 CPUID Base Register (E000 ED00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Implementer Variant Constant...
Page 120 XMC4500 XMC4000 Family Central Processing Unit (CPU) ICSR Interrupt Control and State Register (E000 ED04 Reset Value: 0000 0000 ISRP VECTPEN ENDI DING VECTPENDING VECTACTIVE Field Bits Type Description VECTACTIVE [8:0] Active exception number Thread mode Nonzero = The exception number of the currently active exception.
Page 121 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description VECTPENDING [17:12] r Vector Pending Indicates the exception number of the highest priority pending enabled exception: no pending exceptions Nonzero = the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
Page 122 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description PENDSVSET PendSV set-pending bit Write: no effect Read: PendSV exception is not pending Write: changes PendSV exception state to pending Read: PendSV exception is pending Writing 1 to this bit is the only way to set the PendSV exception state to pending.
Page 123 XMC4500 XMC4000 Family Central Processing Unit (CPU) VTOR Vector Table Offset Register (E000 ED08 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBLOFF Field Bits...
Page 124 XMC4500 XMC4000 Family Central Processing Unit (CPU) AIRCR Application Interrupt and Reset Control Register (E000 ED0C Reset Value: FA05 0000 VECTKEY ENDI PRIGROUP TIVE Field Bits Type Description VECTRESET Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable VECTCLRACTIVE 1...
Page 125 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description VECTKEY [31:16] rw Register key Read: = VECTKEY, reads as 0xFA05 Write: = VECTKEYSTAT, On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. [14:11], Reserved [7:3] Read as 0; should be written with 0. Binary point The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the Interrupt Priority Registers into separate group priority and subpriority fields.
Page 126 XMC4500 XMC4000 Family Central Processing Unit (CPU) System Control Register The SCR controls features of entry to and exit from low power state. System Control Register (E000 ED10 Reset Value: 0000 0000 NEXI Field Bits Type Description SLEEPONEXIT Sleep on Exit Indicates sleep-on-exit when returning from Handler mode to Thread mode: do not sleep when returning to Thread mode.
Page 127 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description SEVONPEND Send Event on Pending bit: only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE.
Page 128 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description NONBASETHR Non Base Thread Mode Enable DENA Indicates how the processor enters Thread mode: processor can enter Thread mode only when no exception is active. processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception...
Page 129 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description BFHFNMIGN Bus Fault Hard Fault and NMI Ignore Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated handlers: data bus faults caused by load and store instructions cause a lock-up...
Page 130: Table 2-8 Table
XMC4500 XMC4000 Family Central Processing Unit (CPU) Table 2-21 System fault handler priority fields (cont’d) Handler Field Register description PendSV PRI_14 System Handler Priority Register 3 on Page 2-72 SysTick PRI_15 Each PRI_N field is 8 bits wide, but the XMC4500 implements only bits[7:2] of each field, and bits[1:0] read as zero and ignore writes.
Page 131 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description PRI_11 [31:24] rw Priority of system handler 11, SVCall [23:0] Reserved Read as 0; should be written with 0. System Handler Priority Register 3 SHPR3 System Handler Priority Register 3 (E000 ED20 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 132 XMC4500 XMC4000 Family Central Processing Unit (CPU) SHCSR System Handler Control and State Register (E000 ED24 Reset Value: 0000 0000 TICK ITOR Field Bits Type Description MEMFAULTACT MemManage exception active bit Reads as 1 if exception is active. BUSFAULTACT BusFault exception active bit Reads as 1 if exception is active.
Page 133 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description BUSFAULTPENDED BusFault exception pending bit Reads as 1 if exception is pending. SVCALLPENDED SVCall pending bit Reads as 1 if exception is pending. MEMFAULTENA MemManage enable bit Set to 1 to enable. BUSFAULTENA BusFault enable bit Set to 1 to enable.
Page 134 XMC4500 XMC4000 Family Central Processing Unit (CPU) The flags in the BFSR indicate the cause of a bus access fault. The UFSR indicates the cause of a UsageFault. 16 15 Bus Fault Status Memory Management Usage Fault Status Register Register Fault Status Register UFSR BFSR...
Page 135 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description IACCVIOL Instruction access violation flag no instruction access violation fault the processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
Page 136 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description MLSPERR MemManage fault during floating point lazy state preservation No MemManage fault occurred during floating- point lazy state preservation A MemManage fault occurred during floating- point lazy state preservation MMARVALID MemManage Fault Address Register (MMFAR) valid flag...
Page 137 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description IMPRECISERR Imprecise data bus error no imprecise data bus error a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.
Page 138 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description LSPERR BusFault during floating point lazy state preservation No bus fault occurred during floating-point lazy state preservation. A bus fault occurred during floating-point lazy state preservation BFARVALID BusFault Address Register (BFAR) valid flag value in BFAR is not a valid fault address BFAR holds a valid fault address.
Page 139 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description INVPC Invalid PC load UsageFault caused by an invalid PC load by EXC_RETURN: no invalid PC load UsageFault the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value.
Page 140 XMC4500 XMC4000 Family Central Processing Unit (CPU) HardFault Status Register The HFSR gives information about events that activate the HardFault handler. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0. The bit assignments are: HFSR HardFault Status Register (E000 ED2C...
Page 141 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description DEBUGEVT Reserved for Debug use When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable [29:2], Reserved Read as 0; should be written with 0. Note: The HFSR bits are sticky.
Page 142 XMC4500 XMC4000 Family Central Processing Unit (CPU) BusFault Address Register The BFAR contains the address of the location that generated a BusFault. BFAR BusFault Address Register (E000 ED38 Reset Value: XXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRESS Field Bits...
Page 143: Systick Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) Each AFSR bit maps directly to an AUXFAULT input of the processor, and a single-cycle HIGH signal on the input sets the corresponding AFSR bit to one. It remains set to 1 until you write 1 to the bit to clear it to zero.
Page 144 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description CLKSOURCE Clock source STDBY COUNTFLAG Counter Flag Returns 1 if timer counted to 0 since last time this was read. [31:17], Reserved [15:3] Read as 0; should be written with 0. When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR register and then counts down.
Page 145 XMC4500 XMC4000 Family Central Processing Unit (CPU) 2. The RELOAD value is calculated according to its use. For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. SysTick Current Value Register The SYST_CVR register contains the current value of the SysTick counter.
Page 146: Nvic Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description TENMS [23:0] Ten Milliseconds Reload Value Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. SKEW Ten Milliseconds Skewed Indicates whether the TENMS value is exact:...
Page 147 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description SETENA [31:0] Interrupt set-enable bits Write: no effect Read: interrupt disabled Write: enable interrupt Read: interrupt enabled If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
Page 148 XMC4500 XMC4000 Family Central Processing Unit (CPU) Interrupt Set-pending Registers The NVIC_ISPRx registers force interrupts into the pending state, and show which interrupts are pending. NVIC_ISPRx (x=0-3) Interrupt Set-pending Register x (E000 E200 + 4*x) Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SETPEND Field Bits...
Page 149 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description CLRPEND [31:0] Interrupt set-pending bits. Write: no effect Read: interrupt is not pending Write: removes pending state an interrupt Read: interrupt is pending Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
Page 150 XMC4500 XMC4000 Family Central Processing Unit (CPU) 24 23 16 15 IPR27 PRI_111 PRI_110 PRI_109 PRI_108 IPRn PRI_4n+3 PRI_4n+2 PRI_4n+1 PRI_4n IPR0 PRI_3 PRI_2 PRI_1 PRI_0 Figure 2-10 Interrupt Priority Register NVIC_IPRx (x=0-27) Interrupt Priority Register x (E000 E400 + 4*x) Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI_3...
Page 151 XMC4500 XMC4000 Family Central Processing Unit (CPU) • the corresponding IPR number n, see Figure 2-10 Page 2-917, is given by n = m DIV 4 • the byte offset of the required Priority field in this register is m MOD 4, where: –...
Page 152: Mpu Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.9.4 MPU Registers MPU Type Register The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU_TYPE MPU Type Register (E000 ED90 Reset Value: 0000 0800 IREGION DREGION Field...
Page 153 XMC4500 XMC4000 Family Central Processing Unit (CPU) MPU_CTRL MPU Control Register (E000 ED94 Reset Value: 0000 0000 PRIV Field Bits Type Description ENABLE Enable MPU MPU disabled MPU enabled. HFNMIENA Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers When the MPU is enabled: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the...
Page 154 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description PRIVDEFENA Enables privileged software access to the default memory map If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault.
Page 155 XMC4500 XMC4000 Family Central Processing Unit (CPU) MPU Region Number Register The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers. MPU_RNR Reset Value: 0000 0000 MPU Region Number Register (E000 ED98 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGION Field Bits...
Page 156 XMC4500 XMC4000 Family Central Processing Unit (CPU) MPU_RBAR MPU Region Base Address Register (E000 ED9C Reset Value: 0000 0000 MPU_RBAR_A1 MPU Region Base Address Register A1 (E000 EDA4 Reset Value: 0000 0000 MPU_RBAR_A2 MPU Region Base Address Register A2 (E000 EDAC Reset Value: 0000 0000 MPU_RBAR_A3 MPU Region Base Address Register A3...
Page 157 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description VALID MPU Region Number valid bit Write: MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field the processor: - updates the value of the MPU_RNR to the value of the REGION field...
Page 158 XMC4500 XMC4000 Family Central Processing Unit (CPU) MPU_RASR MPU Region Attribute and Size Register (E000 EDA0 Reset Value: 0000 0000 MPU_RASR_A1 MPU Region Attribute and Size Register A1 (E000 EDA8 Reset Value: 0000 0000 MPU_RASR_A2 MPU Region Attribute and Size Register A2 (E000 EDB0 Reset Value: 0000 0000 MPU_RASR_A3...
Page 159 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description Memory access attribute Table 2-15 onPage 2-48. Shareable bit Table 2-15 onPage 2-48. [21:19] rw Memory access attribute Table 2-15 onPage 2-48. [26:24] rw Access permission field Table 2-18 Page 2-49.
Page 160: Fpu Registers
XMC4500 XMC4000 Family Central Processing Unit (CPU) 2.9.5 FPU Registers Coprocessor Access Control Register The CPACR register specifies the access privileges for coprocessors. CPACR Coprocessor Access Control Register (E000 ED88 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP11 CP10 Field Bits...
Page 161 XMC4500 XMC4000 Family Central Processing Unit (CPU) Floating-point Context Control Register The FPCCR register sets or returns FPU control data. FPCCR Floating-point Context Control Register (E000 EF34 Reset Value: C000 0000 Field Bits Type Description LSPACT Lazy State Preservation Active Lazy state preservation is not active.
Page 162 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description MMRDY MemManage Ready MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
Page 163 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description [29:9], Reserved 7, 2 Read as 0; should be written with 0. Floating-point Context Address Register The FPCAR register holds the location of the unpopulated floating-point register space allocated on an exception stack frame. FPCAR Floating-point Context Address Register (E000 EF38...
Page 164 XMC4500 XMC4000 Family Central Processing Unit (CPU) Floating-point Status Control Register The FPSCR register provides all necessary User level control of the floating-point system. FPSCR Floating-point Status Control Register Reset Value: XXXX XXXX AHP DN RMode IXC UFC OFC DZC IOC Field Bits Type Description...
Page 165 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description RMode [23:22] rw Rounding Mode control field Round to Nearest (RN) mode Round towards Plus Infinity (RP) mode Round towards Minus Infinity (RM) mode Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions.
Page 166 XMC4500 XMC4000 Family Central Processing Unit (CPU) Floating-point Default Status Control Register The FPDSCR register holds the default values for the floating-point status control data. FPDSCR Floating-point Default Status Control Register (E000 EF3C Reset Value: 0000 0000 AHP DN RMode Field Bits Type Description...
Page 167 XMC4500 XMC4000 Family Central Processing Unit (CPU) MVFR0 Media and FP Feature Register 0 (E000 EF40 Reset Value: 1011 0021 ROUNDING_MODES SHORT_VECTORS SQUARE_ROOT DIVIDE EXCEPTION_TRAP DOUBLE_PRECISION SINGLE_PRECISION A_SIMD_REGISTERS Field Bits Type Description ROUNDING_MODES [31:28] r Indicates the rounding modes supported by the FP floating-point hardware.
Page 168 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description SINGLE_PRECISION [7:4] Indicates the hardware support for FP single-precision operations. : Supported (Instruction to load a single- precision floating-point constant, and conversions between single-precision and fixed-point values is available). A_SIMD_REGISTERS [3:0] Indicates the size of the FP register bank.
Page 169 XMC4500 XMC4000 Family Central Processing Unit (CPU) Field Bits Type Description D_NAN_MODE [7:4] Indicates whether the FP hardware implementation supports only the Default NaN mode. : Hardware supports propagation of NaN values. FTZ_MODE [3:0] Indicates whether the FP hardware implementation supports only the Flush-to- Zero mode of operation.
Page 170: Bus System
XMC4500 XMC4000 Family Bus System Bus System The XMC4500 is targeted for use in embedded systems. Therefore the key features are timing determinism and low latency on real time events. Bus bandwidth is required particularly for communication peripherals. The bus system will therefore provide: •...
Page 171 XMC4500 XMC4000 Family Bus System arbitration scheme enables optimal access conflicts resolution resulting in improved system stability and real time behavior. Masters System System Ethernet DMA0 DMA1 Flash & BROM PSRAM DSRAM 1 DSRAM 2 Peripherals 0 (PBA0) Peripherals 1 (PBA1) Peripherals 2 (PBA2)
Page 172 XMC4500 XMC4000 Family Bus System Table 3-1 Access Priorities per Slave GPDMA0 GPDMA1 PMU/FLASH PSRAM DSRAM1 DSRAM2 PBA0 PBA1 PBA2 1) Lower number means higher priority The DSRAM priorities are choosen to support the application dependance of the data memories: •...
Page 173: Service Request Processing
XMC4500 XMC4000 Family Service Request Processing Service Request Processing A hardware pulse or level change is called Service Request (SR) in an XMC4500 system. Service Requests are the fastest way to send trigger “messages” between connected on-chip resources. An SR can generate any of the following requests •...
Page 174: Block Diagram
XMC4500 XMC4000 Family Service Request Processing • DMA Line Router (DLR) – Routing and processing of DMA requests 4.1.2 Block Diagram The shaded components shown in Figure 4-1 are described in this chapter. On-Chip Unit PORTS Outputs Interconnections On-Chip Unit NVIC PORTS Inputs...
Page 175: Service Request Distribution
XMC4500 XMC4000 Family Service Request Processing Service Request Distribution The following figure shown an example of how a service request can be distributed concurrently. To support the concurrent distribution to multiple receivers, the receiving modules are capable to enable/disable incoming requests. NVIC (Interrupt) (DMA Request)
Page 176: Interrupt Service Requests
XMC4500 XMC4000 Family Service Request Processing Table 4-2 Interrupt and DMA services per Module Modules Request NVIC DLR/GPDMA Type Sources VADC Pulse Pulse Pulse CCU40-3 Pulse CCU80-1 Pulse POSIF0-1 Pulse Pulse USIC0-2 Pulse LEDTS0 Pulse Pulse PMU0/Flash Pulse GPDMA0-1 Level Level ERU0-1 Pulse...
Page 177 XMC4500 XMC4000 Family Service Request Processing • One external Non-maskable interrupt (NMI) • Relocatable vector table • Software interrupt generation Level-sensitive and pulse interrupts The NVIC is capable to capture both level-sensitive and pulse interrupts. • A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal.
Page 178 XMC4500 XMC4000 Family Service Request Processing Table 4-3 Interrupt Node assignment (cont’d) Service Request IRQ Number Description VADC.G1SR0 - 22...25 Analog to Digital Converter Group 1 VADC.G1SR3 VADC.G2SR0 - 26...29 Analog to Digital Converter Group 2 VADC.G2SR3 VADC.G3SR0 - 30...33 Analog to Digital Converter Group 3 VADC.G3SR3 DSD.SRM0 -...
Page 179: Dma Line Router (Dlr)
XMC4500 XMC4000 Family Service Request Processing Table 4-3 Interrupt Node assignment (cont’d) Service Request IRQ Number Description USIC1.SR0 - 90...95 Universal Serial Interface Channel (Module 1) USIC1.SR5 USIC2.SR0 - 96...101 Universal Serial Interface Channel (Module 2) USIC2.SR5 LEDTS0.SR0 LED and Touch Sense Control Unit (Module 0) Reserved FCE.SR0 Flexible CRC Engine...
Page 180: Reference Manual
XMC4500 XMC4000 Family Service Request Processing Service Request Subset of DMA capable SR SRSELx.RSy DEMUX Selected SR Transfer Transfer LNEN.LNy Lines 8-11 Lines 0-7 GPDMA1 GPDMA0 Handler OVRCLR.LNy OVRSTAT.LNy SRRAW.DLROVR Figure 4-3 DMA Line Handler For each DMA line the user can assign one service request source from the subset of DMA capable XMC4500 service request sources.
Page 181 XMC4500 XMC4000 Family Service Request Processing If any bit within the DLR_OVRSTAT register is set, a service request is flagged by setting the SCU_SRRAW.DLROVR bit. The DLR unit has the following inputs: Table 4-4 DMA Handler Service Request inputs Service Request # of Inputs Description ERU0.SR1 -...
Page 182: Dma Service Request Source Selection
XMC4500 XMC4000 Family Service Request Processing Table 4-4 DMA Handler Service Request inputs (cont’d) Service Request # of Inputs Description USIC0.SR0 - Universal Serial Interface Channel (Module 0) USIC0.SR1 USIC1.SR0 - Universal Serial Interface Channel (Module 1) USIC1.SR1 USIC2.SR0 - Universal Serial Interface Channel (Module 2) USIC2.SR3 4.4.2...
Page 183 XMC4500 XMC4000 Family Service Request Processing Table 4-5 DMA Request Source Selection (cont’d) DMA Line DMA Request Line Selected by DLR_SRSEL bit field VADC.C0SR1 RS1 = 0001 VADC.G0SR2 RS1 = 0010 VADC.G1SR0 RS1 = 0011 VADC.G2SR2 RS1 = 0100 DAC.SR0 RS1 = 0101 CCU40.SR0 RS1 = 0110...
Page 184 XMC4500 XMC4000 Family Service Request Processing Table 4-5 DMA Request Source Selection (cont’d) DMA Line DMA Request Line Selected by DLR_SRSEL bit field Reserved RS2 = 1111 ERU0.SR2 RS3 = 0000 VADC.C0SR2 RS3 = 0001 VADC.C0SR3 RS3 = 0010 VADC.G1SR1 RS3 = 0011 VADC.G1SR2 RS3 = 0100...
Page 185 XMC4500 XMC4000 Family Service Request Processing Table 4-5 DMA Request Source Selection (cont’d) DMA Line DMA Request Line Selected by DLR_SRSEL bit field VADC.G3SR1 RS4 = 1101 CCU43.SR0 RS4 = 1110 Reserved RS4 = 1111 ERU0.SR1 RS5 = 0000 VADC.G0SR0 RS5 = 0001 VADC.G0SR1 RS5 = 0010...
Page 186 XMC4500 XMC4000 Family Service Request Processing Table 4-5 DMA Request Source Selection (cont’d) DMA Line DMA Request Line Selected by DLR_SRSEL bit field USIC0.SR1 RS6 = 1011 USIC1.SR1 RS6 = 1100 VADC.G3SR0 RS6 = 1101 CCU43.SR1 RS6 = 1110 Reserved RS6 = 1111 ERU0.SR0 RS7 = 0000...
Page 187: Event Request Unit (Eru)
XMC4500 XMC4000 Family Service Request Processing Table 4-5 DMA Request Source Selection (cont’d) DMA Line DMA Request Line Selected by DLR_SRSEL bit field ERU0.SR1 RS9 = 0000 VADC.C0SR1 RS9 = 0001 VADC.G3SR1 RS9 = 0010 DSD.SRM1 RS9 = 0011 DAC.SR1 RS9 = 0100 CCU42.SR1 RS9 = 0101...
Page 188: Event Request Select Unit (Ers)
XMC4500 XMC4000 Family Service Request Processing Service Requests Event Service by by Event Sources Action Providers Event Request Unit CAPCOM CAPCOM >1 & & GPIO EVENTS TRIGGERS POSIF POSIF Figure 4-4 Event Request Unit Overview Each ERU unit consists of the following blocks: •...
Page 189: Event Trigger Logic (Etlx)
XMC4500 XMC4000 Family Service Request Processing In addition to the direct choice of either input Ax or Bx or their inverted values, the possible logical combinations for two selected inputs are a logical AND or a logical OR. EXICONx. EXICONx. EXISEL.
Page 190 XMC4500 XMC4000 Family Service Request Processing EXICONx. EXICONx. ETLx Modify Status Flag EXICONx.FL Status to all OGUy clear Flag Detect ERSxO edge event Event ERSx TRx0 to (edge) OGU0 TRx1 to Enable Select OGU1 trigger pulse Trigger Trigger TRx2 to Pulse Output OGU2...
Page 191: Cross Connect Matrix
XMC4500 XMC4000 Family Service Request Processing 4.5.3 Cross Connect Matrix The matrix shown in Figure 4-7 distributes the trigger signals (TRxy) and status signals (EXICONx.FL) from the different ETLx units between the OGUy units. In addition, it receives peripheral trigger signals that can be OR-combined with the ETLx trigger signals in the OGUy units.
Page 192: Output Gating Unit (Oguy)
XMC4500 XMC4000 Family Service Request Processing 4.5.4 Output Gating Unit (OGUy) Each OGUy (y = 0-3) unit combines the available trigger events and status flags from the Input Channels and distributes the results to the system. Figure 4-8 illustrates the logic blocks within an OGUy unit.
Page 193 XMC4500 XMC4000 Family Service Request Processing Each OGUy unit generates 4 output signals that are distributed to the system (not all of them are necessarily used): • ERU_PDOUTy to directly output the pattern match information for gating purposes in other modules (pattern match = 1). •...
Page 194 XMC4500 XMC4000 Family Service Request Processing • Pattern match (EXOCONy.PDR = 1 and ERU_PDOUTy = 1): A pattern match is indicated while all status flags FL that are included in the pattern detection are 1. • Pattern miss (EXOCONy.PDR = 0 and ERU_PDOUTy = 0): A pattern miss is indicated while at least one of the status flags FL that are included in the pattern detection is 0.
Page 195: Service Request Generation
XMC4500 XMC4000 Family Service Request Processing Service Request Generation If any bit within the DLR.DLR_OVRSTAT register is set, a service request is flagged by setting the SCU_SRRAW.DLROVR bit. To clear a request user must program the corresponding bit in the DLR.DLR_OVRCLR register.
Page 196: Registers
XMC4500 XMC4000 Family Service Request Processing 4.10 Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 4-6 Registers Address Space Module Base Address End Address Note 5000 4900 5000 49FF ERU0 5000 4800 5000 48FF ERU1...
Page 197 XMC4500 XMC4000 Family Service Request Processing Table 4-7 (cont’d) Short Name Description Offset Access Mode Description Addr. Read Write EXICON3 ERU External Input 001C U, PV Page 4-31 Control Selection EXOCON0 ERU Output Control 0020 U, PV Page 4-33 Register EXOCON1 ERU Output Control 0024...
Page 198 XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description [31:12] r Reserved Read as 0; should be written with 0. DLR_OVRCLR The DLR_OVRCLR register is used to clear the DLR_OVRSTAT register bits. DLR_OVRCLR Overrun Clear Reset Value: 0000 0000 LN11 LN10 LN9 LN8 LN7 LN6 LN5 LN4 LN3 LN2 LN1 LN0 Field Bits...
Page 199 XMC4500 XMC4000 Family Service Request Processing DLR_LNEN Line Enable Reset Value: 0000 0000 LN11 LN10 LN9 LN8 LN7 LN6 LN5 LN4 LN3 LN2 LN1 LN0 Field Bits Type Description Line x Enable (x = 0-11) Disables the line Enables the line and resets a pending request [31:12] r Reserved Read as 0;...
Page 200 XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description [x*4+3: Request Source for Line x (x = 0-7) x*4] The request source according to Table 4-5 selected for DMA line x.These lines are connected to GPDMA0 DLR_SRSEL1 Service Request Selection 1 Reset Value: 0000 0000 RS11 RS10...
Page 201: Eru Registers
XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description [31:16] r Reserved Read as 0; should be written with 0. 4.10.2 ERU Registers ERU0_EXISEL Event Input Select Reset Value: 0000 0000 ERU1_EXISEL Event Input Select (0000 Reset Value: 0000 0000 EXS3B EXS3A EXS2B...
Page 202 XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description EXS1A [5:4] Event Source Select for A1 (ERS1) This bit field defines which input is selected for A1. Input ERU_1A0 is selected Input ERU_1A1 is selected Input ERU_1A2 is selected Input ERU_1A3 is selected EXS1B [7:6]...
Page 203 XMC4500 XMC4000 Family Service Request Processing ERU0_EXICONx (x=0-3) Event Input Control x + 4*x) Reset Value: 0000 0000 ERU1_EXICONy (y=0-3) Event Input Control y (0010 + 4*y) Reset Value: 0000 0000 Field Bits Type Description Output Trigger Pulse Enable for ETLx This bit enables the generation of an output trigger pulse at TRxy when the selected edge is detected (set condition for the status flag FL).
Page 204 XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description Rising Edge Detection Enable ETLx This bit enables/disables the rising edge event as edge event as set condition for the status flag FL or as possible trigger pulse for TRxy. A rising edge is not considered as edge event A rising edge is considered as edge event Falling Edge Detection Enable ETLx...
Page 205 XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description Input B Negation Select for ERSx This bit selects the polarity for the input B. Input B is used directly Input B is inverted [31:12] r Reserved Read as 0; should be written with 0. ERU0_EXOCONx (x=0-3) Event Output Trigger Control x + 4*x)
Page 206: Interconnects
XMC4500 XMC4000 Family Service Request Processing Field Bits Type Description Pattern Detection Result Flag This bit represents the pattern detection result. A pattern miss is detected A pattern match is detected [5:4] Gating Selection for Pattern Detection Result This bit field defines the gating scheme for the service request generation (relation between the OGU output ERU_PDOUTy and ERU_GOUTy).
Page 207: Eru0 Connections
XMC4500 XMC4000 Family Service Request Processing ERU0 - Select xA[3:0] - Combine IOUTy TRIGGER - Detect - Cross- Connect xB[3:0] - Gate GPDMA PORTS PORTS PORTS NVIC.SRn PORTS ERU1 - Select xA[3:0] TRIGGER IOUTy - Combine - Detect - Cross- Connect xB[3:0] PDOUTy...
Page 208 XMC4500 XMC4000 Family Service Request Processing Table 4-8 ERU0 Pin Connections Global Connected To Description Inputs/Outputs ERU0.0B0 PORTS ERU0.0B1 PORTS ERU0.0B2 PORTS ERU0.0B3 PORTS ERU0.1A0 PORTS ERU0.1A1 SCU.HIB_SR0 ERU0.1A2 PORTS ERU0.1A3 SCU.G0ORCOUT7 ERU0.1B0 PORTS ERU0.1B1 SCU.HIB_SR1 ERU0.1B2 PORTS ERU0.1B3 PORTS ERU0.2A0 PORTS ERU0.2A1...
Page 209: Table 2-14 Table
XMC4500 XMC4000 Family Service Request Processing Table 4-8 ERU0 Pin Connections Global Connected To Description Inputs/Outputs ERU0.OGU03 ERU0.OGU11 ERU0.OGU12 ERU0.OGU13 ERU0.OGU21 ERU0.OGU22 ERU0.OGU23 ERU0.OGU31 ERU0.OGU32 ERU0.OGU33 ERU0.PDOUT0 not connected ERU0.GOUT0 not connected ERU0.TOUT0 not connected ERU0.IOUT0 SCU.ERU0.SR0 ERU0.PDOUT1 not connected ERU0.GOUT1 not connected ERU0.TOUT1...
Page 210: Table 2-16 Table
XMC4500 XMC4000 Family Service Request Processing 4.11.2 ERU1 Connections The following table shows the ERU1 connections. Please refer to the ports chapter for details about PORTS connections. Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.0A0 PORTS ERU1.0A1 POSIF0.SR1 ERU1.0A2 CCU40.ST0...
Page 211: Table 2-18 Table
XMC4500 XMC4000 Family Service Request Processing Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.3A2 CCU40.ST3 ERU1.3A3 not connected ERU1.3B0 PORTS ERU1.3B1 CCU80.ST3 ERU1.3B2 VADC.G1BFL3 ERU1.3B3 not connected ERU1.OGU01 VADC.C0SR0 ERU1.OGU02 CCU40.ST0 ERU1.OGU03 ERU1.OGU11 VADC.C0SR1 ERU1.OGU12 CCU41.ST0 ERU1.OGU13 ERU1.OGU21 VADC.C0SR2 ERU1.OGU22...
Page 212 XMC4500 XMC4000 Family Service Request Processing Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.PDOUT0 CCU40.IN0J, CCU41.IN0J CCU42.IN0J, CCU43.IN0J CCU40.IN1D CCU40.IN2D CCU40.IN3D CCU41.IN1D CCU41.IN2D CCU41.IN3D CCU42.IN1D CCU42.IN2D CCU42.IN3D CCU43.IN1D CCU43.IN2D CCU43.IN3D CCU80.IN0J CCU80.IN1J CCU80.IN2J CCU80.IN3J VADC.G0REQGTO VADC.G1REQGTO VADC.G2REQGTO VADC.G3REQGTO VADC.BGREQGTO DSD.ITR0A...
Page 213 XMC4500 XMC4000 Family Service Request Processing Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.IOUT0 CCU40.IN0K CCU41.IN0K CCU42.IN0K CCU43.IN0K CCU80.IN0G CCU81.IN0G VADC.G0REQTRM VADC.G1REQTRM VADC.G2REQTRM VADC.G3REQTRM VADC.BGREQTRM CCU40.MCLKA CCU41.MCLKA CCU42.MCLKA CCU43.MCLKA CCU80.MCLKA CCU81.MCLKA NVIC.ERU1.SR0 POSIF0.EWHEB POSIF1.EWHEB Reference Manual 4-41 V1.6, 2016-07 Service Request Processing, V1.6 Subject to Agreement on the Use of Product Information...
Page 214 XMC4500 XMC4000 Family Service Request Processing Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.PDOUT1 CCU40.IN1J CCU41.IN1J CCU42.IN1J CCU43.IN1J CCU81.IN0I CCU81.IN1I CCU81.IN2I CCU81.IN3I CCU40.IN0D CCU41.IN0D CCU42.IN0D CCU43.IN0D VADC.G0REQGTP VADC.G1REQGTP VADC.BGREQGTP DSD.ITR0B DSD.ITR1B DSD.ITR2B DSD.ITR3B POSIF0.IN1D POSIF1.IN1D PORTS ERU1.GOUT1 not connected ERU1.TOUT1 not connected...
Page 215 XMC4500 XMC4000 Family Service Request Processing Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.IOUT1 CCU40.IN1K CCU41.IN1K CCU42.IN1K CCU43.IN1K CCU80.IN1G CCU81.IN1G VADC.G0REQTRN VADC.G1REQTRN VADC.BGREQTRN CCU40.MCLKB CCU41.MCLKB CCU42.MCLKB CCU43.MCLKB CCU80.MCLKB CCU81.MCLKB NVIC.ERU1.SR1 POSIF0.EWHEC POSIF1.EWHEC ERU1.PDOUT2 CCU40.IN2J CCU41.IN2J CCU42.IN2J CCU43.IN2J CCU80.IN2F CCU81.IN2F DSD.ITR0C...
Page 216 XMC4500 XMC4000 Family Service Request Processing Table 4-9 ERU1 Pin Connections Global Connected To Description Inputs/Outputs ERU1.IOUT2 CCU40.IN2K CCU41.IN2K CCU42.IN2K CCU43.IN2K CCU80.IN2G CCU81.IN2G VADC.G2REQTRN VADC.G3REQTRN ERU1.1B3 NVIC.ERU1.SR2 POSIF0.MSETF POSIF1.MSETF ERU1.PDOUT3 CCU40.IN3J CCU41.IN3J CCU42.IN3J CCU43.IN3J CCU80.IN3F CCU81.IN3F DSD.ITR0D DSD.ITR1D DSD.ITR2D DSD.ITR3D DSD.SGNB PORTS ERU1.GOUT3...
Page 217: General Purpose Dma (Gpdma)
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) General Purpose DMA (GPDMA) The GPDMA is a highly configurable DMA controller, that allows high-speed data transfers between peripherals and memories. Complex data transfers can be done with minimal intervention of the processor, keeping this way the CPU resources free for other operations.
Page 218 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) • Transfers – Support for memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral DMA transfers Channels All channels can be programmed for the following transfer modes • DMA triggered by software or selectable from hardware service request sources •...
Page 219: Block Diagram
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.1.2 Block Diagram Figure 5-1 shows the following functional groupings of the main interfaces to the GPDMA block: • DMA hardware request interface (DLR) • Up to twelve channels • Arbiter • Bus Master and Slave interfaces One channel of the GPDMA is required for each source/destination pair.
Page 220: Functional Description
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Functional Description This chapter describes the functional details of the GPDMA. 5.2.1 Terminology The following terms are concise definitions of the DMA concepts are used throughout this chapter: Service Partner Terms • Source peripheral - Device from which the GPDMA reads data; the GPDMA then stores the data in the channel FIFO.
Page 221 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Flow Control Terms • Flow controller - Device that determines the length of a DMA block transfer and terminates it. – If you know the length of a block before enabling the channel, then GPDMA should be programmed as the flow controller.
Page 222 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) DMA Transfer Level Transfer Block Transfer Block Block Block Level Burst Burst Burst Single Bus Transfer Transfer Transfer Transfer Transfer Level Figure 5-3 Transfer Hierarchy for Memory • DMA transfer - Can be programmed to single or multiple blocks (depends on channel features).
Page 223: Variable Definitions
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Specific Transfer Mode Terms • Scatter - Relevant to destination transfers within a block. The destination address is incremented or decremented by a programmed amount when a scatter boundary is reached. The number of AHB transfers between successive scatter boundaries is under software control.
Page 224: Flow Controller And Transfer Type
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Block size in bytes • GPDMA is the flow controller: With the GPDMA as the flow controller, the processor programs the GPDMA with the number of data items (block size) of source transfer width (CTL.SRC_TR_WIDTH) to be transferred by the GPDMA in a block transfer;...
Page 225: Handshaking Interface
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-2 Transfer Type, Flow Control and Handshake Combinations Transfer Type Flow Controller Handshaking Memory to Memory GPDMA Memory to Peripheral GPDMA Hardware or Software Peripheral to Memory GPDMA Hardware or Software Peripheral to Peripheral GPDMA Hardware or Software Peripheral to Memory...
Page 226: Hardware Handshaking
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.2.4.1 Hardware Handshaking Before the transfer can begin the GPDMA and DLR units must be set up according to the user requirements (shown as step 1 in Figure 5-4). Once the peripheral (source or destination) is ready for a transaction it sends a service request.
Page 227: Handshaking With Gpdma As Flow Controller
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Set up the channel Execute Transaction GPDMA DMA Trigger (Software Handshake) Peripheral Service Request Figure 5-5 Software Handshaking Interface 5.2.4.3 Handshaking with GPDMA as Flow Controller The GPDMA tries to efficiently transfer the data using as little of the bus bandwidth as possible.
Page 228 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Early-Terminated Burst Transaction When a source or destination peripheral is in the Single Transaction Region, a burst transaction can still be requested when using Software Handshaking. In this case, the burst transaction is started and "early-terminated" at block completion without transferring the programmed amount of data, that is, src_burst_size_bytes or dst_burst_size_bytes, but only the amount required to complete the block transfer.
Page 229: Handshaking With Peripheral As Flow Controller
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Single Transaction Region, then the block completes using an Early-Terminated Burst Transaction. Software can poll the relevant channel bit in the SGLREQSRCREG, SGLREQDSTREG and REQSRCREG, REQDSTREG registers. When both are 0, then either the requested burst or single transaction has completed.
Page 230: Fifo Usage
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The request is the last in the block if the corresponding channel bit in the Last Source/Destination Request register is asserted; refer to LSTSRCREG LSTDSTREG, respectively. If LSTSRCREG[n], LSTDSTREG[n] = 1 when a 1 is written to the REQSRCREG[n], REQDSTREG[n] register, this means that software is requesting that this transaction is the last transaction in the block.
Page 231: Bus And Channel Locking
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Note: An exception to FIFO readiness for destination transfers occurs in "FIFO flush mode" In this mode, FIFO readiness for destination transfers occurs when the channel FIFO contains data to form at least a single transfer of CTL.SRC_TR_WIDTH width (and not CTL.DST_TR_WIDTH width, as is the normal case).
Page 232 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) • Channel locking - Locks the arbitration for the AHB master interface, which grants ownership of the master bus interface to one of the requesting channel state machines (source or destination). Bus and channel locking can proceed for the duration of a DMA transfer, a block transfer, or a single or burst transaction.
Page 233: Scatter/Gather
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Source and destination block transfers occur successively in time, and a new source block cannot commence until the previous destination block has completed. Block and DMA transfer level locking are both terminated on completion of the block or DMA transfer to the destination.
Page 234 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) gather boundary is reached. If the CTL.SINC field indicates a fixed-address control throughout a DMA transfer, then the CTL.SRC_GATHER_EN field is ignored, and the gather feature is automatically disabled. Note: For multi-block transfers, the counters that keep track of the number of transfers left to reach a gather/scatter boundary are re-initialized to the source gather count (SGRx.SGC) and destination scatter count (DSC), respectively, at the start of each block transfer.
Page 235 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Figure 5-7 Source Gather when SGR.SGI = 0x1 In general, if the starting address is A0 and CTL.SINC = 00 (increment source address control), then the transfer will be: A0, AO + TWB, A0 + 2*TWB (A0 + (SGR.SGC-1)*TWB) <-scatter_increment->...
Page 236: Abnormal Transfer Termination
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.2.8 Abnormal Transfer Termination A GPDMA DMA transfer may be terminated abruptly by software by clearing the channel enable bit, CHENREG.CH_EN or by clearing the global enable bit in the GPDMA Configuration Register (DMACFGREG[0]). If a transfer is in progress while a channel is disabled, abnormal transfer termination and data corruption occurs.
Page 237: Basic Transfers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Basic Transfers From a users perspective DMA transfers can be grouped into • software triggered transfers and • hardware triggered transfers. The setup procedure for both kinds of transfers is identical to a large extent and is described in more detail later in this section after highlighting the differences of the trigger types.
Page 238: Block Transfer With Gpdma As The Flow Controller
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-3 Parameters Used in Transfer Examples (cont’d) Parameter Description CTL.SRC_MSIZE Source burst transaction length CTL.DEST_MSIZE Destination burst transaction length CFG.MAX_ABRST Maximum AMBA burst length CFG.FIFO_MODE FIFO mode select CFG.FCMODE Flow-control mode The GPDMA is programmed with the number of data items that are to be transferred for each burst transaction request, CTL.SRC_MSIZE and CTL.DEST_MSIZE.
Page 239: Effect Of Maximum Amba Burst Length On A Block Transfer
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Figure 5-8 Breakdown of Block Transfer The channel FIFO is alternatively filled by a burst from the source and emptied by a burst to the destination until the block transfer has completed, as shown in Figure 5-9.
Page 240 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Channel Fifo Figure 5-10 Breakdown of Block Transfer where max_abrst = 2, Case 1 The channel FIFO is alternatively half filled by a burst from the source, and then emptied by a burst to the destination until the block transfer has completed; this is illustrated in Figure 5-11.
Page 241 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Channel Fifo Figure 5-12 Breakdown of Block Transfer where max_abrst = 2, Case 2 This depends on the timing of the source and destination transaction requests, relative to each other. Figure 5-13 illustrates the channel FIFO status for Figure 5-12.
Page 242 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Limiting a burst to a maximum length prevents the GPDMA from saturating the AHB bus when the system arbiter is configured to only allow changing of the grant signals to bus masters at the end of an undefined length burst. It also prevents a channel from saturating a GPDMA master bus interface.
Page 243: Multi Block Transfers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Multi Block Transfers A DMA transfer may consist of • single block transfer, supported by all channels. • multi-block transfers, supported by channels 0 and 1 of GPDMA0. On successive blocks of a multi-block transfer, the SAR, register in the GPDMA is reprogrammed using either of the following methods: •...
Page 244 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The SAR, DAR, LLP, and registers are fetched from system memory on an LLI update. The updated contents of the CTL, SSTAT, and DSTAT registers are optionally written back to memory on block completion. Figure 5-14 Figure 5-15 show how...
Page 245 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Note: In order to not confuse the SAR, DAR, LLP, CTL, SSTAT DSTAT register locations of the LLI with the corresponding GPDMA memory mapped register locations, the LLI register locations are prefixed with LLI; that is, LLI.SAR, LLI.DAR, LLI.LLP, LLI.CTLH/L, LLI.SSTATx, and LLI.DSTATx.
Page 246 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-5 Programming of Transfer Types and Channel Register Update Method (cont’d) 5. Single-block or None, user None None last transfer of reprograms (single) (single) multi-block. 6. Linked list CTL, Contig Linked multi-block loaded from uous List...
Page 247: Table 2-20 Table
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) [LLP] + 0x18 LLI.DSTAT LLI. SSTAT [LLP] + 0x14 [LLP] + 0x10 LLI.CTLH LLI.CTLL [LLP] + 0x0C LLI.LLP(1) [LLP] + 0x08 LLI.DAR [LLP] + 0x04 Base Address of LLI LLI.SAR [LLP] (LLP.LOC) Figure 5-16 Mapping of Block Descriptor (LLI) in Memory to Channel Registers When CFG.SS_UPD_EN = 1 LLI.DSTAT [LLP] + 0x14...
Page 248: Auto-Reloading Of Channel Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 4. The destination status is fetched and written to system memory at the end of every block transfer if the Write Back column entry is "Yes” and CFG.DS_UPD_EN is enabled. 5.4.2 Auto-Reloading of Channel Registers During auto-reloading, the channel registers are reloaded with their initial values at the completion of each block and the new values used for the new block.
Page 249: Ending Multi-Block Transfers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) For rows 2, 3, 4, 7, and 9 of Table 5-5 (SAR and/or auto-reloaded between block transfers), the DMA transfer does not stall if either: • Interrupts are disabled, CTL.INT_EN = 0, or •...
Page 250: Programing Examples
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.4.6 Programing Examples Three registers - LLP, CTL, and - need to be programmed to determine whether single- or multi-block transfers occur, and which type of multi-block transfer is used. The different transfer types are shown in Table 5-5.
Page 251: Multi-Block Transfer With Source Address Auto-Reloaded And Contiguous Destination Address
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) b) Write the starting destination address in the register for channel x. c) Program according to Row 1, as shown in Table 5-5. Program the register with 0. d) Write the control information for the DMA transfer in the register for channel x.
Page 252 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing Interrupt Clear registers: CLEARTFR, CLEARBLOCK, CLEARSRCTRAN, CLEARDSTTRAN, and CLEARERR. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3.
Page 253 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 7. The DMA transfer proceeds as follows: a) If interrupts are enabled (CTL.INT_EN = 1) and the block-complete interrupt is unmasked (MASKBLOCK[x] = 1 , where x is the channel number), hardware sets the block-complete interrupt when the block transfer has completed.
Page 254 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The DMA transfer flow is shown in Figure 5-19. Channel enabled by SW Block transfer Reload SAR and CTLH/L Last Block? Transfer complete interrupt generated here Channel disabled by HW CTLL.INT_EN = 1 AND MASKBLOCK[Chan.] = 1 Block-complete interrupt generated here...
Page 255: Multi-Block Transfer With Source And Destination Address Auto-Reloaded
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.4.6.3 Multi-Block Transfer with Source and Destination Address Auto-Reloaded This section is an example for the transfer listed in row 4 in Table 5-5. Note: This type of transfer is supported by GPDMA0 channels 0 and 1 only. 1.
Page 256 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) samples the row number, as shown in Table 5-5. If the GPDMA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. You can either respond to the Block Complete or Transfer Complete interrupts, or poll for the transfer complete raw interrupt status register (RAWTFR[n], where n is the channel number) until it is set by hardware, in order to detect when the transfer is complete.
Page 257 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The transfer is similar to that shown in Figure 5-20. Figure 5-20 Multi-Block DMA Transfer with Source and Destination Address Auto-Reloaded Reference Manual 5-41 V1.6, 2016-07 GPDMA, V1.4 Subject to Agreement on the Use of Product Information...
Page 258 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The DMA transfer flow is shown in Figure 5-21. Channel enabled by SW Block transfer Reload SAR, DAR and CTLH/L Last Block? Transfer complete interrupt generated here Channel disabled by HW CTLL.INT_EN = 1 AND MASKBLOCK[Chan.] = 1 Block-complete interrupt generated here...
Page 259: Multi-Block Transfer With Source Address Auto-Reloaded And Linked List Destination Address
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.4.6.4 Multi-Block Transfer with Source Address Auto-Reloaded and Linked List Destination Address This section is an example for the transfer listed in row 7 in Table 5-5. Note: This type of transfer is supported by GPDMA0 channels 0 and 1 only. 1.
Page 260 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) destination status information is fetched from system memory, refer to the Write Back column of Table 5-5. 11. If gather is enabled (CTL.SRC_GATHER_EN = 1), program the register for channel x. 12. If scatter is enabled (CTL.DST_SCATTER_EN = 1), program the register for channel x.
Page 261 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) asserted, then this block transfer has completed. This LLI.CTLH/L.DONE bit was cleared at the start of the transfer (Step 8). 21. The SSTAT register is now written out to system memory if CFG.SS_UPD_EN is enabled.
Page 262 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) DMA block transfer. If the next block is the last block of the DMA transfer, then the registers just fetched from the LLI should match Row 1 or Row 5 of Table 5-5. The DMA transfer might look like that shown in Figure 5-22.
Page 263 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The DMA transfer flow is shown in Figure 5-23. Channel enabled by SW LLI fetch HW reprograms DAR, CTLH/L and LLP Block transfer Source/destination status fetch Write-back of control and source/ destination status to LLI Reload SAR Last Block? Transfer complete...
Page 264: Multi-Block Dma Transfer With Linked List For Source And Contiguous Destination Address
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.4.6.5 Multi-Block DMA Transfer with Linked List for Source and Contiguous Destination Address This section is an example for the transfer listed in row 8 in Table 5-5. Note: This type of transfer is supported by GPDMA0 channels 0 and 1 only. 1.
Page 265 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) destination status information is fetched from system memory, refer to the Write Back column of Table 5-5. 11. If gather is enabled (CTL.SRC_GATHER_EN = 1), program the register for channel x. 12. If scatter is enabled (CTL.DST_SCATTER_EN = 1), program the register for channel x.
Page 266 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) asserted, then this block transfer has completed. This LLI.CTLH/L.DONE bit was cleared at the start of the transfer (Step 8). 21. The SSTAT register is now written out to system memory if CFG.SS_UPD_EN is enabled.
Page 267: Multi-Block Transfer With Linked List For Source And Destination
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The DMA transfer flow is shown in Figure 5-25. Channel enabled by SW LLI fetch HW reprograms DAR, CTLH/L and LLP Block transfer Source/destination status fetch Write-back of control and source/ destination status to LLI Block-complete complete interrupt generated here Last Block?
Page 268 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. Write the control information in the LLI.CTL register location of the block descriptor for each LLI in memory (see Figure 5-14) for channel x.
Page 269 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 14. Program the register with LLP(0), the pointer to the first linked list item. 15. Finally, enable the channel by writing a 1 to the GPDMA0_CHENREG.CH_EN bit; the transfer is performed. 16. The GPDMA fetches the first LLI from the location pointed to by LLP(0). The LLI.SAR, LLI.DAR, LLI.LLP, and LLI.CTL registers are fetched and the GPDMA automatically reprograms the according SAR, DAR, LLP, and channel registers.
Page 270 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) by the previous value of the LLP.LOC register, not the LLI pointed to by the current value of the LLP.LOC register. 21. The GPDMA does not wait for the block interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by the current register and automatically reprograms the SAR, DAR, CTL, and...
Page 271 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Figure 5-27 Multi-Block with Linked Address for Source and Destination Where Between Successive Blocks are Contiguous Reference Manual 5-55 V1.6, 2016-07 GPDMA, V1.4 Subject to Agreement on the Use of Product Information...
Page 272 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The DMA transfer flow is shown in Figure 5-28. Channel enabled by software LLI fetch Hardware reprograms SAR, DAR, CTLH/L and LLP DMA block transfer Source/destination status fetch Write-back of control and source/ destination status to LLI Block interrupt generated here...
Page 273: Service Request Generation
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Service Request Generation Each GPDMA block provides a number of registers (see Section 5.8.3) to control the request behavior and to provide an interface for software to check for request occurrence. The following DMA Events can be generated for each channel due to DMA activity: •...
Page 274: Power, Reset And Clock
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Power, Reset and Clock The GPDMA unit is inside the core power domain, therefore no special considerations about power up or power down sequences need to be taken. For an explanation about the different power domains, please address the SCU (System Control Unit) chapter. Additionally, if a GPDMA unit is not needed, it can be held in reset via the PRSET2.DMAyRS bitfield (address the SCU chapter for a full description).
Page 275: Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Registers This chapter includes information on how to program the GPDMA. Register references There are references to software parameters throughout this chapter. The software parameters are the field names in each register description table and are prefixed by the register name;...
Page 276: Table 2-22 Table
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-7 Register Overview Short Name Description Offset Access Mode Description Addr. Read Write ChannelRegisters Source Address Register 0000 U, PV U, PV Page 5-66 x*58 Destination Address 0008 U, PV U, PV Page 5-67 Register x*58...
Page 277: Table 4-1 Table
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-7 Register Overview (cont’d) Short Name Description Offset Access Mode Description Addr. Read Write RAW* with Interrupt Raw Status 02C0 U, PV U, PV Page 5-101 *TFR, Registers 02E0 *BLOCK, *SRCTRAN, *DSTTRAN, *ERR STATUS* with Interrupt Status Registers...
Page 278: Table 4-3 Table
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-7 Register Overview (cont’d) Short Name Description Offset Access Mode Description Addr. Read Write SGLREQDSTR Single Destination 0380 U, PV U, PV Page 5-118 Transaction Request Register LSTSRCREG Last Source Transaction 0388 U, PV U, PV Page 5-120...
Page 279: Configuration And Channel Enable Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.8.1 Configuration and Channel Enable Registers DMACFGREG This register is used to enable the GPDMA, which must be done before any channel activity can begin. GPDMA0_DMACFGREG GPDMA Configuration Register (398 Reset Value: 0000 0000 GPDMA1_DMACFGREG GPDMA Configuration Register (398 Reset Value: 0000 0000...
Page 280 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The channel enable bit, CHENREG.CH_EN, is written only if the corresponding channel write enable bit, CHENREG.CH_EN_WE, is asserted on the same AHB write transfer. For example, writing hex 01x1 writes a 1 into CHENREG[0], while CHENREG[7:1] remains unchanged.
Page 281: Channel Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description [3:0] Enables/Disables the channel Setting this bit enables a channel; clearing this bit disables the channel. Disable the Channel Enable the Channel The CHENREG.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed.
Page 282 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current AHB transfer.
Page 283 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current AHB transfer.
Page 284 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) upwards if address control is incrementing or next address downwards if address control is decrementing). The destination address is automatically realigned by the GPDMA in the following DMA transfer setup scenario: • Contiguous multi-block transfers on destination side, AND •...
Page 285 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) You need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled. GPDMA0_CHx_LLP (x = 0-1) Linked List Pointer Register for Channel x + x*58 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 286 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) These registers contain fields that control the DMA transfer. The CTLH and CTLL registers are part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.
Page 287 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description BLOCK_TS [11:0] Block Transfer Size When the GPDMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed here indicates the total number of single transactions to perform for every block transfer.
Page 288 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) CTLL Control Register Low. GPDMA0_CHx_CTLL (x=0-1) Control Register Low for Channel x + x*58 Reset Value: 0030 4801 LLP_ LLP_ TT_FC _MSI SRC_MSIZ INT_ DEST_MSIZE SINC DINC SRC_TR_WIDTH DST_TR_WIDTH Field Bits Type Description INT_EN Interrupt Enable Bit If set, then all interrupt-generating sources are...
Page 289 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description DINC [8:7] Destination Address Increment Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to "No change".
Page 290 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description SRC_MSIZE [16:14] rw Source Burst Transaction Length Number of data items, each of width SRC_TR_WIDTH, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface.
Page 291 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_CHx_CTLL (x=2-7) Control Register Low for Channel x + x*58 Reset Value: 0030 4801 GPDMA1_CHx_CTLL (x=0-3) Control Register Low for Channel x + x*58 Reset Value: 0030 4801 TT_FC _MSI SRC_MSIZ INT_ DEST_MSIZE SINC DINC SRC_TR_WIDTH DST_TR_WIDTH...
Page 292 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description SINC [10:9] Source Address Increment Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to "No change".
Page 293 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Table 5-8 CTLL.SRC_MSIZE and CTLL.DST_MSIZE Field Decoding CTLL.SRC_MSIZE / Number of data items to be transferred(of width CTLL.DEST_MSIZE CTLL.SRC_TR_WIDTH or CTLL.DST_TR_WIDTH) others reserved Table 5-9 CTLL.SRC_TR_WIDTH and CTLL.DST_TR_WIDTH Field Decoding CTLL.SRC_TR_WIDTH / Size (bits) CTLL.DST_TR_WIDTH others reserved...
Page 294 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) SSTAT After each block transfer completes, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATAR register. This status information is then stored in the SSTAT register and written out to the SSTAT register location of the LLI before the start of the next block.
Page 295 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) DSTAT After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATAR register. This status information is then stored in the DSTAT register and written out to the DSTAT register location of the LLI before the start of the next block.
Page 296 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) SSTATAR After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATAR register. GPDMA0_CHx_SSTATAR (x=0-1) Source Status Address Register for Channel x + x*58 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 297 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) DSTATAR After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATAR register. GPDMA0_CHx_DSTATAR (x=0-1) Destination Status Address Register for Channel x + x*58 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 298 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) These registers contain fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. Note: You need to program this register prior to enabling the channel. GPDMA0_CHx_CFGH (x=0-1) Configuration Register High for Channel x + x*58...
Page 299 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description FCMODE Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. Source transaction requests are serviced when they occur. Data pre-fetching is enabled. Source transaction requests are not serviced until a destination transaction request occurs.
Page 300 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description DS_UPD_EN 5 Destination Status Update Enable Destination status information is fetched only from the location pointed to by the DSTATAR register, stored in DSTAT register and written out to the DSTAT location of the LLI if DS_UPD_EN is high.
Page 301 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description DEST_PER [14:11] rw Destination Peripheral Assigns a DLR line as hardware handshaking interface to the destination of channel x assigns DLR line 0 assigns DLR line 1 assigns DLR line 2 assigns DLR line 3 assigns DLR line 4 assigns DLR line 5...
Page 302 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description FCMODE Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. Source transaction requests are serviced when they occur. Data pre-fetching is enabled. Source transaction requests are not serviced until a destination transaction request occurs.
Page 303 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description SRC_PER [10:7] Source Peripheral Assigns a DLR line as hardware handshaking interface to the source of channel x assigns DLR line 0 assigns DLR line 1 assigns DLR line 2 assigns DLR line 3 assigns DLR line 4 assigns DLR line 5...
Page 304 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description DEST_PER [14:11] rw Destination Peripheral Assigns a DLR line as hardware handshaking interface to the destination of channel x assigns DLR line 0 assigns DLR line 1 assigns DLR line 2 assigns DLR line 3 assigns DLR line 4 assigns DLR line 5...
Page 305 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description FCMODE Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. Source transaction requests are serviced when they occur. Data pre-fetching is enabled. Source transaction requests are not serviced until a destination transaction request occurs.
Page 306 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description SRC_PER [10:7] Source Peripheral Assigns a DLR line as hardware handshaking interface to the source of channel x assigns DLR line 8 assigns DLR line 9 assigns DLR line 10 assigns DLR line 11 Other values not defined.
Page 307 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_CHx_CFGL (x=0-1) Configuration Register Low for Channel x + x*58 Reset Value: 0000 0EX0 MAX_ABRST FIFO LOCK_B_ LOCK_CH CH_PRIOR Field Bits Type Description CH_PRIOR [7:5] Channel priority A priority of 7 is the highest priority, and 0 is the lowest.
Page 308 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description HS_SEL_DST Destination Software or Hardware Handshaking Select This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. Hardware handshaking interface. Software- initiated transaction requests are ignored.
Page 309: Table 4-5 Table
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description LOCK_CH Channel Lock Bit When the channel is granted control of the master bus interface and if the CFGLx.LOCK_CH bit is asserted, then no other channels are granted control of the master bus interface for the duration specified in CFGLx.LOCK_CH_L.
Page 310 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_CHx_CFGL (x=2-7) Configuration Register Low for Channel x + x*58 Reset Value: 0000 0EX0 GPDMA1_CHx_CFGL (x=0-3) Configuration Register Low for Channel x + x*58 Reset Value: 0000 0EX0 MAX_ABRST FIFO LOCK_B_ LOCK_CH CH_PRIOR Field Bits Type Description...
Page 311 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description FIFO_EMPTY Indicates if there is data left in the channel FIFO Can be used in conjunction with CFGLx.CH_SUSP to cleanly disable a channel. Channel FIFO empty Channel FIFO not empty HS_SEL_DST 10 Destination Software or Hardware Handshaking Select...
Page 312: Table 5-6 Table
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description LOCK_CH Channel Lock Bit When the channel is granted control of the master bus interface and if the CFGLx.LOCK_CH bit is asserted, then no other channels are granted control of the master bus interface for the duration specified in CFGLx.LOCK_CH_L.
Page 313 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The Source Gather register contains two fields: • Source gather count field (SGRx.SGC) - Specifies the number of contiguous source transfers of CTL.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. •...
Page 314 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The Destination Scatter register contains two fields: • Destination scatter count field (DSRx.DSC) - Specifies the number of contiguous destination transfers of CTL.DST_TR_WIDTH between successive scatter boundaries. • Destination scatter interval field (DSRx.DSI) - Specifies the destination address increment/decrement in multiples of CTL.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer.
Page 315: Interrupt Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.8.3 Interrupt Registers The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources: • IntBlock - Block Transfer Complete Interrupt. This interrupt is generated on DMA block transfer completion to the destination peripheral.
Page 316 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The contents of each of the five Status registers is ORed to produce a single bit for each interrupt type in the Combined Status register; that is, STATUSINT. Note: For interrupts to propagate past the raw* interrupt register stage, CTL.INT_EN must be set to 1 , and the relevant interrupt must be unmasked in the mask* interrupt register.
Page 317 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Interrupt Raw Status Registers Interrupt events are stored in these Raw Interrupt Status registers before masking: RAWBLOCK, RawDstTran, RawErr, RawSrcTran, and RAWTFR. Each Raw Interrupt Status register has a bit allocated per channel; for example, RAWTFR[2] is the Channel 2 raw transfer complete interrupt.
Page 318 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_RAWTFR Raw IntTfr Status (2C0 Reset Value: 0000 0000 GPDMA0_RAWBLOCK Raw IntBlock Status (2C8 Reset Value: 0000 0000 GPDMA0_RAWSRCTRAN Raw IntSrcTran Status (2D0 Reset Value: 0000 0000 GPDMA0_RAWDSTTRAN Raw IntBlock Status (2D8 Reset Value: 0000 0000 GPDMA0_RAWERR Raw IntErr Status (2E0...
Page 319 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA1_RAWTFR Raw IntTfr Status (2C0 Reset Value: 0000 0000 GPDMA1_RAWBLOCK Raw IntBlock Status (2C8 Reset Value: 0000 0000 GPDMA1_RAWSRCTRAN Raw IntSrcTran Status (2D0 Reset Value: 0000 0000 GPDMA1_RAWDSTTRAN Raw IntBlock Status (2D8 Reset Value: 0000 0000 GPDMA1_RAWERR Raw IntErr Status (2E0...
Page 320 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Interrupt Status Registers All interrupt events from all channels are stored in these Interrupt Status registers after masking: STATUSBLOCK, STATUSDSTTRAN, STATUSERR, STATUSSRCTRAN, and STATUSTFR. Each Interrupt Status register has a bit allocated per channel; for example, STATUSTFR[2] is the Channel 2 status transfer complete interrupt.
Page 321 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_STATUSTFR IntTfr Status (2E8 Reset Value: 0000 0000 GPDMA0_STATUSBLOCK IntBlock Status (2F0 Reset Value: 0000 0000 GPDMA0_STATUSSRCTRAN IntSrcTran Status (2F8 Reset Value: 0000 0000 GPDMA0_STATUSDSTTRAN IntBlock Status (300 Reset Value: 0000 0000 GPDMA0_STATUSERR IntErr Status (308 Reset Value: 0000 0000...
Page 322 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA1_STATUSTFR IntTfr Status (2E8 Reset Value: 0000 0000 GPDMA1_STATUSBLOCK IntBlock Status (2F0 Reset Value: 0000 0000 GPDMA1_STATUSSRCTRAN IntSrcTran Status (2F8 Reset Value: 0000 0000 GPDMA1_STATUSDSTTRAN IntBlock Status (300 Reset Value: 0000 0000 GPDMA1_STATUSERR IntErr Status (308 Reset Value: 0000 0000...
Page 323 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Interrupt Mask Registers The contents of the Raw Status registers are masked with the contents of the Mask registers: MASKBLOCK, MASKDSTTRAN, MASKERR, MASKSRCTRAN, and MASKTFR. Each Interrupt Mask register has a bit allocated per channel; for example, MASKTFR[2] is the mask bit for the Channel 2 transfer complete interrupt.
Page 324 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_MASKTFR Mask for Raw IntTfr Status (310 Reset Value: 0000 0000 GPDMA0_MASKBLOCK Mask for Raw IntBlock Status (318 Reset Value: 0000 0000 GPDMA0_MASKSRCTRAN Mask for Raw IntSrcTran Status (320 Reset Value: 0000 0000 GPDMA0_MASKDSTTRAN Mask for Raw IntBlock Status (328...
Page 325 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA1_MASKTFR Mask for Raw IntTfr Status (310 Reset Value: 0000 0000 GPDMA1_MASKBLOCK Mask for Raw IntBlock Status (318 Reset Value: 0000 0000 GPDMA1_MASKSRCTRAN Mask for Raw IntSrcTran Status (320 Reset Value: 0000 0000 GPDMA1_MASKDSTTRAN Mask for Raw IntBlock Status (328...
Page 326 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Interrupt Clear Registers Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: CLEARBLOCK, CLEARDSTTRAN, CLEARERR, CLEARSRCTRAN, and CLEARTFR. Each Interrupt Clear register has a bit allocated per channel;...
Page 327 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_CLEARTFR IntTfr Status (338 Reset Value: 0000 0000 GPDMA0_CLEARBLOCK IntBlock Status (340 Reset Value: 0000 0000 GPDMA0_CLEARSRCTRAN IntSrcTran Status (348 Reset Value: 0000 0000 GPDMA0_CLEARDSTTRAN IntBlock Status (350 Reset Value: 0000 0000 GPDMA0_CLEARERR IntErr Status (358 Reset Value: 0000 0000...
Page 328 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA1_CLEARTFR IntTfr Status (338 Reset Value: 0000 0000 GPDMA1_CLEARBLOCK IntBlock Status (340 Reset Value: 0000 0000 GPDMA1_CLEARSRCTRAN IntSrcTran Status (348 Reset Value: 0000 0000 GPDMA1_CLEARDSTTRAN IntBlock Status (350 Reset Value: 0000 0000 GPDMA1_CLEARERR IntErr Status (358 Reset Value: 0000 0000...
Page 329 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_STATUSINT Combined Interrupt Status Register (360 Reset Value: 0000 0000 GPDMA1_STATUSINT Combined Interrupt Status Register (360 Reset Value: 0000 0000 Field Bits Type Description OR of the contents of STATUSTFR register BLOCK OR of the contents of STATUSBLOCK register SRCT OR of the contents of STATUSSRCTRAN register DSTT...
Page 330: Software Handshaking Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.8.4 Software Handshaking Registers The registers that comprise the software handshaking registers allow software to initiate single or burst transaction requests in the same way that handshaking interface signals do in hardware. Setting CFG.HS_SEL_SRC to 1 enables software handshaking on the source of channel x.
Page 331 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description Source request for channel x (x=0-7) WE_CHx Source request write enable for channel x (x=0-7) write disabled write enabled [31:16] r Reserved GPDMA1_REQSRCREG Source Software Transaction Request Register (368 Reset Value: 0000 0000 CH3 CH2 CH1 CH0 Field...
Page 332 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) The functionality of this register depends on whether the destination is a flow control peripheral or not. GPDMA0_REQDSTREG Destination Software Transaction Request Register (370 Reset Value: 0000 0000 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Field Bits Type Description...
Page 333 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description Source request for channel x (x=0-3) WE_CHx Source request write enable for channel x (x=0-3) write disabled write enabled [31:12], Reserved [7:4] SGLREQSRCREG A bit is assigned for each channel in this register. SGLREQSRCREG[n] is ignored when software handshaking is not enabled for the source of channel n.
Page 334 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description WE_CHx Source request write enable for channel x (x=0-7) write disabled write enabled [31:16] r Reserved GPDMA1_SGLREQSRCREG Single Source Transaction Request Register (378 Reset Value: 0000 0000 CH3 CH2 CH1 CH0 Field Bits Type...
Page 335 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_SGLREQDSTREG Single Destination Transaction Request Register (380 Reset Value: 0000 0000 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Field Bits Type Description Source request for channel x (x=0-7) WE_CHx Source request write enable for channel x (x=0-7) write disabled write enabled...
Page 336 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description Source request for channel x (x=0-3) WE_CHx Source request write enable for channel x (x=0-3) write disabled write enabled [31:12], Reserved [7:4] LSTSRCREG A bit is assigned for each channel in this register. LSTSRCREG[n] is ignored when software handshaking is not enabled for the source of channel n, or when the source of channel n is not a flow controller.
Page 337 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) Field Bits Type Description Source last request for channel x (x=0-7) Not last transaction in current block Last transaction in current block WE_CHx Source last transaction request write enable for (x=0-7) channel x write disabled write enabled [31:16]...
Page 338 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) LSTDSTREG A bit is assigned for each channel in this register. LSTDSTREG[n] is ignored when software handshaking is not enabled for the destination of channel n or when the destination of channel n is not a flow controller. A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDST_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the...
Page 339 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA1_LSTDSTREG Last Destination Transaction Request Register (390 Reset Value: 0000 0000 CH3 CH2 CH1 CH0 Field Bits Type Description Destination last request for channel x (x=0-3) Not last transaction in current block Last transaction in current block WE_CHx Destination last transaction request write enable for (x=0-3)
Page 340: Miscellaneous Gpdma Registers
XMC4500 XMC4000 Family General Purpose DMA (GPDMA) 5.8.5 Miscellaneous GPDMA Registers This is the GPDMA ID register, which is a read-only register that reads back the hardcoded module ID number. GPDMA0_ID GPDMA0 ID Register (3A8 Reset Value: 00AF C0XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE Field Bits...
Page 341 XMC4500 XMC4000 Family General Purpose DMA (GPDMA) GPDMA0_TYPE GPDMA Component Type (3F8 Reset Value: 4457 1110 GPDMA1_TYPE GPDMA Component Type (3F8 Reset Value: 4457 1110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALUE Field Bits...
Page 342: Flexible Crc Engine (Fce)
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Flexible CRC Engine (FCE) The FCE provides a parallel implementation of Cyclic Redundancy Code (CRC) algorithms. The current FCE version for the XMC4500 microcontroller implements the IEEE 802.3 ethernet CRC32, the CCITT CRC16 and the SAE J1850 CRC8 polynomials. The primary target of FCE is to be used as an hardware acceleration engine for software applications or operating systems services using CRC signatures.
Page 343: Application Mapping
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) – CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB7 +x+1 – CRC kernel 2: CCITT CRC16 polynomial: 0x1021 - x – CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D - x •...
Page 344: Functional Description
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Depending on the hardware configuration the FCE may implement more CRC kernels with different CRC polynomials. The specific configuration for the XMC4500 microcontroller is shown in the Figure 6-1 “FCE Block Diagram” on Page 6-3.
Page 345 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) 4. input data reflected: indicates if each byte of the input parallel data is reflected before being used to compute the CRC 5. result data reflected: indicates if the final CRC value is reflected or not 6.
Page 346: Basic Operation
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Status Register [0] Interrupt Status CMF: CRC Mismatch Flag [1] Interrupt Status CEF: Configuration Error Flag [2] Interrupt Status LEF: Length Error Flag [3] Interrupt Status BEF: Bus Error Flag Figure 6-3 CRC kernel status register 6.2.1 Basic Operation...
Page 347: Register Protection And Monitoring Methods
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CFGm (m = 0-3)), the LENGTH register is reinitialized with the previously configured value. This feature is especially suited when the FCE is used in combination with a DMA engine. In the case the automatic length reload feature is not enabled, if LENGTH is already at zero but software still writes to IR (by mistake) every bit of the LENGTH should be set to 1 and hold this value until software initializes it again for the processing of a new message.
Page 348 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) SW Write access Property: Redundant Register shall be physically isolated from the functional Register Register <REG> Redundant Register <REG> Register Contents Shifted Left Force Register Mismatch CTR.FRM_<REG> Compare <reg> versus redundant <reg> SW Read Access OR results of all redundant registers per crc kernel STS.CEF Figure 6-4...
Page 349: Service Request Generation
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) 0xFACECAFE value to the <REG> address. The 0xFACECAFE is not written into the <REG> register. The next write access will proceed as a normal bus write access. The write accesses shall use full 32-bit access only. This procedure will then be repeated every time software wants to configure a new <REG>...
Page 350: Debug Behavior
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) interrupt from the same source. If a SW access to clear the interrupt status bit takes place and in the same cycle the hardware wants to set the bit, the hardware condition wins the arbitration. As all the interrupts are caused by an error condition, the interrupt shall be handled by a Error Management software layer.
Page 351 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) FCE_CFG0.U = 0x400; //set CRC initial value (seed) FCE_CRC0.U = 0xFFFFFFFF; Reference Manual 6-10 V1.6, 2016-07 FCE, V2.7 Subject to Agreement on the Use of Product Information...
Page 352: Registers
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Registers Table 6-3 show all registers associated with a FCE CRC-kernel. All FCE kernel register names are described in this section. They should get the prefix “FCE_” when used in the context of a product specification. The registers are numbered by one index to indicate the related FCE CRC Kernel (m = 0-3).
Page 353: System Registers Description
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) 1) The absolute register byte address for each CRC kernel m is calculated as follows: CRC kernel register base Address (Table 6-2) + m*20H, m = 0- Disabling the FCE The FCE module can be disabled using the register.
Page 354: Crc Kernel Control/Status Registers
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Module Identification Register Module Identification Register Reset Value: 00CA C001 MOD_NUMBER MOD_TYPE MOD_REV Field Bits Type Description MOD_REV [7:0] Module Revision Number This bit field defines the module revision number. The value of a module revision starts with 01 (first revision).
Page 355 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Field Bits Type Description [31:0] Input Register This bit field holds the 32-bit data to be computed A write to IRm triggers the CRC kernel to update the message checksum according to the IR contents and to the current CRC register contents. Only 32-bit write transactions are allowed to this IRm registers, any other bus write transaction will lead to a Bus Error.
Page 356 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Field Bits Type Description [7:0] Input Register This bit field holds the 8-bit data to be computed [31:8] Reserved Read as 0; should be written with 0. A write to IRm triggers the CRC kernel to update the message checksum according to the IR contents and to the current CRC register contents.
Page 357 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Field Bits Type Description [15:0] Result Register Returns the final CRC value including CRC reflection and final XOR according to the CFG register configuration. Writing to this register has no effect. [31:16] r Reserved Read as 0;...
Page 358 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Engine Configuration Register CFGm (m = 0-3) CRC Configuration Register m + m*20 Reset Value: 0000 0700 REFI ALR CCE BEI CEI CMI Field Bits Type Description CRC Mismatch Interrupt CRC Mismatch Interrupt is disabled CRC Mismatch Interrupt is enabled Configuration Error Interrupt When enabled, a Configuration Error Interrupt is...
Page 359 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Field Bits Type Description CRC Check Comparison CRC check comparison at the end of a message is disabled CRC check comparison at the end of a message is enabled Automatic Length Reload Disables automatic reload of the LENGTH field. Enables automatic reload of the LENGTH field at the end of a message.
Page 360 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Engine Status Register STSm (m = 0-3) CRC Status Register m + m*20 Reset Value: 0000 0000 BEF LEF CEF CMF Field Bits Type Description CRC Mismatch Flag This bit is set per hardware only. To clear this bit, software must write a 1 to this bit field location.
Page 361 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Engine Length Register LENGTHm (m = 0-3) CRC Length Register m + m*20 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LENGTH Field Bits...
Page 362 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Engine Check Register CHECKm (m = 2-2) CRC Check Register m + m*20 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHECK Field Bits...
Page 363 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Engine Initialization Register CRCm (m = 0-1) CRC Register m + m*20 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Bits Type Description...
Page 364 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) CRC Engine Initialization Register CRCm (m = 3-3) CRC Register m + m*20 Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Bits Type Description...
Page 365: Interconnects
XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Field Bits Type Description FRM_CFG Force CFG Register Mismatch This field is used to control the error injection mechanism used to check the compare logic of the redundant CFG registers. This is a one shot operation. When the hardware detects a 0 to 1 transition of this bit field it triggers a Configuration Mismatch interrupt (if enabled by the corresponding CFGm register).
Page 366 XMC4500 XMC4000 Family Flexible CRC Engine (FCE) Table 6-5 Hamming Distance as a function of message length (bits) Hamming Distance IEEE-802.3 CRC32 CCITT CRC16 J1850 CRC8 8 - 10 Information not Information not available available 8 - 10 8 - 10 11 - 12 13 - 21 22 - 34...
Page 367 XMC4500 XMC4000 Family On-Chip Memories On-Chip Memories Reference Manual V1.6, 2016-07 Subject to Agreement on the Use of Product Information...
Page 368: Memory Organization
XMC4500 XMC4000 Family Memory Organization Memory Organization This chapter provides description of the system Memory Organization and basic information related to Parity Testing and Parity Error handling. References [8] Cortex™-M4 User Guide, ARM DUI 0508B (ID062910) Overview The Memory Map is intended to balance decoding cost at various level of the system bus infrastructure.
Page 369 XMC4500 XMC4000 Family Memory Organization 0xE0100000 0xFFFFFFFF ROM Table 0xE00FF000 External PPB System 0xE0042000 0xE0041000 0xE0100000 TPIU 0xE0040000 Private peripheral bus - External 0xE0040000 Private peripheral bus - Internal 0xE0040000 0xE0000000 Reserved 0xE000F000 0xE000E000 Reserved 0xE0003000 External device 1.0GB 0xE0002000 0xE0001000 0xE0000000 0xA0000000...
Page 370: Memory Regions
XMC4500 XMC4000 Family Memory Organization Memory Regions The XMC4500 device specific address map assumes presence of internal and external memories and peripherals. The memory regions for XMC4500 are described in Table 7-1. Table 7-1 Memory Regions Start Size (hex) Space name Usage 00000000 1FFFFFFF...
Page 371 XMC4500 XMC4000 Family Memory Organization Table 7-2 Memory Map Addr space Start Address (hex) End Address (hex) Modules Code 00000000 00003FFF BROM (PMU ROM) 00004000 07FFFFFF reserved 08000000 080FFFFF PMU/FLASH (cached) 08100000 09E1FFFF reserved 09E20000 09E23FFF reserved 09E24000 0BFFFFFF reserved 0C000000 0C0FFFFF PMU/FLASH...
Page 372 XMC4500 XMC4000 Family Memory Organization Table 7-2 Memory Map (cont’d) Addr space Start Address (hex) End Address (hex) Modules Peripherals 0 40000000 40003FFF PBA0 40004000 40007FFF VADC 40008000 4000BFFF 4000C000 4000FFFF CCU40 40010000 40013FFF CCU41 40014000 40017FFF CCU42 40018000 4001BFFF reserved 4001C000 4001FFFF...
Page 373 XMC4500 XMC4000 Family Memory Organization Table 7-2 Memory Map (cont’d) Addr space Start Address (hex) End Address (hex) Modules Peripherals 2 50000000 50003FFF PBA2 50004000 50007FFF SCU & RTC 50008000 5000BFFF 5000C000 5000FFFF 50010000 50013FFF reserved 50014000 50017FFF DMA0 50018000 5001BFFF DMA1 5001C000...
Page 374: Service Request Generation
XMC4500 XMC4000 Family Memory Organization Table 7-2 Memory Map (cont’d) Addr space Start Address (hex) End Address (hex) Modules Private Peripheral E0000000 E0000FFF E0001000 E0001FFF E0002000 E0002FFF E0003000 E000DFFF reserved E000E000 E000EFFF E000E010 E000E01C SysTick E000EF34 E000EF47 E000F000 E003FFFF reserved E0040000 E0040FFF TPIU...
Page 375 XMC4500 XMC4000 Family Memory Organization mapped resources, unsupported access data widths, protected memory regions. For module specific limitations please refer to individual module chapters. Invalid Address Accesses to invalid addresses result in error responses. Invalid addresses are defined as those that do not mapped to any valid resources. This applies to single addresses and to wider address ranges.
Page 376: Debug Behavior
XMC4500 XMC4000 Family Memory Organization Bufferable Write Access to Peripheral Bufferable writes to peripheral may result in error responses as described above. Bus error responses from modules attached to peripheral bridges PBA0 and PBA1 trigger service request from the respective bridge that will result in NMI to the CPU. Error status and access address that caused the service request get stored in dedicated registers of the peripheral bridges.
Page 377: Registers
XMC4500 XMC4000 Family Memory Organization Registers This section describes registers of the Peripheral Bridges. The purpose of the registers is handling of errors signalized during bufferable accesses to peripherals connected to the respective bridges. Active errors on bufferable writes trigger interrupt requests generated from the Peripheral Bridges that can be monitored and cleared in the register defiled in this chapter.
Page 378 XMC4500 XMC4000 Family Memory Organization PBA0_STS Peripheral Bridge Status Register (0000 Reset Value: 0000 0000 Field Bits Type Description WERR Bufferable Write Access Error no write error occurred. write error occurred, interrupt request is pending. [31:1] Reserved bits. Write zeros PBA0_WADDR The Write Error Address Register keeps write access address that caused a bus error upon bufferable write attempt to a peripheral connected to PBA0 bridge.
Page 379 XMC4500 XMC4000 Family Memory Organization Field Bits Type Description WADDR [31:0] Write Error Address Address of the write access that caused a bus error on the bridge Master port. PBA1_STS The status register of PBA1 bridge indicates bus error occurrence for write access. Is meant to be used for errors triggered upon buffered writes.
Page 380 XMC4500 XMC4000 Family Memory Organization PBA1_WADDR PBA Write Error Address Register (0004 Reset Value: 0000 0000 WADDR WADDR Field Bits Type Description WADDR [31:0] Write Error Address Address of the write access that caused a bus error on the bridge Master port. Reference Manual 7-13 V1.6, 2016-07...
Page 381: Flash And Program Memory Unit (Pmu)
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Flash and Program Memory Unit (PMU) The Program Memory Unit (PMU) controls the Flash memory and the BROM and connects these to the system. The Prefetch unit maximizes system performance with higher system frequencies, by buffering instruction and data accesses to the Flash.
Page 382: Boot Rom (Brom)
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Boot ROM (BROM) The Boot ROM in PMU0 has a capacity of 16 KB. The BROM contains the Firmware with: • startup routines • bootstrap loading software. Details on the operations of the BROM are given in the chapter “Startup Modes”. 8.2.1 BROM Addressing The BROM is visible at one location, as can be seen in the memory map:...
Page 383: Operation
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Instruction ICode Bus Instruction Buffer Flash memory DCode Bus Data Buffer Data System Bus Figure 8-2 Prefetch Unit 8.3.2 Operation 8.3.2.1 Instruction Buffer The instruction buffer acts like a regular instruction cache with the characteristics described in the overview, optimized for minimum latency via the dedicated instruction interface.
Page 384: Pmu Interface
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) the DMA. CPU read accesses to the prefetch buffer are without any penalty i.e. single cycle access rate. The miss latency is minimized. The data interface is shared between DMA requests, CPU DCode bus requests and CPU System bus requests.
Page 385: Program Flash (Pflash)
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Program Flash (PFLASH) This chapter describes the embedded Flash module of the XMC4500 and its software interface. 8.4.1 Overview The embedded Flash module of XMC4500 includes 1.0 MB of Flash memory for code or constant data (called Program Flash).
Page 386: Definition Of Terms
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.4.2 Definition of Terms The description of Flash memories uses a specific terminology for operations and the hierarchical structure. Flash Operation Terms • Erasing: The erased state of a Flash cell is logical ‘0’. Forcing a cell to this state is called “erasing”.
Page 387: Flash Structure
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) by the user. The “UCBs” are the only part of the configuration sector that can be programmed and erased by the user. • Word-Line: A “word-line” consists of two pages, an even one and an odd one. In the PFLASH a word-line contains aligned 512 bytes.
Page 388: Flash Read Access
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Table 8-2 Sector Structure of PFLASH (cont’d) Sector Phys. Sector Size Offset Address 16 KB 01’0000 16 KB 01’4000 16 KB 01’8000 16 KB 01’C000 – 128 KB 02’0000 – 256 KB 04’0000 –...
Page 389: Flash Write And Erase Operations
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) The Prefetch generates the 4x64-bit bursts for code and data fetches from the cached address range in order to fill one cache line or the data buffer respectively. Data reads from the non-cached address range are performed with single 32-bit transfers. Following an inital Flash access, the PFLASH automatically starts a prefetch of the next linear address (even before it has been requested).
Page 390: Command Sequences
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Register read and write accesses are not affected by these modes. 8.4.7 Command Sequences All Flash operations except read are performed with command sequences. When a Flash bank is in read mode or page mode all write accesses to its reserved address range are interpreted as command cycle belonging to a command sequence.
Page 391 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) • UL: User protection level (xxx0 or xxx1 for user levels 0 and 1). • PWx: 32-bit password. Command Sequence Overview Table Table 8-4 summarizes all commands sequences. The following sections describe each command sequence in detail.
Page 392 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Reset to Read This function resets the command interpreter to its initial state (i.e. the next command cycle must be the 1st cycle of a sequence). A page mode is aborted. This command is the only one that is accepted without generating a SQER when the command interpreter has already received command cycles of a different sequence but is still not in command mode.
Page 393 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) This command is refused with SQER when the addressed Flash bank is not in page mode. SQER is also issued when PA addresses an unavailable Flash range or when PA does not point to a legal page start address.
Page 394: Flash Page Programming Example
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Disable Sector Write Protection The sector write protection belonging to user level “UL” is temporarily disabled by setting FSR.WPRODIS when the passwords PW0 and PW1 match their configured values in the corresponding UCB. The command fails by setting PROER when any of PW0 and PW1 does not match.
Page 395 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) The “Write Page” command triggers the actual write operation, transfering the 256 bytes data from the assembly buffer to the addressed page in the Flash. FSR.PROG is set with the last cycle of the “Write Page” command sequence, indicating that a program operation is started.
Page 396 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) S ta rt S e q u e n c e to p ro g ra m a F la s h p a g e E n te r P a g e M o d e L o a d P a g e u p to 3 2 L o a d P a g e o p e ra tio n s to fill a c o m p le te p a g e...
Page 397: Flash Protection
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.4.8 Flash Protection The Flash memory can be read and write protected. The protection is configured by programming the User Configuration Blocks “UCB”. For an effective IP protection the Flash read protection must be activated. This ensures system wide that the Flash cannot be read from external or changed without authorization.
Page 398: Flash Read Protection
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) If the confirmation code field is programmed with 8AFE 15C3 the UCB content is “confirmed” otherwise it is “unconfirmed”. The status flags FSR.PROIN, FSR.RPROIN and FSR.WPROIN0–2 indicate this confirmation state: • FSR.PROIN: set when any UCB is in the confirmed state.
Page 399 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Read Protection Status A read access to PFLASH fails with bus error under the following conditions: • Code fetch: FCON.DCF and FCON.RPA. • Data read: FCON.DDF and FCON.RPA. The read protection bit FCON.RPA is determined during startup by the protection configuration of UCB0.
Page 400: Flash Write And Otp Protection
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) The disabled state of read protection is controlled with the FCON.RPA=’0’ and indicated in the Flash Status Register with the RPRODIS bit (see Section 8.7.3.1). As long as read protection is disabled (and thus not active), the FCON-bits DDF and DCF can be cleared.
Page 401 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) • PROCON0.SxL and not(FSR.WPRODIS0) • PROCON1.SxL and not(PROCON0.SxL) and not(FSR.WPRODIS1) Thus with the password of UCB0 the write protection of sectors protected by user 0 and user 1 can be disabled, however with the password of UCB1 only those sectors that are only protected by user 1.
Page 402: System Wide Effects Of Flash Protection
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Resumption of write protection after disablement is performed with the “Resume Read/Write Protection” command, which is identical for user 0 and user 1. Generally, sector write protection will remain installed as long as it is configured and confirmed in the User Configuration Block belonging to the user.
Page 403: Margin Checks
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) PFLASH uses an ECC code with SEC-DED (Single Error Correction, Double Error Detection) capabilities. Each block of 64 data bits is accompanied with 8 ECC bits. Standard PFLASH ECC In the standard PFLASH ECC the 8-bit ECC value is calculated over 64 data bits. An erased data block (all bits ‘0’) has an ECC value of 00 .
Page 404: Interrupt Control
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.5.1 Interrupt Control The PMU and Flash module supports immediate error and status information to the user by interrupt generation. One CPU interrupt request is provided by the Flash module. The Flash interrupt can be issued because of following events: •...
Page 405: Handling Errors During Operation
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Note: A double-bit error trap during margin check can be disabled (via MARP register) and redirected to an interrupt request. 8.5.3 Handling Errors During Operation The previous sections described shortly the functionality of “error indicating” bits in the flash status register FSR.
Page 406: Pfoper "Operation Error
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) data is correct. Is the written data wrong, the whole sector must be erased and reprogrammed. 8.5.3.2 PFOPER “Operation Error” Fault conditions: ECC double-bit error detected in Flash module internal SRAM during a program or erase operation in PFLASH.
Page 407: Ver "Verification Error
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) • Write UC-Page to protected UCB. Attention: a protection violation can even occur when a protection was not explicitly installed by the user. This is the case when the Flash startup detects an error and starts the user software with read-only Flash (see Section 8.5.3.6).
Page 408: Pfsber/Dfsber "Single-Bit Error
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) • VER after erase: the erase operation can be repeated until VER disappears. Repeating the erase more than 3 times consecutively for the same sector is not recommended. After that it is better to ignore the VER, program the data and check its readability.
Page 409: Handling Flash Errors During Startup
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) • Each sector should be reprogrammed at most once, afterwards SBEs can be ignored. Due to the specificity of each application the appropriate usage and implementation of these measures (together with the more elaborate VER handling) must be chosen according to the context of the application.
Page 410 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Flash Sleep Mode As power reduction feature, the Flash module provides the Flash Sleep mode which can be selected by the user individually for the Flash. The Sleep mode can be requested by: •...
Page 411: Reset Control
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.6.3 Reset Control All PMU and Flash functionality is reset with the system reset with the exception of the register bits: FSR.PROG, FSR.ERASE, FSR.PFOPER. These bits are reset with the power-on reset. The flash will be automatically reset to the read mode after every reset.
Page 412 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) If a complete page can be spent as marker, the following recipe allows to reduce the marker size to 8 bytes. This recipe violates the rule that a page may be programmed only once.
Page 413: Clock
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.6.4 Clock The Flash interface is operating at the same clock speed as the CPU, . Depending on the frequency, wait states must be inserted in the Flash accesses. Further details onthe wait states configuration are give in Section 8.4.4.
Page 414: Pmu Id Register
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.7.1.1 PMU ID Register The PMU0_ID register is a read-only register, thus write accesses lead to a bus error trap. Read accesses are permitted in Privileged Mode PV and in User Mode. The PMU0_ID register is defined as follows: PMU0_ID PMU0 Identification Register...
Page 415: Prefetch Registers
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.7.2 Prefetch Registers This section describes the register of the Prefetch unit. Table 8-8 Registers Address Space Module Base Address End Address Note PREF 5800 4000 5800 7FFF Prefetch Module Registers Table 8-9 Registers Overview Short Name Description...
Page 416 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description IBYP Instruction Prefetch Buffer Bypass Instruction prefetch buffer not bypassed. Instruction prefetch buffer bypassed. IINV Instruction Prefetch Buffer Invalidate Write Operation: No effect. Initiate invalidation of entire instruction cache. Reserved Must be written with 0.
Page 417: Flash Registers
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.7.3 Flash Registers All register addresses are word aligned, independently of the register width. Besides word-read/write accesses, also byte or half-word read/write accesses are supported. The absolute address of a Flash register is calculated by the base address from Table 8-10 plus the offset address of this register from Table...
Page 418: Flash Status Definition
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.7.3.1 Flash Status Definition The Flash Status Register FSR reflects the overall status of the Flash module after Reset and after reception of the different commands. Sector specific protection states are not indicated in the FSR, but in the registers PROCON0, PROCON1 and PROCON2.
Page 419 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 3)4) PROG Programming State HW-controlled status flag. There is no program operation requested or in progress or just finished. Programming operation (write page) requested (from FIM) or in action or finished. Set with last cycle of Write Page command sequence, cleared with Clear Status command (if not busy) or with power-on reset.
Page 420 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 1)2)3) SQER Command Sequence Error No sequence error Command state machine operation unsuccessful because of improper address or command sequence. A sequence error is not indicated if the Reset to Read command aborts a command sequence.
Page 421 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description RPROIN Read Protection Installed No read protection installed Read protection and global write protection is configured and correctly confirmed in the User Configuration Block 0. Supported only for the master user (user zero). HW-controlled status flag 1)5) RPRODIS...
Page 422 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 1)5) WPRODIS0 Sector Write Protection Disabled for User 0 All protected sectors of user 0 are locked if write protection is installed All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection.
Page 423: Flash Configuration Control
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 2,3,7, Reserved 9,13, Read zero, no write 15,17, 20,24, 27, 29 Note: The footnote numbers of FSR bits describe the specific reset conditions: 1)Cleared with System Reset 2)Cleared with command “Reset to Read”...
Page 424 One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer. Set this bit only when requested by Infineon. IDLE Dynamic Flash Idle Normal/standard Flash read operation Dynamic idle of Program Flash enabled for power saving;...
Page 425 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description ESLDIS External Sleep Request Disable External sleep request signal input is enabled Externally requested Flash sleep is disabled The ‘external’ signal input is connected with a global power-down/sleep request signal from SCU.
Page 426 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description Disable Any Data Fetch from Flash This bit enables/disables the data read access to the Flash memory area (Program Flash and Data Flash). Once set, this bit can only be cleared when RPA=’0’. This bit is automatically set with reset and is cleared during ramp up, if no RP installed, and during startup (BROM) in case of internal start out of Flash.
Page 427 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 1) WSPFLASH = 0 deviates from this formula and results in the same timing as WSPFLASH = 1 Note: The default numbers of wait states represent the slow cases. This is a general proceeding and additionally opens the possibility to execute higher frequencies without changing the configuration.
Page 428: Flash Identification Register
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.7.3.3 Flash Identification Register The module identification register of Flash module is directly accessible by the CPU via PMU access. This register is mapped into the space of the Flash Interface Module’s registers (see Table 8-11).
Page 429: Margin Check Control Register
XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) 8.7.3.4 Margin Check Control Register MARP Margin Control Register PFLASH (1018 Reset Value: 0000 0000 MARGIN Field Bits Type Description MARGIN [3:0] PFLASH Margin Selection 0000 Default, Standard (default) margin. 0001 Tight0, Tight margin for 0 (low) level.
Page 430 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) The Flash Protection Configuration registers PROCONx are loaded out of the user’s configuration block directly after reset during ramp up. For software the three PROCONx registers are read-only registers. PROCON0 Flash Protection Configuration Register User 0 (1020 Reset Value: 0000 XXXX S10_...
Page 431 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 13, 12, Reserved deliver the corresponding UCB0 entry. Shall be configured to 0. [31:16], Reserved Always reads as 0. PROCON1 Flash Protection Configuration Register User 1 (1024 Reset Value: 0000 XXXX S10_ S9L S8L S7L S6L S5L S4L S3L S2L S1L S0L...
Page 432 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 13, 12, Reserved Deliver the corresponding UCB1 entry. Shall be configured to 0. [31:16], Reserved 15, 14 Always reads as 0. PROCON2 Flash Protection Configuration Register User 2 (1028 Reset Value: 0000 XXXX S10_...
Page 433 XMC4500 XMC4000 Family Flash and Program Memory Unit (PMU) Field Bits Type Description 13, 12, Reserved Deliver the corresponding UCB2 entry. Shall be configured to 0. [31:16], Reserved 15, 14 Always reads as 0. Reference Manual 8-53 V1.6, 2016-07 PMU, V1.8 Subject to Agreement on the Use of Product Information...
Page 434 XMC4500 XMC4000 Family System Control System Control Reference Manual V1.6, 2016-07 Subject to Agreement on the Use of Product Information...
Page 435: Window Watchdog Timer (Wdt)
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) Window Watchdog Timer (WDT) Purpose of the Window Watchdog Timer module is improvement of system integrity. WDT triggers the system reset or other corrective action like e.g. non-maskable interrupt if the main program, due to some fault condition, neglects to regularly service the watchdog (also referred to as “kicking the dog”, “petting the dog”, “feeding the watchdog”...
Page 436: Block Diagram
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) Table 9-1 Application Features Feature Purpose/Application System reset upon Bad Servicing Triggered to restore system stable operation and ensure system integrity Servicing restricted to be within Allows to consider minimum and maximum defined boundaries of refresh window software timing Independent clocks To ensure that WDT counts even in case...
Page 437: Time-Out Mode
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) PBA2 Bus Interface SCU.HCU wdt_service external watchdog Registers SCU.GCU HALTED wdt_alarm SCU.RCU wdt_rst_req Timer SCU.CCU Figure 9-1 Watchdog Timer Block Diagram Time-Out Mode An overflow results in an immediate reset request going to the RCU of the SCU via the signal wdt_rst_req whenever the counter crosses the upper bonundary it triggers an overflow event pre-warning is not enabled with register.
Page 438: Pre-Warning Mode
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) First serviced serviced overflow Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 9-2 Reset without pre-warning The example scenario depicted in Figure 9-2 shows two consecutive service pulses generated from WDT module as the result of successful servicing within valid time windows.
Page 439: Bad Service Operation
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) First Second serviced overflow overflow Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 9-3 Reset after pre-warning The example scenario depicted in Figure 9-3 shows service pulse generated from WDT module as the result of successful servicing within valid time window.
Page 440 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) serviced in wrong serviced window Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 9-4 Reset upon servicing in a wrong window The example in Figure 9-4 shows servicing performed outside of valid servicing window. Attempt to service WDT while counter value remains below the Window Lower Bound results in immediate reset request on wdt_rst_req signal.
Page 441: Service Request Processing
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) The example in Figure 9-5 shows servicing performed within a valid servicing window but with an invalid Magic Word. Attempt to write a wrong word to the register results in immediate reset request on wdt_rst_req signal. Service Request Processing The WDT generates watchdog alarm service requests via wdt_alarm output signal upon first counter overflow over Watchdog Upper Bound when pre-warning mode is enabled.
Page 442: Initialization & Start Of Operation
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) 9.8.1 Initialization & Start of Operation Complete WDT module initialization is required after system reset. • check reason for last system reset in order to determine power state – read out SCU_RSTSTAT.RSTSTAT register bit field to determine last system reset cause –...
Page 443: Software Stop & Resume Operation
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) • service the watchdog – check current timer value in WDT_TIM register against programmed time window – write magic word to WDT_SRV register within valid time window 9.8.3 Software Stop & Resume Operation The WDT module can be stopped and re-started at any point of time for e.g.
Page 444 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) • alarm event – exception routine (system trap or service request) clearing WDT_WDTSTAT register with WDT_WDTCLR register • service the watchdog – check current timer value in WDT_TIM register against programmed time window –...
Page 445: Registers
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) Registers Registers Overview All these registers can be read in User Mode, but can only be written in Supervisor Mode. The absolute register address is calculated by adding: Module Base Address + Offset Address Table 9-2 Registers Address Space Module...
Page 446 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) WDT ID Register Reset Value: 00AD C0XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_NUMBER MOD_TYPE MOD_REV...
Page 447 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) Field Bits Type Description Pre-warning disables pre-warning enables pre-warning, Debug Suspend watchdog timer is stopped during halting mode debug, watchdog timer is not stopped during halting mode debug [15:8] Service Indication Pulse Width Pulse width (SPW+1) of service indication in f cycles...
Page 448 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) The actual watchdog timer register count value. This register can be read by software in order to determine current position in the WDT time window. Reset Value: 0000 0000 WDT Timer Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Bits Type Description...
Page 449 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) WDT Window Upper Bound Register (14 Reset Value: FFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Bits Type Description...
Page 450: Interconnects
XMC4500 XMC4000 Family Window Watchdog Timer (WDT) Field Bits Type Description [31:1] Reserved WDTCLR The status register contains sticky bitfield indicating occurrence of alarm condition. WDTCLR WDT Clear Register (001C Reset Value: 00000000 Field Bits Type Description ALMC Pre-warning Alarm clears pre-warning alarm no-action [31:1]...
Page 451 XMC4500 XMC4000 Family Window Watchdog Timer (WDT) Table 9-4 Pin Table (cont’d) Input/Output Connected To Description HALTED In halting mode debug. HALTED remains asserted while the core is in debug. Service Request Connectivity wdt_alarm SCU.GCU pre-warning alarm wdt_rst_req SCU.RCU reset request Reference Manual 9-17 V1.6, 2016-07...
Page 452: Real Time Clock (Rtc)
XMC4500 XMC4000 Family Real Time Clock (RTC) Real Time Clock (RTC) Real-time clock (RTC) is a clock that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time in a digital format for clock displays and real-time actions.
Page 453: Rtc Operation
XMC4500 XMC4000 Family Real Time Clock (RTC) The main building blocks of the RTC is Time Counter implementing real time counter and RTC registers containing multi-field registers for the time counter and alarm programming register. Dedicated fields represent values for elapsing second, minutes, hours, days, days of week, months and years.
Page 454: Register Access Operations
XMC4500 XMC4000 Family Real Time Clock (RTC) seconds minutes hours days months years Alarm Time (ATIM0 & ATIM1) alarm Real Time (TIM0 & TIM1) days of week Prescaler 1 second seconds minutes hours days months years tick periodic_event Periodic Service Request Logic Figure 10-2 Block Diagram of RTC Time Counter Occurrence of an internal timer event is stored in the service request raw status register RAWSTAT...
Page 455: Service Request Processing
XMC4500 XMC4000 Family Real Time Clock (RTC) After wake-up from hibernate state the content of the mirror registers TIM0 TIM1 undefined until the first update of the corresponding RTC timers occurs and is propagated to the registers. 10.4 Service Request Processing The RTC generates service requests upon: •...
Page 456: Debug Behavior
XMC4500 XMC4000 Family Real Time Clock (RTC) 10.6 Debug behavior The RTC clock does not implement dedicated debug mechanisms. 10.7 Power, Reset and Clock RTC is instantiated entirely in hibernate domain and remains powered up when hibernate domain is powered up. Supply voltage is passed either from VDDP or VBAT pin as specified in the SCU chapter.
Page 457: Re-Configuration & Re-Start Of Operation
XMC4500 XMC4000 Family Real Time Clock (RTC) 10.8.2 Re-configuration & Re-start of Operation Reset and re-initialization of the RTC module may be required without complee power up sequence of the hibernate domain. • apply and release reset of hibernate domain reset –...
Page 458 XMC4500 XMC4000 Family Real Time Clock (RTC) – check SCU_MIRRSTS to ensure that no transfer over serial interface is pending to the RTC_CTR register – set TAE bit field of RTC_CTR register in order enable individual periodic timer events • enable service request for timer alarm events in RTC module –...
Page 459: Registers
XMC4500 XMC4000 Family Real Time Clock (RTC) 10.9 Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 10-2 Registers Address Space Module Base Address End Address Note 5000 4A00 5000 4BFF Accessible via Mirror Registers Table 10-3...
Page 460 XMC4500 XMC4000 Family Real Time Clock (RTC) RTC ID Register Reset Value: 00A3 C0XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_NUMBER MOD_TYPE MOD_REV...
Page 461 XMC4500 XMC4000 Family Real Time Clock (RTC) Field Bits Type Description Timer Alarm Enable for Hibernation Wake-up disable timer alarm enable timer alarm ESEC Enable Seconds Comparison for Hibernation Wake-up disabled enabled EMIC Enable Minutes Comparison for Hibernation Wake-up disabled enabled EHOC Enable Hours Comparison for Hibernation...
Page 462 XMC4500 XMC4000 Family Real Time Clock (RTC) RAWSTAT RTC Raw Service Request Register contains raw status info i.e. before status mask takes effect on generation of service requests. This register serves debug purpose but can be also used for polling of the status without generating serice requests. RAWSTAT RTC Raw Service Request Register Reset Value: 0000 0000...
Page 463 XMC4500 XMC4000 Family Real Time Clock (RTC) STSSR RTC Service Request Status Register contains status info reflecting status mask effect on generation of service requests. This register needs to be accessed by software in order to determine the actual cause of an event. STSSR RTC Service Request Status Register (0C Reset Value: 0000 0000...
Page 464 XMC4500 XMC4000 Family Real Time Clock (RTC) MSKSR RTC Service Request Mask Register contains masking value for generation control of service requests or interrupts. MSKSR RTC Service Request Mask Register (10 Reset Value: 0000 0000 Field Bits Type Description MPSE Periodic Seconds Interrupt Mask disable enable...
Page 465 XMC4500 XMC4000 Family Real Time Clock (RTC) Field Bits Type Description Reserved [31:9] CLRSR RTC Clear Service Request Register serves purpose of clearing sticky bits of RAWSTAT STSSR registers. Write one to a bit in order to clear it is set. Writing zero has no effect on the set nor reset bits.
Page 466 XMC4500 XMC4000 Family Real Time Clock (RTC) Field Bits Type Description RPYE Periodic Years Interrupt Clear no effect clear status bit Alarm Interrupt Clear no effect clear status bit Reserved [31:9] ATIM0 RTC Alarm Time Register 0 serves purpose of programming single alarm time at a desired point of time reflecting comparison configuration in the for individual fields against...
Page 467 XMC4500 XMC4000 Family Real Time Clock (RTC) Field Bits Type Description [13:8] Alarm Minutes Compare Value Match of minutes timer count to this value triggers alarm minutes interrupt. Setting value equal or above 3C results in setting the field value to 0 [20:16] Alarm Hours Compare Value Match of hours timer count to this value triggers...
Page 468 XMC4500 XMC4000 Family Real Time Clock (RTC) ATIM1 RTC Alarm Time Register 1 Reset Value: 0000 0000 Field Bits Type Description [11:8] Alarm Month Compare Value Match of months timer count to this value triggers alarm month interrupt. Setting value equal or above the number of days of the actual month count results in setting the field value to 0 [31:16] rw...
Page 469 XMC4500 XMC4000 Family Real Time Clock (RTC) TIM0 RTC Time Register 0 Reset Value: 0000 0000 Field Bits Type Description [5:0] Seconds Time Value Setting value equal or above 3C results in setting the field value to 0 Value can only be written, when RTC is disabled. After wake-up from hibernate, value is undefined until first update of RTC.
Page 470 XMC4500 XMC4000 Family Real Time Clock (RTC) Field Bits Type Description [28:24] Days Time Value Setting value equal or above the number of days of the actual month count results in setting the field value to 0 Value can only be written, when RTC is disabled. After wake-up from hibernate, value is undefined until first update of RTC.
Page 471: Interconnects
XMC4500 XMC4000 Family Real Time Clock (RTC) Field Bits Type Description DAWE [2:0] Days of Week Time Value Setting value above 6 results in setting the field value to 0 Value can only be written, when RTC is disabled. After wake-up from hibernate, value is undefined until first update of RTC.
Page 472: System Control Unit (Scu)
XMC4500 XMC4000 Family System Control Unit (SCU) System Control Unit (SCU) The SCU is the SoC power, reset and a clock manager with additional responsibility of providing system stability protection and other auxiliary functions. 11.1 Overview The functionality of the SCU described in this chapter is organized in the following sub- chapters, representing different aspects of system control: •...
Page 473: Block Diagram
XMC4500 XMC4000 Family System Control Unit (SCU) – Individual peripheral clock gating – Input clock selection – Clock Generation – Clock Distribution – Clock Supervision – Power Management – RTC Clock 11.1.2 Block Diagram The block diagram shown in Figure 11-1 reflects logical organization of the System Control Unit.
Page 474 XMC4500 XMC4000 Family System Control Unit (SCU) Bus Interface SCU Register Interface Parity Error Trap Request RTC Module Interface Service Request NMI/IRQ Retention Memory EVR Module Hibernate Control I/O Control Wake-up Triggers XTAL1 Reset Requests XTAL2 Reset Signals EXTCLK Clock Signals Figure 11-1 SCU Block Diagram Interface of General Control Unit The General Control Unit GCU has a memory fault interface to the memory validation...
Page 475 XMC4500 XMC4000 Family System Control Unit (SCU) each power related reset. Reset requests are coming to the unit from the watchdog, the CPU and the test control unit. The RCU is providing the reset signals to all other units of the chip in the Core power domain.
Page 476: Miscellaneous Control Functions
XMC4500 XMC4000 Family System Control Unit (SCU) 11.2 Miscellaneous Control Functions System Control implements system management functions accessible via GCU registers. General system control including various auxiliary function is performed in General Control Unit (GCU). 11.2.1 Startup Software Support Externally driven boot mode pins determine the boot mode after a power on reset. It also possible for applications to decide the boot mode.
Page 477: Service Requests
XMC4500 XMC4000 Family System Control Unit (SCU) 11.2.2 Service Requests Service request events listed in Table 11-1 can result in assertion of a regular interrupt or an NMI. Please refer to SRMSK NMIREQEN register description. The interrupt structure is shown in Figure 11-2 .
Page 478: Memory Parity Protection
XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-1 Service Requests Service Request Name Service Request Short Name WDT pre-warning PRWARN RTC Periodic Event RTC Alarm DLR Request Overrun DLROVR HDCLR Mirror Register Updated HDCLR HDSET Mirror Register Updated HDSET HDCR Mirror Register Updated HDCR OSCSICTRL Mirror Register Updated...
Page 479 XMC4500 XMC4000 Family System Control Unit (SCU) directly and are internal to peripherals are capable of generating system traps resulting in NMI. Parity trap requests get enabled with PETE register implementing individual control for each memory. Parity error signalling with trap generation is not recommended to be used for memories capable of bus error generation and therefore should be disabled.
Page 480: Trap Generation
XMC4500 XMC4000 Family System Control Unit (SCU) The logic is controlled by registers PMTSR PMTPR . Via bit field PMTPR .PWR a parity value can be written to any address of every memory for software driven testing purpose. The parity control software test update has to be enabled with bit PMTSR each memory individually.
Page 481: Die Temperature Measurement
XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-2 SCU Trap Request Overview Source of Trap Short Trap Name OSC_HP Oscillator Watchdog Trap SOSCWDGT USB VCO Lock Trap UVCOLCKT System VCO Lock Trap SVCOLCKT Parity Error Trap Brownout Trap BRWNT OSC_ULP Oscillator Watchdog Trap ULPWDGT Peripheral Bus 0 Write Error Trap...
Page 482: Offset Adjustment
XMC4500 XMC4000 Family System Control Unit (SCU) The accuracy of the measurement can be improved with adjustment of the OFFSET and GAIN bit fields in the DTSCON register. The following formula can be applied in order to reflect relation between the actual adjustment settings and the resulting value in the DTSSTAT register:...
Page 483: Gain Adjustment
XMC4500 XMC4000 Family System Control Unit (SCU) RESULT max + OFFSET positive offset negative offset max - OFFSET min + OFFSET positive offset negative offset min - OFFSET °C Figure 11-5 Offset adjustment of the RESULT curve Offset adjustment has direct effect on the RESULT value in DTSSTAT register as illustrated in...
Page 484: Retention Memory
XMC4500 XMC4000 Family System Control Unit (SCU) RESULT 1023 1023 - GAIN °C Figure 11-6 Gain adjustment of the RESULT curve The gain error can be minimzed using 6-bit GAIN bit field of DTSCON register where 0 corresponds with a maximum gain and value of 63 corresponds with minimum gain i.e. RESULT value reduced by 63 at the upper imaginary end of the curve.
Page 485: Out Of Range Comparator Control
XMC4500 XMC4000 Family System Control Unit (SCU) 11.2.7 Out of Range Comparator Control The out of range comparator serves the purpose of overvoltage monitoring for analog input pins of the chip. A number of analog channels are associated with dedicated pads connected to inputs of analog modules.
Page 486: System States
XMC4500 XMC4000 Family System Control Unit (SCU) Logic in the hibernate domain, mainly the real-time clock RTC, hibernate control and retention memory, is supplied by an auxiliary power supply using an additional power pad. The auxiliary voltage, supplied from e.g. a coin battery, enables the RTC to operate while the main supply is switched off.
Page 487 XMC4500 XMC4000 Family System Control Unit (SCU) source. Unused peripherals might be stopped. Stopping a peripheral means that the peripheral i put into reset and the clock to this peripherals is disabled. After a cold start the hibernate domain stays disabled until activated by user code. Sleep State The Sleep state of the system corresponds to the Sleep state of the CPU.
Page 488: Hibernate Domain Operating Modes
XMC4500 XMC4000 Family System Control Unit (SCU) • RTC Alarm Event • RTC Periodic Event • OSC_ULP Watchdog Event The system can only wake-up from Hibernate if is present. An external power supply can be switched on by the HIBOUT signal of the Hibernate Control Unit. All blocks outside of the Hibernate domain will see a complete power-up sequence upon wake-up.
Page 489 XMC4500 XMC4000 Family System Control Unit (SCU) voltage System Supply Active Mode Hibernate Mode Active Mode VDDP 3.3 V VBAT VDDC 1.3 V time Figure 11-10 Hibernate controlled with external voltage regulator The externally controlled Hibernate mode is realized with HIB pin and external power supply device.
Page 490: Embedded Voltage Regulator (Evr)
XMC4500 XMC4000 Family System Control Unit (SCU) voltage System Supply OFF State Active Mode Battery insertion 3.3 V VBAT VDDC 1.3 V time Figure 11-11 Initial power-up sequence One of the valid power-up scenarios assumes that battery will be installed, possibly soldered, before core supply is available (see Figure 11-11 ).
Page 491: Supply Watchdog (Swd)
XMC4500 XMC4000 Family System Control Unit (SCU) 11.3.6 Supply Watchdog (SWD) Figure 11-12 shows the operation of the supply monitor. The supply watchdog compares the supply voltage against the reset threshold . The Data Sheet defines the nominal value and applied hysteresis. voltage time PORST...
Page 492: Hibernate Domain Power Management
XMC4500 XMC4000 Family System Control Unit (SCU) A drop of supply voltage to a critical threshold level programmed by the user can be signalized to the CPU with an NMI. An emergency corrective action may involve e.g. reduction of current consumption by switching of some modules or some interaction with external devices that should result in recovery of the supply voltage level.
Page 493: Hibernate Domain Pin Functions
XMC4500 XMC4000 Family System Control Unit (SCU) Hibernation Support The entry of the hibernate state is configured via the register HDCR by setting of the HIB bit. The HIBOUT bit in conjunction with selected HIBIOnPOL bit of HDCR register drives HIB_IO_n pad.
Page 494: System Level Integration
XMC4500 XMC4000 Family System Control Unit (SCU) WWDT_SERVICE_OUT HIB_SR0 HIB_SR1 Core Domain Isolation Isolation Isolation Cell Cell Cell Hibernate Domain HIB_IO_0 HIBIO0SEL[1:0] GPI0SEL HIBOUT Hibernate Control WKUP WKUPSEL HIB_IO_1 HIBIO1SEL[1:0] RTC_XTAL_1 (Digital GPI) RTC_XTAL_1 Figure 11-13 Alternate function selection of HIB_IO_0 and HIB_IO_1 pins of Hibernate Domain 11.4.3 System Level Integration...
Page 495 XMC4500 XMC4000 Family System Control Unit (SCU) Externally Controlled Hibernate mode The Externally Controlled Power Supply scheme require external devices on in order to fully support power management related functions. The external power supply needs to support on/off control of the VDDP voltage generation.
Page 496: Reset Control
XMC4500 XMC4000 Family System Control Unit (SCU) supply core domain External Voltage 3.3V VDDP Buck Regulator alarm Converter 12-48V VBAT SHTDN hibernate Hibernate LOW = ON VBAT Control domain HIB_IO_0 32kHz Clock WAKE bi-directional Retention open drain driver Memory battery and/or capacitor Figure 11-15 System Level Power Control example - externally controlled with single pin After power up and before entering Hibernate mode the HIB_IO_0 needs to be...
Page 497 XMC4500 XMC4000 Family System Control Unit (SCU) • Debug Reset, DBGRESET Power-on Reset (PORESET) A complete reset of the core domain of the device is executed upon power-up. Whenever the supply is ramped-up and crossing the PORST voltage threshold the power-on reset is released.
Page 498: Peripheral Reset Control
XMC4500 XMC4000 Family System Control Unit (SCU) 11.5.2 Peripheral Reset Control Software can activate the reset of all peripherals individually via the registers PRSET0 PRSET1 PRSET2 PRSET3 . The default state is that all peripherals are in reset after power-up. A return to the default state of a peripheral can be performed by forcing it to reset state by a separate reset.
Page 499 XMC4500 XMC4000 Family System Control Unit (SCU) The CGU provides in parallel three clocks to the CSU: • USB PLL clock PLLUSB • System PLL output clock • internally generated clock from the Backup Clock Source. clock of 32.768 kHz is generated in the Standby Clock Generation Unit STDBY (SCGU) of the hibernate domain by either the external crystal oscillator OSC_ULP or by Internal Slow Clock Source.
Page 500: Clock Sources
XMC4500 XMC4000 Family System Control Unit (SCU) 11.6.2 Clock Sources The system has multiple clock sources distributed over the core power domain and the hibernate power domain. The source clock for CGU can be supplied from: • internally generate in the Backup Clock Source •...
Page 501: Clock System Overview
XMC4500 XMC4000 Family System Control Unit (SCU) Clock Generation Unit PLLUSB PLLUSB OSCHP XTAL1/CLKIN OSC_HP XTAL2 Backup 32.768 kHz Clock reference clock Source Figure 11-17 Clock Generation Block Diagram 11.6.3 Clock System Overview The clock selection unit CSU provides the following clocks to the system: Table 11-4 Clock Signals Clock name...
Page 502: Clock System Architecture
XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-4 Clock Signals (cont’d) Clock name From/to Description module or pin Internal Clock Signals System PLL System PLL output clock USB PLL USB PLL output clock PLLUSB OSC_HP External crystal oscillator output clock Internal System Backup Block Backup Clock...
Page 503 XMC4500 XMC4000 Family System Control Unit (SCU) • , external crystal oscillator clock, bypassing PLL Please note that in dependence of the PLL mode setting the PLL output clock either a scaled version of the VCO clock in normal mode or a scaled version of one of the input clocks.
Page 504 XMC4500 XMC4000 Family System Control Unit (SCU) Some limitations apply on clock ratio combinations between . Only PERIPH divider setting listed in the table Table 11-5 are allowed for the PERIPH clocks. All other clock dividers settings must be prohibited by application software in order to avoid invalid clock ratios leading to system malfunctions.
Page 505 XMC4500 XMC4000 Family System Control Unit (SCU) CPU Clock Selection The CPU clock may be equal to or a half of the system clock Peripheral Bus Clock Selection The Peripheral Bus clock is derived from the clock and may be equal t or a half of .
Page 506: High Precision Oscillator Circuit (Osc_Hp)
XMC4500 XMC4000 Family System Control Unit (SCU) EXTCLK Divider Divider ECLKCR.ECKDIV ECLKCR.ECKSEL Figure 11-19 External Clock Selection 11.6.4 High Precision Oscillator Circuit (OSC_HP) The high precision oscillator circuit can drive an external crystal or accepts an external clock source. It consists of an inverting amplifier with XTAL1 as input, and XTAL2 as output.
Page 507: Backup Clock Source
XMC4500 XMC4000 Family System Control Unit (SCU) XTAL1 OSCHP External Clock Signal OSC_HP XTAL2 leave unconnected Figure 11-20 External Clock Input Mode for the High-Precision Oscillator External Crystal Mode For the external crystal mode an external oscillator load circuitry is required. The circuitry must be connected to both pins, XTAL1 and XTAL2.
Page 508: Main Pll
XMC4500 XMC4000 Family System Control Unit (SCU) source during normal operation. While in prescaler mode this clock is automatically used as emergency clock if the external clock failure is detected. Clock adjustment is required to reach desired level of precision. The backup clock source provides two adjustment procedures: •...
Page 509 XMC4500 XMC4000 Family System Control Unit (SCU) and accordingly controls the frequency of the VCO ( ). A PLL lock detection unit monitors and signals this condition. The phase detection logic continues to monitor the two clocks and adjusts the VCO clock if required. The following figure shows the PLL block structure.
Page 510 XMC4500 XMC4000 Family System Control Unit (SCU) PLLSTAT.FINDIS Divider Divider Lock Detect. Divider Osc. PLLCON0. VCOBYP PLL Block Figure 11-22 PLL Normal Mode It is strongly recommended to apply even value of P and K2 Divider parameters in order to minimize PLL output clock jitter effect. Please find PLL configuration examples values Table 11-6 Table 11-6 PLL example configuration values...
Page 511 XMC4500 XMC4000 Family System Control Unit (SCU) • Register Values – PLLCON0.FINDIS = 0 – PLLSTAT.VCOBYST = 0 – PLLSTAT.VCOLOCK = 1 – PLLSTAT.PLLLV = 1 – PLLSTAT.PLLLH = 1 Operation on the Normal Mode does require an input clock frequency of .
Page 512: Configuration And Operation Of The Prescaler Mode
XMC4500 XMC4000 Family System Control Unit (SCU) interface. The duty cycles values for the different K2-divider values are defined in the Data Sheet. PLL VCO Lock Detection The PLL has a lock detection that supervises the VCO part of the PLL in order to differentiate between stable and unstable VCO circuit behavior.
Page 513 XMC4500 XMC4000 Family System Control Unit (SCU) Divider Osc. OSCCON.PLLLV PLLCON0. VCOBYP OSCCON.PLLHV PLL Block Figure 11-23 PLL Prescaler Mode Diagram The Prescaler Mode is selected by the following settings • PLLCON0.VCOBYP = 1 The Prescaler Mode is entered when the following requirements are all together valid: •...
Page 514: Bypass Mode
XMC4500 XMC4000 Family System Control Unit (SCU) 11.6.6.4 Bypass Mode The bypass mode is used only for testing purposes. In Bypass Mode the input clock is directly connected to the PLL output The output frequency is given by: (11.3) f PLL f OSC 11.6.6.5 System Oscillator Watchdog (OSC_WDG) The oscillator watchdog monitors the incoming clock frequency...
Page 515: Vco Power Down Mode
XMC4500 XMC4000 Family System Control Unit (SCU) clears all three bits PLLSTAT .PLLSP, PLLSTAT .PLLLV, and PLLSTAT .PLLHV all three trap status flags will be set. Therefore all three flags should be cleared before the trap generation is enabled again. The trap disabling-clearing-enabling sequence should also be used if only bit PLLCON0 .OSCVAL is set without any modification of...
Page 516: Alternative Internal Clock Calibration
XMC4500 XMC4000 Family System Control Unit (SCU) that the reference clock generated in the Hibernate domain is activated prior to STDBY enabling this method of clock calibration. 11.6.7.3 Alternative Internal Clock Calibration An alternative system clock calibration can be performed by programming of the system PLL with register values reflecting individual chip calibration characteristics determined by the CLKCALCONST...
Page 517 XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-7 PLL example configuration values Target Frequency TRIM Constant P Parameter N Parameter K2 Parameter [MHz] Reference Manual 11-46 V1.6, 2016-07 SCU, V3.6 Subject to Agreement on the Use of Product Information...
Page 518: Usb Pll
XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-7 PLL example configuration values (cont’d) Target Frequency TRIM Constant P Parameter N Parameter K2 Parameter [MHz] Note: The values of P, N and K2 configuration parameters specified in Table 11-7 should must decremented by one before programmed into corresponding registers.
Page 519 XMC4500 XMC4000 Family System Control Unit (SCU) The output frequency is given by: (11.6) ⋅ ---------- f f PLLUSB P 2 ⋅ Operation of the PLLUSB require an input clock frequency of The following requirement must be fulfilled regarding the frequency of (see).
Page 520: Ultra Low Power Oscillator
XMC4500 XMC4000 Family System Control Unit (SCU) Note: Re-configuration of the P-Divider before the USBPLL has locked must be avoided. 11.6.9 Ultra Low Power Oscillator The ultra low power oscillator is providing a real time clock source of 32.768 kHz when paired with an external crystal.
Page 521: Power, Reset And Clock
XMC4500 XMC4000 Family System Control Unit (SCU) 11.8 Power, Reset and Clock The SCU module consists of sub-modules that interact with different power, clock and reset domains. Some of the sub-modules are controlled via dedicated interfaces across the power, clock and reset boundries.The sub-modules are considered parts of the SCU in the functional sense therefore the complete SCU module is considered a multi domain circuit.
Page 522: Initialization And System Dependencies
XMC4500 XMC4000 Family System Control Unit (SCU) 11.9 Initialization and System Dependencies The initialization sequence of the XMC4500 is a process taking place before user application software takes control of the system and is comprising of two major phases (see Figure 11-25 ), split in several distinctive steps: Hardware Controlled Initialization Phase...
Page 523: Power-Up
XMC4500 XMC4000 Family System Control Unit (SCU) Hardware Controlled Initialization Phase Power-Up Power-on Reset Release Backup Clock Generation Start System Reset Release Boot Code Execution Configuration of Clock System Idividual Module Reset Release Configuration of Special System Functions Configuration of Miscellaneous Functions Initialization Completed Start of Application...
Page 524: Power-On Reset Release
XMC4500 XMC4000 Family System Control Unit (SCU) 11.9.2 Power-on Reset Release The XMC4500 implements bi-directional pin PORST for the Power-on Reset PORESET control. The internal Power-on Reset generation is based on the supply and core voltage validation. The PORST pin may be used either to control the PORESET from an external source in the system or to control the reset of external components from the XMC4500.
Page 525: System Reset Release
XMC4500 XMC4000 Family System Control Unit (SCU) Reset Master VDDP VDDP XMC4000 Reset Slave PORST PORESET BUTTON Power Validation Manual Reset VDDP Device 1 Device 2 RESET RESET RESET RESET Internal Reset Internal Reset Device 3 Device n RESET RESET RESET RESET Figure 11-26 System Level Power On Reset Control...
Page 526 XMC4500 XMC4000 Family System Control Unit (SCU) recommended to keep the unused modules in reset state in order to reduce power consumption. It is also highly recommended to ensure that clock of the corresponding modules are active before individual peripheral reset release. Reference Manual 11-55 V1.6, 2016-07...
Page 527: Clock System Setup
XMC4500 XMC4000 Family System Control Unit (SCU) 11.9.4 Clock System Setup The following system clocking modes are supported: • PLL Normal • PLL Prescaler • Backup Clock The default clock signal available after power-up is the internally generated Backup Clock .
Page 528 XMC4500 XMC4000 Family System Control Unit (SCU) Clock init start Switch the f Backup Clock Source clock trimming Factory Automatic trimming mode Check-and-set the Check-and-set the f FTOR Bit in PLLCON1 as the Stanby Clock Set the AORTEN bit in Reset the FTOR bit in Switch on f and wait...
Page 529: Configuration Of Special System Functions
XMC4500 XMC4000 Family System Control Unit (SCU) After reset release the system is clocked with a clock derived from the Backup Clock source. If a PLL output clock is required as the system clock source then it is necessary to initialize the respective PLL with a software routine. For details please refer to PLL section in “Main PLL”...
Page 530: Configuration Of Miscellaneous Functions
XMC4500 XMC4000 Family System Control Unit (SCU) of the main supply of the chip i.e. VDDP, the hibernate domain will remain intact if is still supplied. For details of hibernate control please refer to “Hibernate Control” on Page 11-21 . For details of RTC module control please refer to RTC chapter. Watchdog Timer The Watchdog Timer requires a clock source selection and activation.
Page 531 XMC4500 XMC4000 Family System Control Unit (SCU) Die Temperature Sensor The Die Temperature Sensor allows to perform temperature measurements of the die. DTSCON The module needs to be enabled with register before used. For details please refer to “Die Temperature Measurement” on Page 11-10 Out of Range Comparators The out of range comparator serves the purpose of overvoltage monitoring for analog input pins of the chip.
Page 532: Registers
XMC4500 XMC4000 Family System Control Unit (SCU) 11.10 Registers This section describes the registers of SCU. Most of the registers are reset SYSRESET reset signal but some of the registers can be reset only with PORST reset. Table 11-9 Base Addresses of sub-sections of SCU registers Short Name Description Offset...
Page 533 XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-11 Registers Overview (cont’d) Short Name Register Long Name Offset Access Mode Description Addr. Read Write IDMANUF Manufactory ID 0008 U, PV Page 11-67 STCON Start-up Control 0010 U, PV Page 11-68 GPR0 General Purpose 002C...
Page 534 XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-11 Registers Overview (cont’d) Short Name Register Long Name Offset Access Mode Description Addr. Read Write RMADATA Retention Memory 00CC U, PV U, PV Page 11-92 Access Data Register PEEN Parity Error Enable 013C U, PV Page 11-93...
Page 535 XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-11 Registers Overview (cont’d) Short Name Register Long Name Offset Access Mode Description Addr. Read Write HCU Registers HDSTAT Hibernate Domain Status 0000 U, PV Page 11-118 Register HDCLR Hibernate Domain Status 0004 U, PV Page 11-119...
Page 536 XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-11 Registers Overview (cont’d) Short Name Register Long Name Offset Access Mode Description Addr. Read Write PRSTAT2 Peripheral Reset Status 0024 U, PV Page 11-138 Register 2 PRSET2 Peripheral Reset Set 0028 Page 11-140 Register 2 PRCLR2...
Page 537 XMC4500 XMC4000 Family System Control Unit (SCU) Table 11-11 Registers Overview (cont’d) Short Name Register Long Name Offset Access Mode Description Addr. Read Write OSCHPCTRL OSC_HP Control 0104 U, PV Page 11-157 Register CLKCALCONST Clock Calibration 010C U, PV Page 11-158 Constant Register PLLSTAT System PLL Status...
Page 538 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description MOD_REV [7:0] Module Revision Indicates the revision number of the implementation. This information depends on the design step. MOD_TYPE [15:8] Module Type This internal marker is fixed to C0 MOD_NUMBER [31:16] r Module Number Indicates the module identification number...
Page 539 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description DEPT [4:0] Department Identification Number DEPT indicates department within Infineon Technologies. MANUF [15:5] Manufacturer Identification Number JEDEC normalized Manufacturer code. MANUF = stands for Infineon Technologies. [31:16] r Reserved STCON Startup configuration register determining boot process of the chip.
Page 540 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description SWCON [11:8] SW Configuration Bit[9:8] is copy of Bit[1:0] after PORESET 0000 Normal mode, boot from Boot ROM 0001 ASC BSL enabled 0010 BMI customized boot enabled 0011 CAN BSL enabled 0100 Boot from Code SRAM 1000...
Page 541 XMC4500 XMC4000 Family System Control Unit (SCU) ETH0_CON Ethernet 0 Port Control Register (50004040 Reset Value: 0000 0000 INFS MDIO CLK_TX RXER CRS_DV CLK_RMII RXD3 RXD2 RXD1 RXD0 Field Bits Type Description RXD0 [1:0] MAC Receive Input 0 This bit field indicates the receive input position of the RXD0 signal.
Page 542 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description RXD3 [7:6] MAC Receive Input 3 This bit field indicates the receive input position of the RXD3 signal. Data input RXD3A is selected Data input RXD3B is selected Data input RXD3C is selected Data input RXD3D is selected CLK_RMII [9:8]...
Page 543 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description [17:16] rw COL input This bit field indicates the receive input position of the COL clock input signal. Data input COLA is selected Data input COLB is selected Data input COLC is selected Data input COLD is selected CLK_TX [19:18] rw...
Page 544 XMC4500 XMC4000 Family System Control Unit (SCU) CCUCON CCU Control Register (004C Reset Value: 0000 0000 Field Bits Type Description GSC40 Global Start Control CCU40 Disable Enable GSC41 Global Start Control CCU41 Disable Enable GSC42 Global Start Control CCU42 Disable Enable GSC43 Global Start Control CCU43...
Page 545 XMC4500 XMC4000 Family System Control Unit (SCU) SRSTAT Service request status reflecting masking with SRMSK mask register. Write one to a bit in SRCLR register to clear a bit or SRSET to set a bit. Writing zero has no effect. Outputs of this register are used to trigger interrupts or service requests.
Page 546 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OSCSICTRL OSCSICTRL Mirror Register Update Status Not updated Update completed OSCULCTRL OSCULCTRL Mirror Register Update Status Not updated Update completed RTC_CTR RTC CTR Mirror Register Update Status Not updated Update completed RTC_ATIM0 RTC ATIM0 Mirror Register Update Status...
Page 547 XMC4500 XMC4000 Family System Control Unit (SCU) SRRAW SCU Raw Service Request Status (0078 Reset Value: 0000 0000 _TIM _TIM _ATI _ATI SICT Field Bits Type Description PRWARN WDT pre-warning Interrupt Status Before Masking Inactive Active RTC Raw Periodic Interrupt Status Before Masking Set whenever periodic counter increments RTC Raw Alarm Interrupt Status Before Masking...
Page 548 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OSCSICTRL OSCSICTRL Mirror Register Update Status Before Masking Not updated Update completed OSCULCTRL OSCULCTRL Mirror Register Update Status Before Masking Not updated Update completed RTC_CTR RTC CTR Mirror Register Update Status Before Masking Not updated Update completed...
Page 549 XMC4500 XMC4000 Family System Control Unit (SCU) SRMSK Service request mask used to mask outputs of SRRAW register outputs connected to SRSTAT register. SRMSK SCU Service Request Mask (007C Reset Value: 0000 0000 _TIM _TIM _ATI _ATI SICT Field Bits Type Description PRWARN WDT pre-warning Interrupt Mask...
Page 550 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description HDCR HDCR Mirror Register Update Mask Disabled Enabled OSCSICTRL OSCSICTRL Mirror Register Update Mask Disabled Enabled OSCULCTRL OSCULCTRL Mirror Register Update Mask Disabled Enabled RTC_CTR RTC CTR Mirror Register Update Mask Disabled Enabled RTC_ATIM0...
Page 551 XMC4500 XMC4000 Family System Control Unit (SCU) SRCLR SCU Service Request Clear (0080 Reset Value: 0000 0000 _TIM _TIM _ATI _ATI SICT Field Bits Type Description PRWARN WDT pre-warning Interrupt Clear No effect Clear the status bit RTC Periodic Interrupt Clear No effect Clear the status bit RTC Alarm Interrupt Clear...
Page 552 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OSCULCTRL OSCULCTRL Mirror Register Update Clear No effect Clear the status bit RTC_CTR RTC CTR Mirror Register Update Clear No effect Clear the status bit RTC_ATIM0 RTC ATIM0 Mirror Register Update Clear No effect Clear the status bit RTC_ATIM1...
Page 553 XMC4500 XMC4000 Family System Control Unit (SCU) SRSET SCU Service Request Set (0084 Reset Value: 0000 0000 _TIM _TIM _ATI _ATI SICT Field Bits Type Description PRWARN WDT pre-warning Interrupt Set No effect set the status bit RTC Periodic Interrupt Set No effect set the status bit RTC Alarm Interrupt Set...
Page 554 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OSCULCTRL OSCULCTRL Mirror Register Update Set No effect set the status bit RTC_CTR RTC CTR Mirror Register Update Set No effect set the status bit RTC_ATIM0 RTC ATIM0 Mirror Register Update Set No effect set the status bit RTC_ATIM1...
Page 555 XMC4500 XMC4000 Family System Control Unit (SCU) NMIREQEN SCU Service Request Mask (0088 Reset Value: 0000 0000 Field Bits Type Description PRWARN Promote Pre-Warning Interrupt Request to NMI Request Disabled Enabled Promote RTC Periodic Interrupt request to NMI Request Disabled Enabled Promote RTC Alarm Interrupt Request to NMI Request...
Page 556 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description ERU03 Promote Channel 3 Interrupt of ERU0 Request to NMI Request Disabled Enabled [15:3], Reserved [31:20] DTSCON Die temperature sensor control register DTSCON Die Temperature Sensor Control Register (008C Reset Value: 0000 0001 BGTRIM REFTRIM...
Page 557 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OFFSET [10:4] Offset Calibration Value This bit field interfaces the offset calibration values to the DTS. The calibration values are forwarded to the DTS by setting bit START. GAIN [16:11] rw Gain Calibration Value This bit field interfaces the gain calibration values to...
Page 558 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description RESULT [9:0] Result of the DTS Measurement This bit field shows the result of the DTS measurement. The value given is directly related to the die temperature. Sensor Ready Status This bit indicate the DTS is ready or not.
Page 559 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description TAPDEL [7:4] Number of Delay Elements Select number of delay elements of (TAPDEL+1), [3:1], Reserved [31:8] Read as 0; should be written with 0. G0ORCEN Enable register for out-of-range comparators of group 0 of analog input channels. G0ORCEN Out of Range Comparator Enable Register 0 (00A0 Reset Value: 0000 0000...
Page 560 XMC4500 XMC4000 Family System Control Unit (SCU) G1ORCEN Out of Range Comparator Enable Register 1 (00A4 Reset Value: 0000 0000 Field Bits Type Description ENORC6 Enable Out of Range Comparator, Channel 6 Each bit (when set) enables the out of range comparator of the associated channel Disabled Enabled...
Page 561 XMC4500 XMC4000 Family System Control Unit (SCU) MIRRSTS Mirror Write Status Register (00C4 Reset Value: 0000 0000 _TIM _TIM _ATI _ATI SICT Field Bits Type Function HDCLR HDCLR Mirror Register Write Status Ready Busy HDSET HDSET Mirror Register Write Status Ready Busy HDCR...
Page 562 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Function RTC_TIM0 RTC TIM0 Mirror Register Write Status Ready Busy RTC_TIM1 RTC TIM1 Mirror Register Write Status Ready Busy Retention Memory Access Register Update Status This fields indicates status of retention memory update from RMDATA register to Hibernate domain...
Page 563 XMC4500 XMC4000 Family System Control Unit (SCU) RMACR Retention Memory Access Control Register (00C8 Reset Value: 0000 0000 ADDR Field Bits Type Function RDWR Hibernate Retention Memory Register Update Control This field controls access to Retention Memory using address selected in ADDR slice transfer data from Retention Memory in Hibernate domain to RMDATA...
Page 564 XMC4500 XMC4000 Family System Control Unit (SCU) RMDATA Retention Memory Access Data Register (00CC Reset Value: 0000 0000 DATA DATA Field Bits Type Function DATA [31:0] Hibernate Retention Memory Data This field data of selected of Retention Memory using address. The address of 0-15 is selected with RMACR register.
Page 565 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PEENPS Parity Error Enable for PSRAM Disabled Enabled PEENDS1 Parity Error Enable for DSRAM1 Disabled Enabled PEENDS2 Parity Error Enable for DSRAM2 Disabled Enabled PEENU0 Parity Error Enable for USIC0 Memory Disabled Enabled PEENU1...
Page 566 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PEENSD1 Parity Error Enable for SDMMC Memory 1 Disabled Enabled [7:3], Reserved Should be written with 0. [15:14], [31:21] MCHKCON The following register enables the functional parity check mechanism for testing purpose.
Page 567 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description USIC0DRA Select Memory Check for USIC0 Not selected Selected USIC1DRA Select Memory Check for USIC1 Not selected Selected USIC2DRA Select Memory Check for USIC2 Not selected Selected MCANDRA Select Memory Check for MultiCAN Not selected Selected PPRFDRA...
Page 568 XMC4500 XMC4000 Family System Control Unit (SCU) PETE The following register enables the functional parity error trap generation mechanism. TRAPRAW The trap flag gets reflected in register and needs to be enabled with TRAPDIS register before can be effectively used to generate an NMI. The same tap flag PERSTEN can be configured with register to generate System Reset instead of an NMI.
Page 569 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PETEU2 Parity Error Trap Enable for USIC2 Memory Disabled Enabled PETEMC Parity Error Trap Enable for MultiCAN Memory Disabled Enabled PETEPPRF Parity Error Trap Enable for PMU Prefetch Memory Disabled Enabled PETEUSB...
Page 570 XMC4500 XMC4000 Family System Control Unit (SCU) PERSTEN Parity Error Reset Enable Register (0148 Reset Value: 0000 0000 Field Bits Type Description RSEN System Reset Enable upon Parity Error Trap Reset request disabled Reset request enabled [31:1] Reserved Should be written with 0. PEFLAG The PEFLAG register controls the functional parity check mechanism.
Page 571 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PEFPS Parity Error Flag for PSRAM No parity error detected Parity error detected PEFDS1 Parity Error Flag for DSRAM1 No parity error detected Parity error detected PEFDS2 Parity Error Flag for DSRAM2 No parity error detected Parity error detected PEFU0...
Page 572 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PESD1 Parity Error Flag for SDMMC Memory 1 No parity error detected Parity error detected [7:3], Reserved Should be written with 0. [15:14], [31:21] PMTPR The following register provides direct access to parity bits of a selected module. The width and therefore the valid bits in register PMTPR is listed in...
Page 573 XMC4500 XMC4000 Family System Control Unit (SCU) PMTPR Parity Memory Test Pattern Register (0154 Reset Value: 0000 0000 Field Bits Type Description [15:8] Parity Read Values for Memory Test For each byte of a memory module the parity bits generated during the most recent read access are indicated here.
Page 574 XMC4500 XMC4000 Family System Control Unit (SCU) PMTSR Parity Memory Test Select Register (0158 Reset Value: 0000 0000 Field Bits Type Description MTENPS Test Enable Control for PSRAM Standard operation Parity bits under test MTENDS1 Test Enable Control for DSRAM1 Standard operation Parity bits under test MTENDS2...
Page 575 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description MTEPPRF Test Enable Control for PMU Prefetch Memory Standard operation Parity bits under test MTUSB Test Enable Control for USB Memory Standard operation Parity bits under test MTETH0TX Test Enable Control for ETH TX Memory Standard operation Parity bits under test MTETH0RX...
Page 576 XMC4500 XMC4000 Family System Control Unit (SCU) TRAPSTAT Trap Status Register (0160 Reset Value: 0000 0000 Field Bits Type Description SOSCWDGT OSC_HP Oscillator Watchdog Trap Status No pending trap request Pending trap request SVCOLCKT System VCO Lock Trap Status No pending trap request Pending trap request UVCOLCKT USB VCO Lock Trap Status...
Page 577 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description BWERR1T Peripheral Bridge 1 Trap Status This trap flags error responses for buffered write operations on the Peripheral Bridge 1 No pending trap request Pending trap request Reserved [11:9], Read as 0;...
Page 578 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description SVCOLCKT System VCO Lock Trap Raw Status No pending trap request Pending trap request UVCOLCKT USB VCO Lock Trap Raw Status No pending trap request Pending trap request Parity Error Trap Raw Status No pending trap request Pending trap request BRWNT...
Page 579 XMC4500 XMC4000 Family System Control Unit (SCU) TRAPDIS Trap Disable Register (0168 Reset Value: 0000 01FF Field Bits Type Description SOSCWDGT OSC_HP Oscillator Watchdog Trap Disable Trap request enabled Trap request disabled SVCOLCKT System VCO Lock Trap Disable Trap request enabled Trap request disabled UVCOLCKT USB VCO Lock Trap Disable...
Page 580 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description Reserved [13:12], Read as 0; should be written with 0. [11:9], 15,14, [31:17] TRAPCLR This register contains the software clear control for the trap status flags in register TRAPRAW TRAPSTAT TRAPCLR Trap Clear Register...
Page 581 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description BRWNT Brown Out Trap Clear No effect Clear trap request ULPWDGT OSC_ULP Oscillator Watchdog Trap Clear No effect Clear trap request BWERR0T Peripheral Bridge 0 Trap Clear No effect Clear trap request BWERR1T Peripheral Bridge 1 Trap Clear...
Page 582 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description SOSCWDGT OSC_HP Oscillator Watchdog Trap Set No effect Set trap request SVCOLCKT System VCO Lock Trap Set No effect Set trap request UVCOLCKT USB VCO Lock Trap Set No effect Set trap request Parity Error Trap Set No effect...
Page 583: Pcu Registers
XMC4500 XMC4000 Family System Control Unit (SCU) PWRSTAT PCU Status Register (0200 Reset Value: 0000 0000 HIBE Field Bits Type Description HIBEN Hibernate Domain Enable Status Inactive Active USBPHYPDQ USB PHY Transceiver State Power-down Active USBOTGEN USB On-The-Go Comparators State Power-down Active USBPUWQ...
Page 584 XMC4500 XMC4000 Family System Control Unit (SCU) PWRSTAT PCU Status Register (0200 Reset Value: 0000 0000 HIBE Field Bits Type Description HIBEN Hibernate Domain Enable Status Inactive Active USBPHYPDQ USB PHY Transceiver State Power-down Active USBOTGEN USB On-The-Go Comparators State Power-down Active USBPUWQ...
Page 585 XMC4500 XMC4000 Family System Control Unit (SCU) PWRSET PCU Set Control Register (0204 Reset Value: 0000 0000 Field Bits Type Description Set Hibernate Domain Enable No effect Enable Hibernate domain USBPHYPDQ Set USB PHY Transceiver Disable No effect Active USBOTGEN Set USB On-The-Go Comparators Enable No effect Active...
Page 586 XMC4500 XMC4000 Family System Control Unit (SCU) PWRCLR PCU Clear Control Register (0208 Reset Value: 0000 0000 Field Bits Type Description Clear Disable Hibernate Domain No effect Disable Hibernate domain USBPHYPDQ Clear USB PHY Transceiver Disable No effect Power-down USBOTGEN Clear USB On-The-Go Comparators Enable No effect Power-down...
Page 587 XMC4500 XMC4000 Family System Control Unit (SCU) EVRSTAT EVR Status Register (0210 Reset Value: 0000 0000 Field Bits Type Description OV13 Regulator Overvoltage for 1.3 V No overvoltage condition Regulator is in overvoltage Reserved [31:2] EVRVADCSTAT Supply voltage monitor register. The actual voltage represented by the VADC13V and VADC33V can be calculated according to the formulas: VADC13V = ( / LSB13V) +1...
Page 588 XMC4500 XMC4000 Family System Control Unit (SCU) EVRVADCSTAT EVR VADC Status Register (0214 Reset Value: 0000 0000 VADC33V VADC13V Field Bits Type Description VADC13V [7:0] VADC 1.3 V Conversion Result This bit field contains the last conversion result of the VADC for the EVR13.
Page 589: Hcu Registers
XMC4500 XMC4000 Family System Control Unit (SCU) PWRMON Power Monitor Control (022C Reset Value: 0000 0000 INTV THRS Field Bits Type Description THRS [7:0] Threshold Threshold value for comparison to for brown- out detection INTV [15:8] Interval Interval value for comparison to expressed in cycles of system clock Enable...
Page 590 XMC4500 XMC4000 Family System Control Unit (SCU) HDSTAT Hibernate Domain Status Register (0300 Reset Value: 0000 0000 HIBN Field Bits Type Description EPEV Wake-up Pin Event Positive Edge Wake-up on positive edge pin event inactive Wake-up on positive edge pin event active ENEV Wake-up Pin Event Negative Edge Wake-up on negative edge pin event inactive...
Page 591 XMC4500 XMC4000 Family System Control Unit (SCU) HDCLR Hibernate Domain Status Clear Register (0304 Reset Value: 0000 0000 Field Bits Type Description EPEV Wake-up Pin Event Positive Edge Clear No effect Clear wake-up event ENEV Wake-up Pin Event Negative Edge Clear No effect Clear wake-up event RTCEV...
Page 592 XMC4500 XMC4000 Family System Control Unit (SCU) HDSET Hibernate Domain Status Set Register (0308 Reset Value: 0000 0000 Field Bits Type Description EPEV Wake-up Pin Event Positive Edge Set No effect Set wake-up event ENEV Wake-up Pin Event Negative Edge Set No effect Set wake-up event RTCEV...
Page 593 XMC4500 XMC4000 Family System Control Unit (SCU) HDCR Hibernate Domain Control Register (030C Reset Value: 000C 2000 HIBIO1SEL HIBIO0SEL HIBI HIBI GPI0 Field Bits Type Description WKPEP Wake-Up on Pin Event Positive Edge Enable Wake-up event disabled Wake-up event enabled WKPEN Wake-up on Pin Event Negative Edge Enable Wake-up event disabled...
Page 594 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description WKUPSEL Wake-Up from Hibernate Trigger Input Selection HIB_IO_1 pin selected HIB_IO_0 pin selected GPI0SEL General Purpose Input 0 Selection This bit field selects input to ERU0 module that optionally can be used with software as a general purpose input.
Page 595 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description 5,9, Reserved Read as 0; should be written with 0. [15:14], [29:24], [31:30] OSCSICTRL Control register for clock source. A special mechanism keeps the the clock active if the external crystal oscillator is switched off, regardless of the value of the PWD bit field.
Page 596 XMC4500 XMC4000 Family System Control Unit (SCU) OSCULSTAT OSC_ULP Status Register (0318 Reset Value: 0000 0000 Field Bits Type Description XTAL1 Data Value This bit monitors the value (level) of pin XTAL1. If XTAL1 is not used as clock input it can be used as GPI pin.
Page 597: Rcu Registers
XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description X1DEN XTAL1 Data General Purpose Input Enable The GPI data can be monitored with X1D bit of OSCULSTAT register Data input inactivated, power down Data input active Note: It is strongly recommended to keep this function inactivated if the XTAL1 input is used as clock source MODE...
Page 598 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description RSTSTAT [7:0] Reset Status Information Provides reason of last reset 00000001 PORST reset 00000010 SWD reset 00000100 PV reset 00001000 CPU system reset 00010000 CPU lockup reset 00100000 WDT reset 01000000 Reserved 10000000...
Page 599 XMC4500 XMC4000 Family System Control Unit (SCU) RSTSET RCU Reset Set Register (0404 Reset Value: 0000 0000 HIBR Field Bits Type Description HIBWK Set Hibernate Wake-up Reset Status No effect Assert reset status bit HIBRS Set Hibernate Reset No effect Assert reset LCKEN Enable Lockup Reset...
Page 600 XMC4500 XMC4000 Family System Control Unit (SCU) RSTCLR RCU Reset Clear Register (0408 Reset Value: 0000 0000 HIBR Field Bits Type Description RSCLR Clear Reset Status No effect Clears field RSTSTAT.RSTSTAT HIBWK Clear Hibernate Wake-up Reset Status No effect De-assert reset status bit HIBRS Clear Hibernate Reset No effect...
Page 601 XMC4500 XMC4000 Family System Control Unit (SCU) PRSTAT0 RCU Peripheral 0 Reset Status (040C Reset Value: 0001 0F9F POSI POSI USIC Field Bits Type Description VADCRS VADC Reset Status Reset de-asserted Reset asserted DSDRS DSD Reset Status Reset de-asserted Reset asserted CCU40RS CCU40 Reset Status Reset de-asserted...
Page 602 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description POSIF1RS POSIF1 Reset Status Reset de-asserted Reset asserted USIC0RS USIC0 Reset Status Reset de-asserted Reset asserted ERU1RS ERU1 Reset Status Reset de-asserted Reset asserted [6:5], Reserved [15:12], [22:17], [31:24] PRSET0 Selective reset assert register for peripherals for Peripherals 0.
Page 603 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description VADCRS VADC Reset Assert No effect Assert reset DSDRS DSD Reset Assert No effect Assert reset CCU40RS CCU40 Reset Assert No effect Assert reset CCU41RS CCU41 Reset Assert No effect Assert reset CCU42RS CCU42 Reset Assert...
Page 604 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description [6:5], Reserved [15:12], [22:17], [31:24] PRCLR0 Selective reset de-assert register for peripherals for Peripherals 0. Write one to de-assert selected reset, writing zeros has no effect. PRCLR0 RCU Peripheral 0 Reset Clear (0414 Reset Value: 0000 0000 POSI...
Page 605 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description CCU42RS CCU42 Reset Clear No effect De-assert reset CCU80RS CCU80 Reset Clear No effect De-assert reset CCU81RS CCU81 Reset Clear No effect De-assert reset POSIF0RS POSIF0 Reset Clear No effect De-assert reset POSIF1RS POSIF1 Reset Clear...
Page 606 XMC4500 XMC4000 Family System Control Unit (SCU) PRSTAT1 RCU Peripheral 1 Reset Status (0418 Reset Value: 0000 01F9 USIC USIC Field Bits Type Description CCU43RS CCU43 Reset Status Reset de-asserted Reset asserted LEDTSCU0RS LEDTS Reset Status Reset de-asserted Reset asserted MCAN0RS MultiCAN Reset Status Reset de-asserted...
Page 607 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PPORTSRS PORTS Reset Status Reset de-asserted Reset asserted [2:1], Reserved [31:10] PRSET1 Selective reset assert register for peripherals for Peripherals 1. Write one to assert selected reset, writing zeros has no effect. PRSET1 RCU Peripheral 1 Reset Set (041C...
Page 608 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description MMCIRS MMC Interface Reset Assert No effect Assert reset USIC1RS USIC1 Reset Assert No effect Assert reset USIC2RS USIC2 Reset Assert No effect Assert reset PPORTSRS PORTS Reset Assert No effect Assert reset [2:1],...
Page 609 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description LEDTSCU0RS LEDTS Reset Clear No effect De-assert reset MCAN0RS MultiCAN Reset Clear No effect De-assert reset DACRS DAC Reset Clear No effect De-assert reset MMCIRS MMC Interface Reset Clear No effect De-assert reset USIC1RS...
Page 610 XMC4500 XMC4000 Family System Control Unit (SCU) PRSTAT2 RCU Peripheral 2 Reset Status (0424 Reset Value: 0000 00F6 Field Bits Type Description WDTRS WDT Reset Status Reset de-asserted Reset asserted ETH0RS ETH0 Reset Status Reset de-asserted Reset asserted DMA0RS DMA0 Reset Status Reset de-asserted Reset asserted DMA1RS...
Page 611 XMC4500 XMC4000 Family System Control Unit (SCU) PRSET2 Selective reset assert register for peripherals for Peripherals 2. Write one to assert selected reset, writing zeros has no effect. PRSET2 RCU Peripheral 2 Reset Set (0428 Reset Value: 0000 0000 Field Bits Type Description WDTRS...
Page 612 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description Reserved [9:8], [31:11] PRCLR2 Selective reset de-assert register for peripherals for Peripherals 2. Write one to de-assert selected reset, writing zeros has no effect. PRCLR2 RCU Peripheral 2 Reset Clear (042C Reset Value: 0000 0000 Field...
Page 613 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description FCERS FCE Reset Clear No effect De-assert reset USBRS USB Reset Clear No effect De-assert reset Reserved [9:8], [31:11] PRSTAT3 Selective reset status register for peripherals for Peripherals 3. Note: Reset release must be effectively prevented for unless module clock is gated or off in cases where kernel clock and bus interface clocks are shared, in order to avoid system hang-ups.
Page 614 XMC4500 XMC4000 Family System Control Unit (SCU) PRSET3 Selective reset assert register for peripherals for Peripherals 3. Write one to assert selected reset, writing zeros has no effect. PRSET3 RCU Peripheral 3 Reset Set (0434 Reset Value: 0000 0000 Field Bits Type Description EBURS...
Page 615: Ccu Registers
XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description EBURS EBU Reset Assert No effect De-assert reset [1:0], Reserved [31:3] 11.10.5 CCU Registers CLKSTAT Global clock status register. CLKSTAT Clock Status Register (0600 Reset Value: 0000 0000 Field Bits Type Description...
Page 616 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description EBUCST EBU Clock Status Clock disabled Clock enabled CCUCST CCU Clock Status Clock disabled Clock enabled WDTCST WDT Clock Status Clock disabled Note: WDT clock can be put on hold in debug mode when this behavior is enabled at the watchdog Clock enabled...
Page 617 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description MMCCEN MMC Clock Enable No effect Enable ETH0CEN Ethernet Clock Enable No effect Enable EBUCEN EBU Clock Enable No effect Enable CCUCEN CCU Clock Enable No effect Enable WDTCEN WDT Clock Enable No effect Enable...
Page 618 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description USBCDI USB Clock Disable No effect Disable clock MMCCDI MMC Clock Disable No effect Disable clock ETH0CDI Ethernet Clock Disable No effect Disable clock EBUCDI EBU Clock Disable No effect Disable clock CCUCDI CCU Clock Disable...
Page 619 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Function SYSDIV [7:0] System Clock Division Value The value the divider operates is (SYSDIV+1). SYSSEL System Clock Selection Value clock clock [15:8], Reserved Read as 0; should be written with 0. [23:17], [31:25] CPUCLKCR...
Page 620 XMC4500 XMC4000 Family System Control Unit (SCU) PBCLKCR Peripheral clock control register. PBCLKCR Peripheral Bus Clock Control Register (0614 Reset Value: 0000 0000 PBDI Field Bits Type Function PBDIV PB Clock Divider Enable This bit enables division of clock to produce clock.
Page 621 XMC4500 XMC4000 Family System Control Unit (SCU) USBCLKCR USB Clock Control Register (0618 Reset Value: 0000 0000 USBDIV Field Bits Type Function USBDIV [2:0] USB Clock Divider Value PLL clock is divided by USBDIV + 1 Must only be programmed, when clock is not used USBSEL USB Clock Selection Value USB PLL Clock...
Page 622 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Function EBUDIV [5:0] EBU Clock Divider Value PLL clock is divided by EBUDIV + 1 Must only be programmed, when clock is not used [31:6] Reserved Read as 0; should be written with 0. CCUCLKCR CCUx clock control register.
Page 623 XMC4500 XMC4000 Family System Control Unit (SCU) WDTCLKCR WDT Clock Control Register (0624 Reset Value: 0000 0000 WDTSEL WDTDIV Field Bits Type Function WDTDIV [7:0] WDT Clock Divider Value WDT is divided by WDTDIV + 1 Must only be programmed, when clock is not used WDTSEL [17:16] rw WDT Clock Selection Value...
Page 624 XMC4500 XMC4000 Family System Control Unit (SCU) EXTCLKCR External Clock Control (0628 Reset Value: 0000 0000 ECKDIV ECKSEL Field Bits Type Description ECKSEL [1:0] External Clock Selection Value clock Reserved clock divided according to ECKDIV bit field configuration clock divided according to ECKDIV bit field configuration ECKDIV [24:16] rw...
Page 625 XMC4500 XMC4000 Family System Control Unit (SCU) SLEEPCR Sleep Control Register (0630 Reset Value: 0000 0000 Field Bits Type Description SYSSEL System Clock Selection Value clock clock USBCR USB Clock Control in Sleep Mode Disabled Enabled MMCCR MMC Clock Control in Sleep Mode Disabled Enabled ETH0CR...
Page 626 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description Reserved [15:2], Read as 0. [23:22], [31:25] DSLEEPCR Configuration register that defines some system behavior aspects while in Deep Sleep mode. The original system state gets restored upon wake-up from sleep mode except for PLL re-start if enabled before entering Deep Sleep mode and configured to go into power down while in Deep Sleep mode.
Page 627 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description USBCR USB Clock Control in Deep Sleep Mode Disabled Enabled MMCCR MMC Clock Control in Deep Sleep Mode Disabled Enabled ETH0CR Ethernet Clock Control in Deep Sleep Mode Disabled Enabled EBUCR EBU Clock Control in Deep Sleep Mode...
Page 628 XMC4500 XMC4000 Family System Control Unit (SCU) OSCHPSTAT OSC_HP Status Register (0700 Reset Value: 0000 0000 Field Bits Type Description XTAL1 Data Value This bit monitors the value (level) of pin XTAL1. If XTAL1 is not used as clock input it can be used as GPI pin.
Page 629 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description X1DEN XTAL1 Data Enable Bit X1D is not updated Bit X1D can be updated SHBY Shaper Bypass The shaper is not bypassed The shaper is bypassed MODE [5:4] Oscillator Mode External Crystal Mode and External Input Clock Mode.
Page 630 XMC4500 XMC4000 Family System Control Unit (SCU) CLKCALCONST Clock Calibration Constant Register (070C Reset Value: 0000 0000 CALIBCONST Field Bits Type Description CALIBCONST [3:0] Clock Calibration Constant Value This field contains clock calibration constant value for PLL configuration. [31:4] Reserved Read as 0;...
Page 631 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description VCOBYST VCO Bypass Status Free-running / Normal Mode is entered Prescaler Mode is entered PWDSTAT PLL Power-saving Mode Status PLL Power-saving Mode was not entered PLL Power-saving Mode was entered VCOLOCK PLL LOCK Status PLL not locked...
Page 632 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description PLLHV Oscillator for PLL Valid High Status Bit This bit indicates if the frequency output of OSC is usable for the VCO part of the PLL. This is checked by the Oscillator Watchdog of the PLL.
Page 633 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description VCOBYP VCO Bypass Normal operation, VCO is not bypassed Prescaler Mode, VCO is bypassed VCOPWD VCO Power Saving Mode Normal behavior The VCO is put into a Power Saving Mode and can no longer be used.
Page 634 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OSCRES Oscillator Watchdog Reset osc_fail_res_i This bit controls signal at the PLL module. The Oscillator Watchdog of the PLL is not reset and remains active The Oscillator Watchdog of the PLL is reset RESLD Restart VCO Lock Detection Setting this bit will clear bit PLLSTAT.VCOLOCK...
Page 635 XMC4500 XMC4000 Family System Control Unit (SCU) PLLCON1 PLL Configuration 1 Register (0718 Reset Value: 0000 0000 PDIV K2DIV NDIV K1DIV Field Bits Type Description K1DIV [6:0] K1-Divider Value The value the K1-Divider operates is K1DIV+1. NDIV [14:8] N-Divider Value The value the N-Divider operates is NDIV+1.
Page 636 XMC4500 XMC4000 Family System Control Unit (SCU) PLLCON2 PLL Configuration 2 Register (071C Reset Value: 0000 0001 K1IN PINS Field Bits Type Description PINSEL P-Divider Input Selection PLL external oscillator selected Backup clock selected K1INSEL K1-Divider Input Selection PLL external oscillator selected Backup clock selected Reserved...
Page 637 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description VCOBYST VCO Bypass Status Normal Mode is entered Prescaler Mode is entered PWDSTAT PLL Power-saving Mode Status PLL Power-saving Mode was not entered PLL Power-saving Mode was entered VCOLOCK PLL VCO Lock Status The frequency difference of greater than allowed.
Page 638 XMC4500 XMC4000 Family System Control Unit (SCU) USBPLLCON USB PLL Configuration Register (0724 Reset Value: 0001 0003 PDIV FIND NDIV DISC Field Bits Type Description VCOBYP VCO Bypass Normal operation, VCO is not bypassed Prescaler Mode, VCO is bypassed VCOPWD VCO Power Saving Mode Normal behavior The VCO is put into a Power Saving Mode...
Page 639 XMC4500 XMC4000 Family System Control Unit (SCU) Field Bits Type Description OSCDISCDIS Oscillator Disconnect Disable This bit is used to disable the control FINDIS in a PLL loss-of-lock case. In case of a PLL loss-of-lock bit FINDIS is set In case of a PLL loss-of-lock bit FINDIS is cleared NDIV [14:8]...
Page 640 XMC4500 XMC4000 Family System Control Unit (SCU) CLKMXSTAT Clock Multiplexing Status Register (0738 Reset Value: 0000 0000 SYSCLKM Field Bits Type Description SYSCLKMUX [1:0] Status of System Clock Multiplexing Upon Source Switching Clock sources that are indicated active are still contributing in glitch-free switching clock active clock active...
Page 641 XMC4500 XMC4000 Family Communication Peripherals Communication Peripherals Reference Manual V1.6, 2016-07 Subject to Agreement on the Use of Product Information...
Page 642: Led And Touch-Sense (Ledts)
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) LED and Touch-Sense (LEDTS) The LED and Touch-Sense (LEDTS) drives LEDs and controls touch pads used as human-machine interface (HMI) in an application. Table 12-1 Abbreviations in chapter Abbreviation Meaning LEDTS LED and Touch-sense time slice duration time frame duration time period duration...
Page 643: Block Diagram
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) • Only one pad can be measured at any time; selection of active pad controllable by software or hardware round-robin • Flexible measurement time on touch pads • Pin oscillation control circuit with adjustments for oscillation •...
Page 644 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Column Control TS Control prescaler LEDTS counter reload value LEDTS _clk Accumulation Oscillator Counter Select Loop CLK_PS 3bit 8bit NR_LEDCOL 0: no clock pad osc 1: clk/1 Internal Compare Oscillation enable Registers Pad Control Pulse 65535 : clk/65535 COLLEV...
Page 645: Functional Overview
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) 12.2 Functional Overview The same pin can support LED & touch-sense functions in a time-multiplexed manner. LED mode or touch-sense mode can be enabled by hardware for respective function controls. Time-division multiplexing is done by dividing the time domain into time slots. This basic time slot is called a time slice .
Page 646 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) oscillation counting to be flexible. This is also how the relative brightness of the LEDs can be controlled. In case of touch pads, the activation time is called the oscillation window. Figure 12-2 shows an example for a LED matrix configuration with touch pads.
Page 647 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Autoscan Time Period Frame 0 Frame 1 Frame 2 Frame 3 time frame time frame interrupt interrupt autoscan time period interrupt C2 C1 TS C3 C1 C0 C3 C2 C0 TS C2 C1 ledts _fn COLA pad _turn_0...
Page 648: Led Drive Mode
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) 12.3 LED Drive Mode LED driving is supported mainly for LED column selection and line control. At one time, only one column is active. The corresponding line level at high or low determines if the associated LED on column is lit or not.
Page 649 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) A time slice interrupt can be enabled. A new time slice starts on the overflow of the 8LSBs of the LEDTS-counter. Figure 12-4 shows the LED function control circuit. This circuit also provides the control for enabling the pad oscillator.
Page 650: Led Pin Assignment And Current Capability
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) No. time slice per time frame No. LE D Column & & LD_E N + 1 Touch-sens e & & TS _E N NR_LE DCOL : LE DTS counter res et/ reload value (in c ase of TS _E N = 0) CLK_PS LEDTS-Counter LEDTS_clk...
Page 651: Touch-Sense Mode
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) 12.4 Touch-Sense Mode Figure 12-5 shows the pin oscillation control unit, which is integrated with the standard PORTS pad. The active pad turn (pad_turn_x) for a touch input line is defined as the time duration within the touch-sense time slice (COL A) where the TS-counter is counting oscillations on the TSIN[x] pin.
Page 652 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) auto scan period extended frame 3 2 1 0 TS 3 2 1 0 TS ....
Page 653 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) internal pull-up enable over-rule can be optionally de-activated (correspondingly internal pull-down disable over-rule is also de-activated; PORTS pin SFR setting for pull applies instead), such as when the user system utilize external resistor for pull-up instead. In the whole duration of the touch-sense time slice, COLA is activated high.
Page 654: Finger Sensing
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) The oscillation is enabled on the pin with valid turn for a configurable duration. A compare value provides the means to adjust the duty cycle within the time slice. The pin oscillation is enabled (TS-counter is counting) only on compare match until the end of the time slice.
Page 655: Operating Both Led Drive And Touch-Sense Modes
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) 12.5 Operating both LED Drive and Touch-Sense Modes It is possible to enable both LED driving and touch-sense functions in a single time frame. If both functions are enabled, up to 7 time slices are configurable for the LED function, and the last time slice is reserved for touch-sensing function.
Page 656: Debug Behavior
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Table 12-4 LEDTS Events’ Interrupt Node Control Event Interrupt Node Interrupt Node Flag Node ID Enable Bit Start of Time Slice LEDTS0.SR0 LEDTS0.SR0 Start of (Extended) Time Frame Start of Autoscan Time Period 12.7 Debug Behavior The LEDTS timers/counters LEDTS-counter and TS-counter can be enabled (together)
Page 657: Interpretation Of Bit Field Fncol
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Enable LED Function Only To enable LED function only: set LD_EN, clear TS_EN. Initialization after reset: GLOBCTL = 0bXXXXXXXX XXXXXXXX XXX00000 0000XX10; //set LD_EN and start LEDTS-counter on prescaled clock //CLK_PS != 0) Re-configuration during run-time: GLOBCTL &= 0x0000X00X;//stop LEDTS-counter by clearing prescaler...
Page 658: Ledts Timing Calculations
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) current time slice and prepare the necessary values (to be shadow-transferred) valid for the next time slice. Referring to the example below, when the FNCOL bit field is 111 , it can be derived that the touch-sensing function/column was active in the previous time slice and therefore the current active column is LED COL[4].
Page 659: Time-Multiplexed Led And Touch-Sense Functions On Pin
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) LED drive active duration: × ÷ (12.6) LED Drive Active Duration TSD Compare_VALUE 2 Touch-sense drive active duration: × ÷ (12.7) Touch-sense Drive Active Duration – Compare_VALUE 12.9.4 Time-Multiplexed LED and Touch-Sense Functions on Pin Some hints are provided regarding the time-multiplexed usage of a pin for LED and touch-sense function: •...
Page 660 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Table 12-6 LEDTS Pin Control Signals Function ld/ts_en ledts_fn Pin Control of Assigned Pin LD_EN 0 = LED Enable COL[x]; PORTS SFR setting column Passive level on COL[the rest]. If TS_EN = 1, COLA = 0.
Page 661: Software Hints
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) HWS E L HW S elec t (Touch -sense time slice active ) AND (Pad turn on pin ) Touch -sense disable pull over -rule Touch -sense pull -up enable , pull -down disable IOCR P ull Control Touch -sense open -drain enable...
Page 662: Hardware Design Hints
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) – enabling dummy LED columns (without assigning/setting the LED column pins) – selecting bigger pre-scale factor ( GLOBCTL .CLK_PS) – accumulating the number of pad oscillations ( FNCTL .ACCCNT) • Valid pad detection period can be reduced by: –...
Page 663: Registers
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) 12.10 Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 12-7 Registers Address Space Module Base Address End Address Note LEDTS0 4801 0000 4801 00FF The prefix “...
Page 664: Registers Description
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Table 12-8 Register Overview of LEDTS Short Name Description Offset Access Mode Description Addr. Read Write TSCMP1 Touch-Sense Compare 0028 U, PV U, PV Page 12-35 Register 1 Reserved Reserved 002C 1FFC 12.10.1 Registers Description The LEDTS SFRs are organized into registers for global initialization control, functional control comprising TS-counter value, line pattern and compare value registers.
Page 665 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description MOD_NUMBER [31:16] r Module Number Value This bit field defines the module identification number. GLOBCTL The GLOBCTL register is used to initialize the LEDTS global controls. GLOBCTL Global Control Register Reset Value: 0000 0000 CLK_PS ITP_...
Page 666 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description ENSYNC Enable Autoscan Time Period Synchronization No synchronization Synchronization enabled on Kernel0 autoscan time period SUSCFG Suspend Request Configuration Ignore suspend request Enable suspend according to request This bit is restored to default with Debug Reset. MASKVAL [11:9] Mask Number of LSB Bits for Event Validation...
Page 667 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description CLK_PS [31:16] LEDTS-Counter Clock Pre-Scale Factor The constant clock input is prescaled according to setting. No clock Divide by 1 65535 Divide by 65535 This bit can only be set to any other value (from 0) provided at least one of touch-sense or LED function is enabled.
Page 668 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description PADT [2:0] Touch-Sense TSIN Pad Turn This is the TSIN[x] pin that is next or currently active in pad turn. When PADTSW = 0, the value is updated by hardware at the end of touch-sense time slice. Software write is always possible.
Page 669 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description ACCCNT [19:16] Accumulate Count on Touch-Sense Input Defines the number of times a touch-sense input/pin is enabled in touch-sense time slice of consecutive frames. This provides to accumulate oscillation count on the TSIN[x].
Page 670 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description COLLEV Active Level of LED Column Active low Active high NR_LEDCOL [31:29] Number of LED Columns Defines the number of LED columns. 1 LED column 2 LED columns 3 LED columns 4 LED columns 5 LED columns 6 LED columns...
Page 671 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) EVFR Event Flag Register Reset Value: 0000 0000 TPF TFF TSF Field Bits Type Description Time Slice Interrupt Flag Set on activation of each new time slice, including when bit CLK_PS is set from 0. To be cleared by software.
Page 672 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description CTFF Clear (Extended) Time Frame Interrupt Flag No action. Bit TFF is cleared. Read always as 0. CTPF Clear Autoscan Time Period Interrupt Flag No action. Bit TPF is cleared. Read always as 0.
Page 673 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description TSCTRVAL [31:16] TS-Counter Value This is the actual TS-counter value. It can only be written when no pad turn is active. The counter may be enabled for automatic reset once per (extended) frame on the start of a new pad turn on the next TSIN[x] pin.
Page 674 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) LINE1 Line Pattern Register 1 Reset Value: 0000 0000 LINE_A LINE_6 LINE_5 LINE_4 Field Bits Type Description LINE_4, [7:0], Output on LINE[x] LINE_5, [15:8], This value is output on LINE[x] to pin when LED LINE_6 [23:16] COL[x] is active.
Page 675 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Field Bits Type Description CMP_LD0, [7:0], Compare Value for LED COL[x] CMP_LD1, [15:8], CMP_LD2, [23:16], CMP_LD3 [31:24] LDCMP1 LED Compare Register 1 Reset Value: 0000 0000 CMP_LDA_TSCOM CMP_LD6 CMP_LD5 CMP_LD4 Field Bits Type Description CMP_LD4, [7:0], Compare Value for LED COL[x]...
Page 676 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) TSCMP0 Touch-sense Compare Register 0 Reset Value: 0000 0000 CMP_TS3 CMP_TS2 CMP_TS1 CMP_TS0 Field Bits Type Description CMP_TS0, [7:0], Compare Value for Touch-Sense TSIN[x] CMP_TS1, [15:8], CMP_TS2, [23:16], CMP_TS3 [31:24] TSCMP1 Touch-sense Compare Register 1 Reset Value: 0000 0000 CMP_TS7 CMP_TS6...
Page 677: Interconnects
XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) 12.11 Interconnects The LEDTS has interconnection to other peripherals enabling higher level of automation without requiring software. Table 12-9 provides a list of the pin connections. LEDTSx.FN is an output signal denoting LEDTS active function. This signal can be used as a source for VADC request gating and background gating.
Page 678 XMC4500 XMC4000 Family LED and Touch-Sense (LEDTS) Table 12-9 Pin Connection (cont’d) Input/Output Connected To Description LEDTS0.COL2 P0.0 LEDTS Column 2 output P2.7 LEDTS0.COL3 P0.1 LEDTS Column 3 output P2.6 LEDTS0.EXTENDED0 O P2.2.HW0 LEDTS0.EXTENDED1 O P2.3.HW0 LEDTS0.EXTENDED2 O P2.4.HW0 LEDTS0.EXTENDED3 O P2.5.HW0 LEDTS0.EXTENDED4 O P2.8.HW0...
Page 679: Sd/Mmc Interface (Sdmmc)
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SD/MMC Interface (SDMMC) This chapter describes the SD/MMC module. The XMC4500 uses the following SD and MMC card standard specification. For more detailed information on how to operate the SDMMC interface, please refer to the SD and MMC specification referenced below. References [10] SD Specifications Part A2, SD Host Controller Standard Specification, Version 2.00, February 2007...
Page 680: Block Diagram
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) • System Interface – Data transfer using Programmed IO mode on AHB Slave interface • SD/SDIO/MMC Card Interface – Transfers data in 1 bit and 4 bit SD modes – Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity –...
Page 681 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Monitor Power Management Synchronizer Command Control Unit SD2.0/ SDIO2.0/ SD Protocol unit MMC4.4 Device Data Interface Control Unit Data Registers FIFO Interrupts Clock Control Figure 13-1 SDMMC Block Diagram Reference Manual 13-3 V1.6, 2016-07 SDMMC, V1.8 Subject to Agreement on the Use of Product Information...
Page 682: Functional Description
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.2 Functional Description This section describes the functional blocks of the SDMMC. AHB Interface Host AHB interface acts as a bridge between AHB and the host controller. The SDMMC host controller provides Programmed IO method in which the ARM Host Driver transfers data using the Buffer Data Port Register SDMMC_DATA_BUFFER .
Page 683 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Power Control The SDMMC host controller controls the SD Bus Power depending on the value SDMMC_POWER_CTRL programmed in the Power Control Register by the CPU. The system has the responsibility to supply SD Bus Voltage according to card OCR and supply voltage capabilities depending on the host controller.
Page 684: Card Detection
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.3 Card Detection When card insertion or removal in the slot is detected, the status will be sent to the CPU via interrupt methodology. The active low card signal SDCD_n is set to 0 during card detection.
Page 685: Read/ Write Operation
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.5 Read/ Write Operation The controller will be configued to work with buffer data port registers SDMMC_DATA_BUFFER without internal DMA. The CPU will act as a master and start writing / reading data via SDMMC_DATA_BUFFER 13.5.1 Write Operation...
Page 686 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Asynchronous Abort In an Asynchronous Abort sequence, the host driver can issue an Abort Command at anytime unless Command Inhibit (CMD) in the Present State Register is set to 1. SDMMC_PRESENT_STATE .COMMAND_INHIBIT_CMD = 1. Synchronous Abort In a Synchronous Abort, the host driver shall issue an Abort command after the data transfer stopped by using Stop At Block Gap Request in the Block Gap Control register.
Page 687: Special Command Types
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.6 Special Command Types There are three types of special commands. Suspend, Resume and Abort. These bits shall be set to 00 for all other commands. Suspend Command Suspend command can be selected by setting SDMMC_COMMAND .CMD_TYPE = If the Suspend command succeeds, the host controller shall assume the SD Bus has...
Page 688: Reference Manual
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.7 Error Detection This section describes data errors or defects detection methods. Cyclic Redundancy Check (CRC) The CRC7 and CRC16 generators calculate the CRC for Command and Data respectively to send the CRC to the SD/SDIO/MMC card. The CRC7 and CRC16 checker checks for any CRC error in the Response and Data sent by the SD/SDIO/MMC card.
Page 689 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) • A hardware reset to the card triggered by the MMC.RST pin. • A software reset occurs. A reset pulse is generated when writing 1 to each bit of the Software Reset Register SDMMC_SW_RESET Clocks The clocks connected to SDMMC include: •...
Page 690: Initialisation And System Dependencies
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.11 Initialisation and System Dependencies This section provides information on how to initialise and use the SDMMC. 13.11.1 Setup SDMMC Data Transfer Figure 13-2 shows the flowchart of SDMMC read/ write data transfer. Start 1.
Page 691 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) The following describes how to setup read/ write data transfer: 1. Set Block Size Register. Set executed data byte length of one block. SDMMC_BLOCK_SIZE.TX_BLOCK_SIZE 2. Set Block Count Register. Set executed data block count. SDMMC_BLOCK_COUNT.BLOCK_COUNT 3.
Page 692: Read Operation
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.11.2 Read Operation The following shows the configurations for SDMMC read operation: 10-R. Wait for Buffer Read Ready Interrupt SDMMC_INT_STATUS_NORM.BUFF_READ_READY 11-R. Clear Buffer Read Ready status Write SDMMC_INT_STATUS_NORM.BUFF_READ_READY = 1 to clear bit 12-R. Read Block Data (in accordance with the number of bytes specified in step (1)) SDMMC_DATA_BUFFER 13-R.
Page 693: Abort Transaction
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.11.4 Abort Transaction This section describes the sequence for the abort transaction. Asynchronous Abort The following shows the asynchronous abort sequence: 1. Check SDMMC_PRESENT_STATE.COMMAND_INHIBIT_CMD is not set to 1. 2. Issue Abort Command. SDMMC_COMMAND .CMD_TYPE = 11 Synchronous Abort The following shows the synchronous abort sequence:...
Page 694: Registers
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.12 Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 13-2 Registers Address Space Module Base Address End Address Note SDMMC 4801 C000 4801 FFFF Table 13-3 Register Overview Short Name...
Page 695 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-3 Register Overview (cont’d) Short Name Description Offset Access Mode Descripti Addr. on See Read Write SDMMC_RESP Response 4 Register 0018 U, PV U, PV Page 13-2 ONSE4 SDMMC_RESP Response 6 Register 001C U, PV U, PV Page 13-2...
Page 696 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-3 Register Overview (cont’d) Short Name Description Offset Access Mode Descripti Addr. on See Read Write SDMMC_EN_IN Error Interrupt Status Enable 0036 U, PV U, PV Page 13-6 T_STATUS_ER Register SDMMC_EN_IN Normal Interrupt Signal 0038 U, PV U, PV...
Page 697 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-3 Register Overview (cont’d) Short Name Description Offset Access Mode Descripti Addr. on See Read Write Reserved Reserved 0075 00FA Slot Interrupt Status Register SDMMC_SLOT_ Slot Interrupt Status Register 00FC U, PV U, PV Page 13-8 INT_STATUS Reserved...
Page 698: Registers Description
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.12.1 Registers Description SDMMC_BLOCK_SIZE This register is used to configure the block size for data transfer. SDMMC_BLOCK_SIZE Block Size Register (0004 Reset Value: 0000 TX_BLOCK_SIZE SIZE Field Bits Type Description TX_BLOCK Transfer Block Size [11:0] _SIZE This register specifies the block size for block data...
Page 699 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_BLOCK_COUNT This register is used to configure the block count for current transfer. SDMMC_BLOCK_COUNT Block Count Register (0006 Reset Value: 0000 BLOCK_COUNT Field Bits Type Description BLOCK_COUNT [15:0] Blocks Count for Current Transfer This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers.
Page 700 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_ARGUMENT1 This register is used to configure the SD command argument. SDMMC_ARGUMENT1 Argument1 Register (0008 Reset Value: 00000000 ARGUMENT1 ARGUMENT1 Field Bits Type Description ARGUMENT1 [31:0] Command Argument The SD Command Argument is specified as bit 39-8 of Command-Format.
Page 701 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_TRANSFER_MODE This register is used to configure the data transfer mode. SDMMC_TRANSFER_MODE Transfer Mode Register (000C Reset Value: 0000 TI_B DIR_ ACMD_EN Field Bits Type Description Reserved Read as 0; must be written with 0. BLOCK_COUNT Block Count Enable This bit is used to enable the Block count register,...
Page 702 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description ACMD_EN [3:2] Auto CMD Enable This field determines use of auto command functions Auto Command Disabled Auto CMD12 Enable Note: Other values are reserved To stop Multiple-block read and write operation: •...
Page 703 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Determination of transfer type Table 13-4 Determination of transfer type Multi / Single Block Block Count Block Count Function Select Enable Don’t Care Don’t Care Single Transfer Don’t Care Infinite Transfer Not Zero Multiple Transfer Zero Stop Multiple Transfer Reference Manual...
Page 704 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_COMMAND This register is used to configure the SDMMC command. SDMMC_COMMAND Command Register (000E Reset Value: 0000 _IND RESP_TY CMD_TYP CMD_IND PE_SELE Field Bits Type Description RESP_TYPE_SELECT [1:0] Response Type Select No Response Response length 136 Response length 48 Response length 48 check Busy after response...
Page 705 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CMD_IND_CHECK_EN Command Index Check Enable If this bit is set to 1, the host controller shall check the index field in the response to see if it has the same value as the command index.
Page 706 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description [15:14] r Reserved Read as 0; should be written with 0. Reference Manual 13-28 V1.6, 2016-07 SDMMC, V1.8 Subject to Agreement on the Use of Product Information...
Page 707 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_RESPONSE This register is used to configure the command response. Table 13-5 shows the relation between parameters and the name of response type. Table 13-5 Relation between parameters and the name of response type Response Type Index Check CRC Check...
Page 708 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-6 Response bit definition for each response type (cont’d) Kind of Response Meaning of Response Response Response Field Register R5, R5b SDIO Response R[39:8] RESPONSE 0[31:0] R6 (Published RCA New published RCA[31:16] R[39:8] RESPONSE response) etc.
Page 709 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_RESPONSE2 Response 2 Register (0014 Reset Value: 00000000 RESPONSE3 RESPONSE2 Field Bits Type Description RESPONSE2 [15:0] Response2 This bit is initialized to 0 at reset. RESPONSE3 [31:16] Response3 This bit is initialized to 0 at reset. SDMMC_RESPONSE4 Response 4 Register (0018...
Page 710 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_RESPONSE6 Response 6 Register (001C Reset Value: 00000000 RESPONSE7 RESPONSE6 Field Bits Type Description RESPONSE6 [15:0] Response6 This bit is initialized to 0 at reset. RESPONSE7 [31:16] Response7 This bit is initialized to 0 at reset. Reference Manual 13-32 V1.6, 2016-07...
Page 711 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_DATA_BUFFER This register is used to configure the SDMMC host controller data buffer. SDMMC_DATA_BUFFER Data Buffer Register (0020 Reset Value: 00000000 DATA_BUFFER DATA_BUFFER Field Bits Type Description DATA_BUFFER [31:0] Data Buffer The host controller buffer can be accessed through this 32-bit Data Port Register.
Page 712 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_PRESENT_STATE This register is used to check the present state of the SDMMC host controller. SDMMC_PRESENT_STATE Present State Register (0024 Reset Value: 00000000 _LIN D_IN DAT_7_4_PIN_LEVEL DAT_3_0_PIN_LEVEL T_PI PIN_ TE_T _LIN D_IN D_IN ITE_ HIBI HIBI CTIV...
Page 713 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description COMMAND_INHIBIT Command Inhibit (CMD) _CMD If this bit is 0, it indicates the CMD line is not in use and the host controller can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written.
Page 714 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description COMMAND_INHIBIT Command Inhibit (DAT) _DAT This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the host controller can issue the next SD command.
Page 715 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description WRITE_TRANSFER_ Write Transfer Active ACTIVE This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the host controller. This bit is set in either of the following cases: After the end bit of the write command.
Page 716 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description READ_TRANSFER_ Read Transfer Active ACTIVE This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer...
Page 717 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description BUFFER_READ_EN Buffer Read Enable ABLE This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer.
Page 718 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CARD_STATE_STAB Card State Stable This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit.
Page 719 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description DAT_7_4_PIN_LEVE [28:25] r Line Signal Level This status is used to check DAT line level to recover from errors, and for debugging. D28 - DAT[7] D27 - DAT[6] D26 - DAT[5] D25 - DAT[4] Reset: F [31:29] r...
Page 720 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 2. When writing to 1 to Continue Request in the Block Gap Control register to continue a write transfer. This bit shall be cleared in either of the following cases: 1. When the SD card releases write busy of the last data block. If SD card does not drive busy signal for 8 SD Clocks, the host controller shall consider the card drive "Not Busy".
Page 721 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_HOST_CTRL This register is used to configure the modes of the SDMMC host controller. SDMMC_HOST_CTRL Host Control Register (0028 Reset Value: 00 CARD_DE CARD_DE SD_8BIT_ HIGH_SPE DATA_TX LED_CTR T_SIGNAL TECT_TES MODE ED_EN _WIDTH _DETECT T_LEVEL Field Bits...
Page 722 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description [4:3] Reserved Read as 0; must be written with 0. SD_8BIT_MODE Extended Data Transfer Width This bit controls 8-bit bus width mode for embedded device. If a device supports 8-bit bus mode, this bit may be set to 1.
Page 723 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_POWER_CTRL This register is used to configure the SD bus power. SDMMC_POWER_CTRL Power Control Register (0029 Reset Value: 00 HARDWA SD_BUS_ RE_RESE SD_BUS_VOLTAGE_SEL POWER Field Bits Type Description SD_BUS_POWER SD Bus Power Before setting this bit, the SD host driver shall set SD Bus Voltage Select.
Page 724 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_BLOCK_GAP_CTRL This register is used to configure the block gap request. SDMMC_BLOCK_GAP_CTRL Block Gap Control Register (002A Reset Value: 00 INT_AT_B STOP_AT READ_WA CONTINU LOCK_GA _BLOCK_ IT_CTRL E_REQ Field Bits Type Description STOP_AT_BLOCK Stop At Block Gap Request _GAP This bit is used to stop executing a transaction at the next block gap for non- DMA transfers.
Page 725 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CONTINUE_REQ Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0 and set this bit to restart the transfer.
Page 726 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description INT_AT_BLOCK_ Interrupt At Block Gap This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer.
Page 727 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_WAKEUP_CTRL Wakeup functionality depends on the host controller system hardware and software. The host driver shall maintain voltage on the SD Bus, by setting SD Bus power to 1 in the Power Control register, when wakeup event via card interrupt is desired. SDMMC_WAKEUP_CTRL Wake-up Control Register (002B...
Page 728 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_CLOCK_CTRL This register is used to configure the SD Clock. SDMMC_CLOCK_CTRL Clock Control Register (002C Reset Value: 0000 INTE INTE SDCLK_FREQ_SEL Field Bits Type Description INTERNAL_CLOCK Internal Clock Enable This bit is set to 0 when the host driver is not using the host controller or the host controller awaits a wakeup event.
Page 729 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description SDCLOCK_EN SD Clock Enable The host controller shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then, the host controller shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0).
Page 730 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description SDCLK_FREQ_SEL [15:8] rw SDCLK Frequency Select This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; this register holds the divisor of the Base Clock Frequency for SD clock. Only the following settings are allowed.
Page 731 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_TIMEOUT_CTRL This register is used to configure the interval for data timeout. SDMMC_TIMEOUT_CTRL Timeout Control Register (002E Reset Value: 00 DAT_TIMEOUT_CNT_VAL Field Bits Type Description DAT_TIMEOUT [3:0] Data Timeout Counter Value _CNT_VAL This value determines the interval by which DAT line time-outs are detected.
Page 732 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_SW_RESET A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the host controller shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0. SDMMC_SW_RESET Software Reset Register (002F...
Page 733 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description SW_RST_DAT Software Reset for DAT Line _LINE Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register Buffer is cleared and Initialized. Present State register Buffer read Enable Buffer write Enable...
Page 734 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_INT_STATUS_NORM The Normal Interrupt Status Enable affects read of this register, but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1. For all bits except Card Interrupt and Error Interrupt, writing 1 to a bit clears it.
Page 735 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description TX_COMPLETE Transfer Complete This bit is set when a read / write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated.
Page 736 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description BLOCK_GAP_EV Block Gap Event If the Stop At Block Gap Request in the Block Gap Control Register is set, this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus timing.
Page 737 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CARD_INS Card Insertion This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the host driver writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.
Page 738 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CARD_INT Card Interrupt Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the host controller shall detect the Card Interrupt without SD Clock to support wakeup.
Page 739: Table 13-8
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-7 Relation between transfer complete and data timeout error Transfer Data Timeout Error Meaning of the Status Complete Interrupted by Another Factor. Timeout occur during transfer. Don’t Care Data Transfer Complete Table 13-8 Relation between command complete and command timeout error Command Command Timeout...
Page 740 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_INT_STATUS_ERR Status defined in this register can be enabled by the Error Interrupt Status Enable Register, but not by the Error Interrupt Signal Enable Register. The Interrupt is generated when the Error Interrupt Signal Enable is enabled and at least one of the statuses is set to 1.
Page 741 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CMD_CRC_ERR Command CRC Error Command CRC Error is generated in two cases. If a response is returned and the Command Time-out Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response The host controller detects a CMD line conflict by monitoring the CMD line when a command is...
Page 742 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description DATA_TIMEOUT Data Timeout Error _ERR Occurs when detecting one of following timeout conditions. Busy Timeout for R1b, R5b type. Busy Timeout after Write CRC status Write CRC status Timeout Read Data Timeout No Error Timeout This bit can be cleared by a software write of 1 to...
Page 743 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CURRENT_LIMIT Current Limit Error _ERR By setting the SD Bus Power bit in the Power Control Register, the host controller is requested to supply power for the SD Bus. If the host controller supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit...
Page 744: Table 13-9
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description CEATA_ERR Ceata Error Status Occurs when ATA command termination has occured due to an error condition the device has encountered. no error error This bit can be cleared by a software write of 1 to the bit.
Page 745 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_EN_INT_STATUS_NORM Interrupt status can be enabled by writing 1 to the bit in this register. The host controller may sample the card Interrupt signal during interrupt period and may hold its value in the flip-flop.
Page 746 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description BUFF_WRITE_READ Buffer Write Ready Status Enable Y_EN Masked Enabled This bit can be set and cleared only by software. BUFF_READ_READY Buffer Read Ready Status Enable Masked Enabled This bit can be set and cleared only by software.
Page 747 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_EN_INT_STATUS_ERR Interrupt status can be enabled by writing 1 to the bit in this register. To Detect CMD Line conflict, the host driver must set both Command Time-out Error Status Enable and Command CRC Error Status Enable to 1. SDMMC_EN_INT_STATUS_ERR Error Interrupt Status Enable Register(0036 Reset Value: 0000...
Page 748 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description DATA_CRC_ERR Data CRC Error Status Enable Masked Enabled This bit can be set and cleared only by software. DATA_END_BIT_ Data End Bit Error Status Enable ERR_EN Masked Enabled This bit can be set and cleared only by software. CURRENT_LIMIT Current Limit Error Status Enable _ERR_EN...
Page 749 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_EN_INT_SIGNAL_NORM This register is used to select which interrupt status is indicated to the Host System as the Interrupt. The interrupt line is shared by all the status bits. Interrupt generation can be enabled by writing 1 to any of these bits. SDMMC_EN_INT_SIGNAL_NORM Normal Interrupt Signal Enable Register(0038 Reset Value: 0000...
Page 750 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description BUFF_READ_READY Buffer Read Ready Signal Enable Masked Enabled This bit can be set and cleared only by software. CARD_INS_EN Card Insertion Signal Enable Masked Enabled This bit can be set and cleared only by software.
Page 751 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_EN_INT_SIGNAL_ERR This register is used to select which interrupt status is notified to the Host System as the Interrupt. The interrupt line is shared by all the status bits. Interrupt generation can be enabled by writing 1 to any of these bits. SDMMC_EN_INT_SIGNAL_ERR Error Interrupt Signal Enable Register(003A Reset Value: 0000...
Page 752 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description DATA_CRC_ERR Data CRC Error Signal Enable Masked Enabled This bit can be set and cleared only by software. DATA_END_BIT_ Data End Bit Error Signal Enable ERR_EN Masked Enabled This bit can be set and cleared only by software. CURRENT_LIMIT Current Limit Error Signal Enable _ERR_EN...
Page 753 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_ACMD_ERR_STATUS This register is used to indicate CMD12 response error of Auto CMD12. The Host driver can determine what kind of Auto CMD12 errors occur by this register. This register is valid only when the Auto CMD Error is set. SDMMC_ACMD_ERR_STATUS Auto CMD Error Status Register (003C...
Page 754 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description ACMD_CRC_ERR Auto CMD CRC Error Occurs when detecting a CRC error in the command response. No Error CRC Error Generated This bit is initialized to 0 at reset. ACMD_END_BIT_ERR 3 Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0.
Page 755 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-10 Relation between Auto CMD12 CRC error and Auto CMD12 timeout error Auto Cmd12 CRC Error Auto CMD12 Timeout Error Kinds of Error No Error Response Timeout Error Response CRC Error CMD Line Conflict The timing of changing Auto CMD12 Error Status can be classified in three scenarios: 1.
Page 756 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_CAPABILITIES This register provides the host controller implementation information. SDMMC_CAPABILITIES Capabilities Register (0040 Reset Value: 01A030B0 NC_I DIA_ MAX_BLO SLOT_TY _64_ CK_LENG _1_8 _3_3 TIME BASE_SD_CLOCK_FREQ TIMEOUT_CLOCK_FREQ _UNI Field Bits Type Description TIMEOUT_CLOCK_ [5:0] Timeout Clock Frequency FREQ Base clock frequency used to detect Data...
Page 757 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description MAX_BLOCK_LEN [17:16] r Max Block Length Maximum block size that the host driver can read and write to the buffer in the host controller. The buffer shall transfer this block size without wait cycles.
Page 758 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_CAPABILITIES_HI This register provides the host controller implementation information. SDMMC_CAPABILITIES_HI Capabilities Register High (0044 Reset Value: 03000000 CLK_MULT 104_ RE_TUNIN 50_S 50_S TIM_CNT_RETUNE G_MODES Field Bits Type Description SDR50_SUPPORT SDR50 Support SDR50 is not supported SDR104_SUPPORT SDR104 Support SDR104 is not supported...
Page 759 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description Reserved Read as 0. USE_TUNING_SDR50 13 Use Tuning for SDR50 Tuning is not required. SDR50 does not require tuning RE_TUNING_MODES [15:14] r Re-tuning modes Retuning if not used. Mode 1 CLK_MULT [23:16] r Clock Multiplier...
Page 760 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_MAX_CURRENT_CAP This register indicates the maximum current capability for the supported voltage. SDMMC_MAX_CURRENT_CAP Maximum Current Capabilities Register(0048 Reset Value: 00000001 MAX_CURRENT_FOR_3_3V Field Bits Type Description MAX_CURRENT [7:0] Maximum Current for 3.3V _FOR_3_3V [31:8] Reserved Read as 0.
Page 761 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_FORCE_EVENT_ACMD_ERR_STATUS The Force Event Register is an address at which the Auto CMD12 Error Status Register can be written. Writing 1 : set each bit of the Auto CMD12 Error Status Register Writing 0 : no effect. SDMMC_FORCE_EVENT_ACMD_ERR_STATUS Force Event Register for Auto CMD Error Status(0050 Reset Value: 0000...
Page 762 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description FE_CMD_NOT_ISSUE Force Event for CMD not issued by Auto D_ACMD12_ERR CMD12 Error No interrupt Interrupt is generated [15:8] Reserved Read as 0; should be written with 0. Reference Manual 13-84 V1.6, 2016-07 SDMMC, V1.8 Subject to Agreement on the Use of Product Information...
Page 763 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_FORCE_EVENT_ERR_STATUS The Force Event Register is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set.
Page 764 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Field Bits Type Description FE_DATA_END_BIT_ Force Event for Data End Bit Error No interrupt Interrupt is generated FE_CURRENT_LIMIT Force Event for Current Limit Error _ERR No interrupt Interrupt is generated FE_ACMD12_ERR Force Event for Auto CMD Error No interrupt Interrupt is generated Reserved...
Page 765 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_DEBUG_SEL This register is used to select the debug mode. SDMMC_DEBUG_SEL Debug Selection Register (0074 Reset Value: 00000000 Field Bits Type Description DEBUG_SEL 0 Debug_sel receiver module and fifo_ctrl module signals are probed out cmd register, Interrupt status, transmitter module and clk sdcard signals are probed out.
Page 766 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) SDMMC_SLOT_INT_STATUS This register is used to configure the interrupt signal for card slot. SDMMC_SLOT_INT_STATUS Slot Interrupt Status Register (00FC Reset Value: 0000 SLOT_INT_STATUS Field Bits Type Description SLOT_INT_ [7:0] Interrupt Signal for Card Slot STATUS These status bit indicate the Interrupt signal and Wakeup signal for the card slot.
Page 767: Interconnects
XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) 13.13 Interconnects The interface signals of the SDMMC Host Controller are described below. Table 13-12 SDMMC Pin Connections Input/ Output Connected to Description clk_xin SCU.EXTCLK Input clock to SDMMC controller SDMMC.CLK_IN P3.6 Feedback clock of clk_sdcard_out from the pads SDMMC.DATA7_IN P1.13...
Page 768 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) Table 13-12 SDMMC Pin Connections (cont’d) Input/ Output Connected to Description SDMMC.CMD_OUT P3.5 SD1/SD4/MMC8 : Command Output SDMMC.BUS_POWER O P3.4 Control Card Power Supply SDMMC.LED P3.3 LED indication SDMMC.RST P0.11 Hardware reset to card SDMMC.SR0 NVIC Service request line...
Page 769 XMC4500 XMC4000 Family SD/MMC Interface (SDMMC) I/O Port SDMMC controller SDMMC.RST rst_n clk_sdcard_out SDMMC.CLK_OUT clk_sdcard_in OUT_EN DATA0 SDMMC.DATA0_OUT OUT_EN DATA1 SDMMC.DATA1_OUT OUT_EN DATA2 SDMMC.DATA2_OUT OUT_EN DATA3 SDMMC.DATA3_OUT OUT_EN DATA4 SDMMC.DATA4_OUT OUT_EN DATA5 SDMMC.DATA5_OUT OUT_EN DATA6 SDMMC.DATA6_OUT OUT_EN DATA7 SDMMC.DATA7_OUT OUT_EN SDMMC.CMD bus_pow SDMMC.BUS_POWER...
Page 770: External Bus Unit (Ebu)
XMC4500 XMC4000 Family External Bus Unit (EBU) External Bus Unit (EBU) The EBU controls the transactions between external memories or peripheral units, and the internal memories and peripheral units. Several external device configurations are supported with little or no additional circuitry, making the EBU a very powerful peripheral for expansion and support of several applications.
Page 771: Block Diagram
XMC4500 XMC4000 Family External Bus Unit (EBU) • External bus frequency: Module frequency: SDRAM clock = 1:1, 1:2, or 1:4. • Highly programmable access parameters. • Intel-style peripheral/device support. • Burst FLASH support (see Section 14.11 for specific device types). •...
Page 772: Interface Signals
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.2 Interface Signals The external EBU interface signals are listed in Table 14-2 below. Table 14-2 EBU Interface Signals Signal/Pin Type Function AD[31:0] Multiplexed Address/Data bus lines 0-31 A[23:16] Address bus lines 16-23 CS[3:0] Chip select 0-3 Read control line...
Page 773 XMC4500 XMC4000 Family External Bus Unit (EBU) The EBU adjusts the data on the data bus to the width of the external device, according to the programmed parameters in its control registers. The byte control signals BC[3:0] specify which parts of the data bus carry valid data. Address Bus, A[23:16] The total address bus of the EBU consists of 24 address output lines, giving a directly addressable range of up to 64 Mbyte (2...
Page 774 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-3 Byte Control Pin Usage Width of External Device 32-bit device D[31:24] D[23:16] D[15:8] D[7:0] with byte write capability 16-bit device inactive inactive D[15:8] D[7:0] with byte write capability (high) (high) 8-bit device inactive inactive inactive...
Page 775: Allocation Of Unused Signals As Gpio
XMC4500 XMC4000 Family External Bus Unit (EBU) SDRAM Clock Output/Input SDCLKO/SDCLKI The EBU provides a clock output for SDRAM devices on the SDCLKO pin. SDCLKO is, by default, a continuously running signal but can also be configured to switch off between accesses to conserve power.
Page 776 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-5 EBU Interface Signals Required by Operating Mode (cont’d) Signal/Pin When Needed by EBU A[23:16] These address bits can be individually enabled for use as GPIO by setting the relevant enable bit in the USERCON register. Setting MODCON.ARBMODE = 00 will also enable for GPIO.
Page 777: Signal States When Ebu Is Inactive
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-5 EBU Interface Signals Required by Operating Mode (cont’d) Signal/Pin When Needed by EBU AD[31:16] These signals are required by the EBU when the EBU is enabled and an enabled region is configured for accessing 32-bit memory or a non-muxed BC[3:2] memory type (MODCON.ARBMODE != 00...
Page 778 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-6 Memory Controller External Bus pin states during reset (cont’d) Pin Name State during State during Idle Reset and “No Bus” mode GPIO Driven to ‘1’ (High). SDCLKO GPIO Dependant on SDRAM clocking/power save mode SDCLKI GPIO High Impedance...
Page 779: Memory Controller Structure
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.3 Memory Controller Structure The AHBIF bridges translate AHB transactions into appropriate transaction requests which can be transferred to the arbiter (see Section 14.4 The arbiter looks at the transaction requests and schedules corresponding requests to the relevant state machine.
Page 780: Memory Controller Ahbif Bridge
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.4 Memory Controller AHBIF Bridge As shown in the Memory Controller Block Diagram ( Figure 14-3 ) Memory Controller contains an EBU specific AHBIF bridge. This bridge supports the AHB-lite protocol which means (among other things) that masters are not allowed to perform early burst termination (except after an error response) and that retries are not generated by slaves.
Page 781: Ahb Error Generation
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-7 Supported AHB Transactions (cont’d) AHB Transfer Type Support Transfer Comment Type Size Word Aligned to any word address single (32-bits) incr4 Yes (if address aligned, otherwise split)) incr8 Yes (if address aligned, otherwise split)) wrap8 others...
Page 782: Read Data Buffering
XMC4500 XMC4000 Family External Bus Unit (EBU) 1. Access to disabled region: If an access is attempted to a memory region which is disabled then an AHB Error Response is returned (i.e. the AHB access is terminated with an error). Note that the region can be disabled for reads and/or writes separately. 2.
Page 783 XMC4500 XMC4000 Family External Bus Unit (EBU) • Divide by 2: The EBU clock is running at half the frequency of the AHB bus clock. The EBU clock is edge aligned with the processor and AHB interface clock. The clock for the AHB interface of the memory controller must always be derived from the same synchronous source (the AHB bus clock).
Page 784: Clock Requirements
XMC4500 XMC4000 Family External Bus Unit (EBU) Memory Controller AHB Bridge Core Data AHB Data (32‐bit) AHB clock EBU clock domain domain Transaction AHB Address (28‐bit) EBU_CLK Pulse Swallowing Clock Divide Clock Control Figure 14-5 AHB/Memory Controller Clocking Domains (Simplified Block Diagram) 14.5.1.1 Clock Requirements The Memory Controller has the ability to clock SDRAM and other synchronous memory devices at the same frequency as the Memory Controller core logic.
Page 785: External Bus Operation
XMC4500 XMC4000 Family External Bus Unit (EBU) An access arriving on any of the Memory Controller, AHB interfaces will trigger an automatic exit from standby mode to service the access request. This condition may also prevent standby mode being entered at all depending upon when the new access arrives at the AHB interface.
Page 786 XMC4500 XMC4000 Family External Bus Unit (EBU) Each of the four user-programmable regions can be configured to respond to a particular address space through registers ADDRSELx. The default region is enable by bit ADDRSELx. REGENAB , the alternate region by ADDRSELx. ALTENAB .
Page 787: Chip Select Control
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.6.2 Chip Select Control The EBU generates four chip select signals, CSx, which are all available at dedicated chip select outputs. 14.6.3 Programmable Device Types Each CS region (0 to 3) can be individually configured using the BUSCONx.AGEN register field, to be connected to one of the following external memory/device types: Table 14-10 AGEN description AGEN value...
Page 788 XMC4500 XMC4000 Family External Bus Unit (EBU) Note: When using multiplexed devices a non-zero recovery phase is mandatory for all devices to prevent read data from one access conflicting with the address for the multiplexed memory. Table 14-11 Pins used to connect Multiplexed Devices to Memory Controller Memory Memory Controller Pins Section...
Page 789 XMC4500 XMC4000 Family External Bus Unit (EBU) interconnect between Memory Controller and a 16-bit Multiplexed device in this mode is shown below (note: for clarity only the address/data signals are shown):- Memory Controller Memory/Peripheral A(MAX:16) A(MAX:16) AD(15:0) AD(15:0) Figure 14-6 Connection of a 16-bit Multiplexed Device to Memory Controller Twin 16-bit Multiplexed Device Configuration This mode allows the use of two 16-bit multiplexed devices to create a 32-bit wide bus.
Page 790: Support For Non-Multiplexed Device Configurations
XMC4500 XMC4000 Family External Bus Unit (EBU) 32-bit Multiplexed Memory/Peripheral Configuration During the address phase the lower 16 bits of the 25 bit address are driven to EBU AD[15:0], the most significant 9 bits of the address are driven to pins AD(24:16) and pins AD(31:17) are driven with 0 (zero).
Page 791: Ahb Bus Width Translation
XMC4500 XMC4000 Family External Bus Unit (EBU) 1) Address will only be driven onto AD[15:0] during the address and address hold phases. AD[31:16] will be driven with address for duration of access 16-bit non-Multiplexed Memory/Peripheral Configuration Throughout the complete external bus cycle the address is driven onto EBU A[23:16] and AD[15:0].
Page 792: Address Alignment During Bus Accesses
XMC4500 XMC4000 Family External Bus Unit (EBU) memory controller External Data32(31:16) DataMS16(15:0) Address Data Bus Bus pins AD(31:16) A(15:0) AHB/memory controller Data32(31:0) Data32(31:16) Bus Interface memory controller External DataLS16(15:0) Data Bus Data Bus pins AD(15:0) AD(15:0) Data32(15:0) Figure 14-10 AHB to External Bus Data Re-Alignment •...
Page 793: External Bus Arbitration
The scheme provided by the EBU is compatible with other Infineon microcontroller devices and therefore allows the use of such devices as (external bus) masters together with the XMC4500.
Page 794 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-16 EBU External Bus Arbitration Signals Signal Direction Function HOLD HOLD is asserted (low) by an external bus master when the external bus master requests to obtain ownership of the external bus from the EBU. HLDA In/Out HLDA is asserted (low) by the Arbiter to signal that the external...
Page 795 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-17 External Bus Arbitration Programmable Parameters Parameter Function Description MODCON.ARBMODE Arbitration mode selection Section 14.7. MODCON.ARBSYNC Arbitration input signal sampling control MODCON.EXTLOCK External bus ownership locking control MODCON.TIMEOUTC External bus time-out control Reference Manual 14-26 V1.6, 2016-07...
Page 796: Arbitration Modes
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.7.3 Arbitration Modes The arbitration mode of the EBU can be selected through configuration pins during reset or by programming the MODCON.ARBMODE bit field (see Section 14.7.3 ) after reset. Four different modes are available: •...
Page 797 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-18 Function of Arbitration Pins in Arbiter Mode Type Pin Function in Arbiter Mode HOLD In Owner Mode (EBU is the owner of the external bus), a low level at HOLD indicates a request for bus ownership from the external master.
Page 798 XMC4500 XMC4000 Family External Bus Unit (EBU) 2. When the EBU is able to release bus ownership, it enters Hold Mode by tri-stating its bus interface lines and drives HLDA = 0 to indicate that it has released the bus. At this point, the external master ia allowed to drive the bus.
Page 799 XMC4500 XMC4000 Family External Bus Unit (EBU) Start EBU in Owner Mode (i.e. owner of the The EBU holds ownership of the external bus) external bus: While EXTLOCK = 1 Perform Appropriate LMB access Until all current/queued external External Bus Access to external bus accesses are completed.
Page 800: Participant Mode
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.7.3.4 Participant Mode The EBU tries to gain bus ownership only in case of pending transfers (e.g. when operating from internal memory and performing stores to external memory). While the EBU is not the owner of the external bus (default state), any AHB access to the external bus will be issued with a retry by the EBU.
Page 801 XMC4500 XMC4000 Family External Bus Unit (EBU) BREQ (EBU Output) ≥1 Cycle HLDA (EBU Input) ≥1 Cycle HOLD (EBU Input) ≥1 Cycle External Bus Ext. Master on Bus EBU on Bus Ext. Master on Bus Figure 14-14 Arbitration Sequence with the EBU in Participant Mode In Participant Mode, the arbitration sequence starts with the EBU in Hold Mode.
Page 802: Arbitration Input Signal Sampling
XMC4500 XMC4000 Family External Bus Unit (EBU) Start EBU is in Hold Mode The EBU remains in Hold Mode until an PLMB access to the external bus is received. This access is rejected with a retry and EBU access the EBU starts an arbitration cycle to ext.
Page 803: Locking The External Bus
XMC4500 XMC4000 Family External Bus Unit (EBU) When synchronous arbitration signal sampling is selected (ARBSYNC = 0), the arbitration input signals are sampled and evaluated in the same clock cycle. This mode provides the least overhead during arbitration (i.e. when changing bus ownership). The disadvantage is that the input signals must adhere to setup and hold times with respect to EBU_CLK to prevent the propagation of meta-stable signals in the EBU.
Page 804: Reaction To An Ahb Access To The External Bus
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.7.6 Reaction to an AHB Access to the External Bus The reaction of the memory controller to an external bus request from an AHB master is controlled as shown in Figure 14-16 LMB Master generates access to external bus Arbitration Mode = "No Bus"?
Page 805: Pending Access Time-Out
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.7.7 Pending Access Time-Out The strategy of stalling an AHB access (when the EBU is not the owner of the external bus) as described in the previous section may result in the occurrence of a time-out condition.
Page 806: Address Phase (Ap)
XMC4500 XMC4000 Family External Bus Unit (EBU) • Command Delay Phase CD (optional) • Command Phase CP (mandatory for read and write cycles of asynchronous device types) • Data Hold Phase DH (optional, only applies to write cycles) • Recovery Phase RP (optional) Throughout the remainder of this document, a short-hand notation is adopted to represent any clock cycle in any phase.
Page 807: Command Delay Phase (Cd)
XMC4500 XMC4000 Family External Bus Unit (EBU) • During a write access, the write data can be driven onto the multiplexed address/data 14.9.3 Command Delay Phase (CD) The Command Delay phase is optional. This means that it can also be programmed for a length of zero EBU_CLK clock cycles.
Page 808: Data Hold Phase (Dh)
XMC4500 XMC4000 Family External Bus Unit (EBU) • Latches the data from the data bus AD[15:0] (in the case of a read cycle), • Returns the appropriate BCx high (in the case where BCx is programmed to be asserted with the RD or RD/WR signals). 14.9.5 Data Hold Phase (DH) The Data Hold phase is optional.
Page 809: Recovery Phase (Rp)
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.9.7 Recovery Phase (RP) The Recovery Phase is optional (although for access types which would cause a bus contention a single cycle of recovery is normally forced by the memory controller logic). This means that it can also be programmed for a length of zero EBU_CLK clock cycles. This phase allows the insertion of a delay following an external bus access that delays the start of the Address Phase for the next external bus access.
Page 810: Asynchronous Read/Write Accesses
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-20 Parameters for Recovery Phase Case Parameter(s) used to calculate “Highest Wins” Recovery Phase Region Current Next Access Access Same CSn Read Read RDRECOVC Write Write WRRECOVC Read Write BUSRAPx.DTACS Write Read BUSWAPx.DTACS Different CSn Read Read...
Page 811: Signal List
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.10.1 Signal List The following signals of the EBU are used for asynchronous accesses: Table 14-21 Asynchronous Mode Signal List Signal/Pin Type Function AD[31:0] Address/Data bus lines 0-31 A[23:16] Address bus lines 16-23 CS[3:0] Chip select 0-3 Read control line...
Page 812: Standard Asynchronous Access Phases
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.10.2 Standard Asynchronous Access Phases Accesses to asynchronous devices are composed of a subset of the standard access phases which are detailed in Section 14.9 . The standard access phases for asynchronous devices are: •...
Page 813: Programmable Parameters
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.10.4 Programmable Parameters Table 14-23 lists the programmable parameters for asynchronous accesses. These parameters only apply to asynchronous devices when BUSCONx.AGEN = 000 . Note that emulation registers “EMU…” include parameters that control the emulator chip select region (CSEMU output), while “BUS…x”...
Page 814: Accesses To Multiplexed Devices
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.10.5 Accesses to Multiplexed Devices EBU_CLK CDi1 CPi1 CPi2 new AP1 Address data in AD(15:0) address A(MAX:16) (a) Read Access EBU_CLK CDi1 CPi1 CPi2 new AP1 address data out AD(15:0) address A(MAX:16) (b) Write Access Figure 14-17 Multiplexed External Bus Access Cycles Figure 14-17 shows an example of a read access to a multiplexed device.
Page 815: Dynamic Command Delay And Wait State Insertion
XMC4500 XMC4000 Family External Bus Unit (EBU) • Command Phase (compulsory) • Data Hold Phase (optional) • Recovery Phase (optional) 14.10.6 Dynamic Command Delay and Wait State Insertion In general, there are two critical phases during asynchronous device accesses. These phases are: Command Delay Phase (see Section 14.9.3...
Page 816 XMC4500 XMC4000 Family External Bus Unit (EBU) programmed to be at least two EBU_CLK cycles (via BUSAPx.WAITRDC or BUSAP.WAITWRC) in this mode. Figure 14-18 shows an example of the extension of the Command Phase through the WAIT input in synchronous mode: •...
Page 817: Interfacing To Nand Flash Devices
XMC4500 XMC4000 Family External Bus Unit (EBU) • At EBU_CLK edge 1 (at the end of the Address Phase), the EBU samples the WAIT input as low and starts the first cycle of the Command Phase (CPi1 - internally programmed). •...
Page 818 XMC4500 XMC4000 Family External Bus Unit (EBU) AD(15:0) I/O(15:0) A(17) A(16) WAIT Memory Memory Interface Interface NAND Flash Figure 14-20 Example of interfacing a Nand Flash device to the Memory Controller The R/B input from the NAND flash is connected to the memory controller WAIT input and is available as the MODCON.STS.
Page 819: Nand Flash
XMC4500 XMC4000 Family External Bus Unit (EBU) Note that the Memory Controller does not directly support byte wide devices. Writes to 8-bit, NAND Flash devices must therefore be done as 16-bit word writes with the valid byte in the lower part and the upper-byte padded. 14.10.7.1 NAND flash page mode NAND flash memories are page oriented devices capable of extended read operations with a single setup phase for command signals at the beginning of the access.
Page 820 XMC4500 XMC4000 Family External Bus Unit (EBU) INT_CLK CDi1 CPi1 CPi2 CDi1 CDi1 CPi1 CPi2 AD(15:0) data in data in ALE/CLE A(17:16) (a) Read Access INT_CLK CDi1 CPi1 CPi2 CPi1 CPi2 AD(15:0) data out data out RD/WR ALE/CLE A(17:16) (b) Write Access Figure 14-21 NAND Flash Page Mode Accesses Example Nand Flash Read Sequence Figure 14-22...
Page 821: Synchronous Read/Write Accesses
The Memory Controller is designed to generate waveforms compatible with the burst modes of: 1. INTEL and compatible burst flash devices 2. SPANSION and compatible burst flash devices 3. INFINEON and MICRON cellular RAM Reference Manual 14-52 V1.6, 2016-07 EBU, V1.6...
Page 822: Signals
XMC4500 XMC4000 Family External Bus Unit (EBU) 4. Fujitsu and Compatible FCRAM/uTRAM/CosmoRAM 5. Samsung OneNAND burst capable NAND flash and compatible devices 6. M-Systems DiskOnchipG3 and compatible devices 7. GSI SSRAM Features The Synchronous Access Controller is primarily designed to perform burst mode read cycles for an external instruction memory and read and write cycles for an external Cellular RAM or FCRAM data memory.
Page 823: Support For Four Burst Flash Device Types
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.11.2 Support for four Burst FLASH device types Support is provided for a maximum of four different Burst FLASH configurations on the external bus - i.e. one on each external chip select. Bit-fields BUSCONx.EBSE, BUSCONx.ECSE, BUSCONx.wait, BUSCONx.FBBMSEL, BUSCONx.BFCMSEL and BUSCONx.FETBLEN are used to configure specific characteristics for burst access cycles.
Page 824: Standard Access Phases
XMC4500 XMC4000 Family External Bus Unit (EBU) synchronous writes to the same device by programming BUSWP.EXTCLOCK to a different value. If a continuously running BFCLKO is required, then the BUSRCONx.BFCMSEL field can be used to enable an ungated flash clock. This bit is normally set to 1 in all the BUSRCONx registers after reset.
Page 825: Burst Length Control
XMC4500 XMC4000 Family External Bus Unit (EBU) • AP: Address Phase (compulsory - see Section 14.9.1 • AH: Address Hold Phase (optional see Section 14.9.2 • CD: Command Delay Phase (optional - see Section 14.9.3 • CP: Command Phase (compulsory - see Section 14.9.4 •...
Page 826: Burst Flash Clock Feedback
XMC4500 XMC4000 Family External Bus Unit (EBU) signals will be delayed by half of an EBU_CLK cycle from the start of the cycle in which they are asserted. Table 14-27 ADV and Chip Select Signal Timing EBU_CLK:BFCLKO Ratio Delay Disabled Delay Enabled Start of AP1 Middle of AP1...
Page 827: Asynchronous Address Phase
XMC4500 XMC4000 Family External Bus Unit (EBU) setting for operating frequency and latency for 1:1 clocking mode where the second resynchronisation stage offers no advantage. Note: If EBU_CLK:BFCLKO = 1:1, then the second and third resynchronisation stages have identical clock signals. There is therefore no advantage to having the second resynchronisation stage and it can be bypassed without loss of performance.
Page 828: Critical Word First Read Accesses
XMC4500 XMC4000 Family External Bus Unit (EBU) Note: The cache line fill will use an AHB, INCR8 (or WRAP8) transfer. This translates to a 16 word burst for a 16-bit device and is the largest AHB transfer supported by the memory controller as a single transfer on the external bus. The memory controller supports a 16 word burst using the continuous burst setting for FBBMSEL.
Page 829 XMC4500 XMC4000 Family External Bus Unit (EBU) EBU_CLK BFCLKO CDi1 CDi2 CPi1 CPi2 A(MAX:0) address AD(15:0) address data in (addr 0) data in (addr 2) data in (addr 4) data in (addr 6) (16 bit wide) Data Latched by Next Data Value Issued EBU on positive by FLASH in response to edge of EBU_CLK positive edge of BFCLKO Figure 14-24 Burst FLASH Read without Clock Feedback (burst length of 4) Notes 1.
Page 830: External Cycle Control Via The Wait Input
XMC4500 XMC4000 Family External Bus Unit (EBU) • Command Phase length = 2 EBU_CLK cycles (see WAITRDC and Section 14.9.4 • Burst Phase length = 2 EBU_CLK cycles (see EXTCLOCK, EXTDATA and Section 14.9.6 • Recovery Phase length = 2 EBU_CLK cycles (see Section 14.9.7 •...
Page 831: Flash Non-Array Access Support
XMC4500 XMC4000 Family External Bus Unit (EBU) only effect on operation is that the number of overrun cycles will increase as the decrementing of the sample counter will be lagged by the resynchronisation stages. During the initial phases of an access, WAIT is sampled on every edge of EBU_CLK. This is so the first burst phase is working with an accurate value for the WAIT signal.
Page 832: Burst Flash Device Programming Sequences
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.11.16 Burst Flash Device Programming Sequences Command sequences for some Burst Flash devices must not be interrupted by other read/write operations to the same device. If this applies to an attached device, the AHB bus master initiating the command sequence must ensure that no accesses are allowed from another AHB bus master until the command sequence has completed.
Page 833 XMC4500 XMC4000 Family External Bus Unit (EBU) Synchronous Write Access EBU_CLK BFCLKO BPi1 BPi2 A(MAX:16) ‐muxed address A(MAX:0) ‐ non‐muxed WAIT AD(15:0) data out data out data out data out address (addr 0) (addr 2) (addr 4) (addr 6) (16 bit) Data Latched by Cellular Next Data Value RAM in response to Issued on positive positive edge of BFCLKO edge of EBU_CLK Figure 14-26 Burst Cellular RAM Burst Write Access (burst length of 4) Notes 1.
Page 834: Programmable Parameters
WR signal to be active with the address and to be latched with the ADV signal. In this mode, FCRAM can be treated as an Infineon/Micron cellular RAM. Alternatively, if a write is attempted to a region configured as a burst flash, the memory controller will generate a burst write with the WR signal asserted with the write data.
Page 835 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-28 Burst Flash Access Programmable Parameters (cont’d) Parameter Function Register RDRECOVC Number of minimum recovery cycles after a read access BUSRAPx when the next access is to the same region. WRRECOVC Number of minimum recovery cycles after a write access BUSWAPx when the next access is to the same region.
Page 836: Sdram Interface
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.12 SDRAM Interface The SDRAM interface supports:- • 64 MBit (organized as 4 banks x 1M x 16) • 128 MBit (as 4 banks x 2M x16) • 256 MBit (as 4 banks x 4M x16) SDRAMs. •...
Page 837: External Interface
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-29 SDRAM Signal List (16-bit support) (cont’d) Signal Type Function Clock enable CS[3:0] Chip select SDCLK0 External SDRAM Clock. SDCLKI External SDRAM Clock Feedback Row Address Strobe for SDRAM accesses. Column Address Strobe for SDRAM accesses. DQM[1:0] Data Qualifiers (output on BC[1:0]) 14.12.3...
Page 838: Sdram Characteristics
XMC4500 XMC4000 Family External Bus Unit (EBU) Unless documented elsewhere, all outputs to the external bus are generated of the rising edge of EBU_CLK. The SDCLKO signal (in 1:1 mode) is antiphase to EBU_CLK. This means that the SDRAM memory device sees control signal changes occur on the negative clock edge.
Page 839: Supported Sdram Commands
XMC4500 XMC4000 Family External Bus Unit (EBU) accessing a location in a different row Memory Controller must issue a “precharge” command so that the local buffer is written back to the main SDRAM array. An SDRAM device provides a local buffer for each bank within the device, thus it is simultaneously possible for each of the banks to be “open”, this is termed “Multibanking”.
Page 840: Sdram Device Size
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-31 Supported SDRAM commands (cont’d) Table 14-43 Memory Controller pins Command Event [9:0] [1:0] Self refresh going into entry power down after precharge all is done Self refresh exit coming out of power down Mode register during...
Page 841 XMC4500 XMC4000 Family External Bus Unit (EBU) Note: This sequence will be referred to as a “cold start”, and is necessary when both the memory and the memory controller have just had power applied. Conversely a “warm start” will be required when the memory controller has just been powered up but data has been retained in the external memory by the use of self refresh mode.
Page 842 XMC4500 XMC4000 Family External Bus Unit (EBU) Figure 14-28 SDRAM Initialization The sequence is triggered by a write to the SDRAM mode register SDRMOD. A region having AGEN in BUSCONx set to 1000 will be configured with the mode from SDRMOD.
Page 843: Mobile Sdram Support
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-32 SDRAM Mode Register Setting Field Value Meaning SDRMOD Corresponding Position Address Pins Burst length Bursts of length 16 burstl [2:0] A[2:0] Bursts of length 8 Bursts of length 4 Bursts of length 2 Bursts of length 1 Burst type ‘0’...
Page 844: Burst Accesses
XMC4500 XMC4000 Family External Bus Unit (EBU) Mode Register write). In addition writes to the Extended Mode Register(s) will be triggered by writes to the SDRMOD register (i.e. whenever the “standard” Mode Register is written). The SDRMOD. XOPM bit-field is used to program the value that is to be written to the Extended Mode Register.
Page 845: Multibanking Operation
XMC4500 XMC4000 Family External Bus Unit (EBU) Figure 14-29 Short Burst Write Access through Data Masking The figure shows how a two beat burst write is translated to an eight beat burst write with data masking. During the first two data cycles (C5 and C6) the BC0 and BC1 outputs are driven low to cause the SDRAM device to write the required data.
Page 846: Bank Mask
XMC4500 XMC4000 Family External Bus Unit (EBU) 2. Last row address (up to 18 bits). These two items are referred to as a “bank tag”. In order to maintain these bank tags The Memory Controller must be made aware of:- •...
Page 847: Row Mask
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-33 BANKM selection BANKM AHB Address Bits used to Comment setting determine bank hit/miss none Reserved - do not use (default after reset). [21 to 20] Bank Size = 8MBit [22 to 21] Bank Size = 16MBit [23 to 22] Bank Size = 32MBit...
Page 848: Banks Precharge
XMC4500 XMC4000 Family External Bus Unit (EBU) It can be seen that the ROWM bit-field only has an effect on the low-end of the address range used to determine the row address (i.e. for use in comparison of the AHB address with the address stored in the bank tag).
Page 849: Refresh Cycles
XMC4500 XMC4000 Family External Bus Unit (EBU) 1. When the next access to a bank is to a different row to the previous access within the bank. 2. When an AHB request cannot be completed before the row active time is due, RAS max then the bank must explicitly be closed and opened again for the current request.
Page 850 XMC4500 XMC4000 Family External Bus Unit (EBU) Figure 14-30 SDRAM Refresh This sequence is periodically triggered by an internal refresh counter with programmable rate set using the ERFSHC and refreshc fields in the SDRMREF register. These fields are combined to create an eight bit value ( ERFSHC as MSBs).
Page 851: Self-Refresh Mode
XMC4500 XMC4000 Family External Bus Unit (EBU) set accordingly. This error flag can be cleared by writing to SDRMCON respective to the appropriate address region. 14.12.18 Self-Refresh Mode SDRAM devices provide a Self-Refresh Mode. In this mode the SDRAM automatically performs internal refresh sequences in response to an on-chip timer.
Page 852: Sdram Addressing Scheme
XMC4500 XMC4000 Family External Bus Unit (EBU) memory. This allows between 1 and 255 NOPs to be inserted before the device sees a non-null command. For predictable operation of the device during warm start, both the SDRMREF. ARFSH and SDRMREF. SELFREX_DLY fields should be set to 0.
Page 853 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-37 Row address generation for 16-bit SDRAM AWIDTH 16-bit, PORTW=01 Comment Address Generation (at Memory Controller pins) A[23:16] = ‘0’ Row size is 256 words. AD[31:16] = [24:9] A[23:16] = ‘0’ Row size is 512 words. AD[31:16] = [25:10] A[23:16] = ‘0’...
Page 854 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-38 Column Address Generation for 16-bit SDRAM AWIDTH 16-bit, PORTW=01 Address Generation (at Memory Controller pins) A[23:16] = ‘0’ A[15:11] = [24:20] A[10] = Command A[9:0] = [10:1] A[23:16] = ‘0’ A[15:11] = [25:21] A[10] = Command A[9:0] =...
Page 855 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-39 Bank Address to Memory Controller Address Pin Connection Number of Rows 2048 A[11] A[12] 4096 A[12] A[13] 8192 A[13] A[14] 16384 A[14] A[15] 1) For devices with four banks only. The following table shows all the multiplexing schemes discussed in the previous sections: Table 14-40 SDRAM Address Multiplexing Scheme Port Width...
Page 856 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-41 16-bit Burst Address Restrictions, A[0] = 0 Burst AHB Address A[4:1] SDRAM Burst Address Generation Length single access XXX0 0 -> 1 XX00 0 -> 1 -> 2 -> 3 X000 0 ->...
Page 857 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-43 Supported Configurations for 16-bit wide data bus (Part 1) SDRAM Memory Controller Pins portw = 01 (16-bit) A[15] A[14] A[13] A[12] A[11] A[10] A[9:0] 1GBit SDRAM Pins BA[1] BA[0] A[13] A[12] A[11] A[10] A[9:0]...
Page 858 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-44 Supported Configurations for 16-bit wide data bus (Part 2) SDRAM Multiplexed AWIDTH portw = 01 (16-bit) AHB Address setting 1GBit SDRAM Pins 64Mx16 A[26:11] A[26:25], A[10:1] 512MBit SDRAM Pins 32Mx16 A[25:11] A[25:23], A[10:1] 256MBit SDRAM Pins...
Page 859: Power Down Mode
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.12.20 Power Down Mode In order to reduce standby power consumption SDRAM devices provide a Power Down Mode. All banks can optionally be pre-charged before the device enters Power Down mode. Once Power Down mode is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off.
Page 860: Sdram Recovery Phases
XMC4500 XMC4000 Family External Bus Unit (EBU) An additional bit SDRMCON.CLKDIS is provided to allow the clock output to be completely disabled. The projected use for this bit is for DDR cold start where CKE should be high before the clock is enabled. Setting this bit will allow a self refresh exit to be performed to enable CKE without starting the clock.
Page 861 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-45 SDRAM Access Programmable Parameters (cont’d) Parameter Function Register rowm To select one pattern for row mask SDRMCON Number of NOP cycles between refresh commands. SDRMCON Crcd Number of NOP cycles between a row and column SDRMCON address awidth...
Page 862: Debug Behavior
XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-45 SDRAM Access Programmable Parameters (cont’d) Parameter Function Register WRDTACS recovery time after write command before accessing BUSWAP another region EXTCLOCK ratio between internal clock and external memory BUSRAP clock for SDRAM accesses (no effect for DDR. External clock always runs at internal clock frequency) 14.13...
Page 863: Power
XMC4500 XMC4000 Family External Bus Unit (EBU) until the EBU is explicitly programmed by the user. Therefore the default state of the PORTS logic is so that EBU hardware control is ignored. The assertion or deassertion of the EBU reset is controlled via the PRSET3.EBU and PRCLR3.EBU bit-fields, respectively (these fields are described on the SCU chapter).
Page 864: Registers
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.16 Registers This section describes the registers and programmable parameters of the EBU. All these registers can be read in User Mode, but can only be written in Supervisor Mode. All registers are reset by the module reset. Table 14-47 Registers Address Space Module Base Address...
Page 865 XMC4500 XMC4000 Family External Bus Unit (EBU) Table 14-48 Registers Overview EBU Control Registers (cont’d) Register Register Long Name Offset Access Mode Description Short Name Address Read Write BUSWAP1 EBU Bus Access 0044 U, PV, 32 PV, 32 Page 14-112 Parameter 1 BUSRCON2 EBU Bus Configuration 2 0048...
Page 866: General Control Registers
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.16.1 General Control Registers EBU basic enabling and setup is supported by the registers in this section. Use this register to enable/disable EBU and to configure various clock settings. Clock Control Register (000 Reset Value: 0011 0000 EBUDIVA DIV2...
Page 867 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description DIV2 DIV2 Clocking Mode standard clocking mode. clock input selected by SYNC bitfield (default after reset). request EBU to run off AHB bus clock divided by 2. EBUDIV [19:18] rw EBU Clock Divide Ratio request EBU to run off input clock (default after reset)
Page 868 XMC4500 XMC4000 Family External Bus Unit (EBU) MODCON Modes Configuration Register (004 Reset Value: 0000 0020 SINH GLOBALCS LOCKTIMEOUT SINH ARBMOD TIMEOUTC Field Bits Type Description Memory Status Bit Software access to the WAIT input pin to the EBU. LCKABRT Lock Abort Reserved, will read as 0 SDTRI...
Page 869 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description ARBMODE [7:6] Arbitration Mode Selection No Bus arbitration mode selected Arbiter Mode arbitration mode selected Participant arbitration mode selected Sole Master arbitration mode selected TIMEOUTC [15:8] Bus Time-out Control This bit field determines the number of inactive cycles leading to a bus time-out after the EBU gains ownership.
Page 870 XMC4500 XMC4000 Family External Bus Unit (EBU) Module Identification Register Reset Value: 0014 C0XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_NUMBER MOD_TYPE MOD_REV...
Page 871: Region Control Registers
XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description ADDIO [24:16] rw Address Pins to GPIO Mode Individual Control Bits for Address Bus Bits 24 down to 16 respectively. Address Bit is required for addressing memory Address Bit is available for GPIO function ADVIO ADV Pin to GPIO Mode Control Bit for the ADV/ALE output...
Page 872 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description ALTENAB Alternate Region Enable Memory region is disabled (default after reset). Memory region is enabled. WPROT Memory Region Write Protect Region is enabled for write accesses Region is write protected. [31:3] Reserved Read as 0;...
Page 873 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description FBBMSEL Synchronous burst buffer mode select Burst buffer length defined by value in FETBLEN (default after reset). Continuous mode. All data required for transaction is transferred in a single burst. BFSSS Read Single Stage Synchronization: The second read-data synchronization stage in the...
Page 874 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description Disable Burst Address Wrapping Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request.
Page 875 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description WAIT [25:24] rw External Wait Control Function of the WAIT input. This is specific to the device type (i.e. the AGEN field). Details for Asynchronous (ASYNC) Devices see Section 14.10.6.1 Details for Synchronous Burst (SYNC) Devices see Section 14.11.13 OFF (default after reset).
Page 876 XMC4500 XMC4000 Family External Bus Unit (EBU) BUSWCONx (x = 0-3) EBU Bus Write Configuration Register(030 +x*10 Reset Value: 00D3 0000 AGEN WAIT PORTW BCGEN TINV FETBLEN Field Bits Type Description FETBLEN [2:0] Burst Length for Synchronous Burst Defines maximum number of burst data cycles which are executed by Memory Controller during a burst access to a Synchronous Burst device.
Page 877 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description ECSE Early Chip Select for Synchronous Burst CS is delayed. CS is not delayed. Note: (see Section 14.10.3 Section 14.11.7) EBSE Early Burst Signal Enable for Synchronous Burst ADV is delayed. ADV is not delayed.
Page 878 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description WAIT [25:24] rw External Wait Control Function of the WAIT input. This is specific to the device type (i.e. the AGEN field). Details for Asynchronous (ASYNC) Devices see Section 14.10.6.1 Details for Synchronous Burst (SYNC) Devices see Section 14.11.13 OFF (default after reset).
Page 879 XMC4500 XMC4000 Family External Bus Unit (EBU) BUSRAPx (x = 0-3) Bus Read Access Parameter Register (02C +x*10 Reset Value: FFFF FFFF EXTCLOC ADDRC AHOLDC CMDDELAY EXTDATA DATAC WAITRDC RDRECOVC RDDTACS Field Bits Type Description RDDTACS [3:0] Recovery Cycles between Different Regions This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of...
Page 880 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description WAITRDC [11:7] Programmed Wait States for read accesses Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock.
Page 881 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description AHOLDC [27:24] rw Address Hold Cycles This bit field determines the number of clock cycles of the address hold phase. 0000 0 clock cycle selected 0001 1 clock cycle selected 1110 14 clock cycles selected 1111...
Page 882 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description WRDTACS [3:0] Recovery Cycles between Different Regions This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of access.
Page 883 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description EXTCLOCK [17:16] rw Frequency of external clock at pin BFCLKO Equal to EBU_CLK frequency. 1/2 of EBU_CLK frequency. 1/3 of EBU_CLK frequency. 1/4 of EBU_CLK frequency (default after reset). Note: See Section 14.11.4.
Page 884: Sdram Control Registers
XMC4500 XMC4000 Family External Bus Unit (EBU) 14.16.3 SDRAM Control Registers Registers in this section are used to control the SDRAM settings. SDRMCON Basic SDRAM configuration done with this register. SDRMCON SDRAM Control Register (068 Reset Value: 8000 0000 PWR_MO CRCE BANKM ROWM...
Page 885 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description BANKM [24:22] rw Mask for bank tag AHB address bits to be used for determining bank number. Reserved; (default after reset) Address bit 21 to 20 Address bit 22 to 21 Address bit 23 to 22 Address bit 24 to 23 Address bit 25 to 24...
Page 886 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description AWIDTH [13:12] rw Width of column address Number of address bits from bit 0 to be used for Section 14.12.19 column address. See also e.g. for 16-bit DRAMs Reserved , do not use Address[8:0] Address[9:0] Address[10:0]...
Page 887 XMC4500 XMC4000 Family External Bus Unit (EBU) SDRMOD SDRAM Mode Register Reset Value: 0000 0020 XOPM OPMODE CASLAT BURSTL Field Bits Type Description [31:28] rw Extended Operation Bank Select Value to be written to the bank select pins of a “Mobile”...
Page 888 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description XOPM [27:16] rw Extended Operation Mode Value to be written to the extended mode register of a “Mobile” SDRAM device. This value is issued to the SDRAM via it’s address inputs during an extended mode register write.
Page 889 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description BURSTL [2:0] Burst length Number of locations can be accessed with a single command. 1 (default after reset) Others: Reserved Reserved Read as 0; should be written with 0. SDRMREF Used to set up the right SDRAM refresh parameters.
Page 890 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description ARFSH Auto Refresh on Self refresh Exit If set to one, an auto refresh cycle will be performed on exiting self refresh before the self refresh exit delay. If set to zero, no refresh will be performed. Note: See Section 14.12.18 SELFREX_DLY [23:16] rw...
Page 891 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description SELFREXST Self Refresh Exit Status. If this bit is set to ‘1’, it means the Self Refresh Exit command has been successfully issued. This bit is reset when bit SELFREN is set to ‘1’ or a reset takes place.
Page 892 XMC4500 XMC4000 Family External Bus Unit (EBU) Field Bits Type Description SDERR SDRAM read error SDRAM controller has detected an error when returning read data Reads running successfully Read error condition has been detected Note: This bit is reset by a write access to SDRMCON.
Page 893: Ethernet Mac (Eth)
Reduced media Independent interface The following document is reprinted with permission of Synopsys Inc. No disclosure of Databook to Synopsys' Competitors without Synopsys consent. List of Competitors is available from Infineon Technologies AG or Synopsys Inc. 15.1 Overview The ETH peripheral is comprised of five major functional units. The ETH-Core takes user provided data frames and formats them for transmission to an external PHY via an MII or RMII interface.
Page 894: Eth Core Features
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.1.1 ETH Core Features • Supports 10/100-Mbit/s data transfer rates with the following PHY interfaces – IEEE 802.3-compliant RMII/MII (default) interface to communicate with an external Fast Ethernet PHY • Supports both full-duplex and half-duplex operation –...
Page 895: Dma Block Features
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.1.2 DMA Block Features The DMA block exchanges data between the MTL block and the XMC4500 memory. A set of registers (DMA CSR) to control DMA operation is accessible by the XMC4500. DMA features include: •...
Page 896 XMC4500 XMC4000 Family Ethernet MAC (ETH) • Configurable Receive FIFO threshold (default fixed at 64 bytes) in Cut-Through mode • Option to filter all error frames on reception and not forward them to the application in Store-and-Forward mode • Option to forward under-sized good frames •...
Page 897: Monitoring, Test, And Debugging Support Features
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.1.4 Monitoring, Test, and Debugging Support Features • Supports internal loopback on the MII for debugging • External loopback is supported via the integrated MDIO controlling the PHY • DMA states (Tx and Rx) given as status bits •...
Page 898: Eth Core
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.2.1 ETH Core The ETH core supports two interfaces towards the PHY chip, MII and RMII. The PHY interface can be selected only once after reset. The ETH core communicates with the application side with the MAC Transmit Interface (MTI), MAC Receive Interface (MRI) and the MAC Control Interface (MCI).
Page 899 XMC4500 XMC4000 Family Ethernet MAC (ETH) Transmit Frame Controller Module The Transmit Frame Controller (TFC) consists of two registers to hold data, byte enables, and the last data control received from the TBU. The register provides a buffer between the Application and the TPE to regulate data flow as well as converts the input data into an 8-bit bus towards the TPE.
Page 900 XMC4500 XMC4000 Family Ethernet MAC (ETH) In MII mode, if a collision occurs any time from the beginning of the frame to the end of the CRC field, the transmit state machine sends a 32-bit jam pattern of 55555555 the MII to inform all other stations that a collision has occurred. If the collision is seen during the preamble transmission phase, the transmit state machine completes the transmission of preamble and SFD and then sends the jam pattern.
Page 901 XMC4500 XMC4000 Family Ethernet MAC (ETH) if a carrier is detected during the first two-thirds (64-bit times for all IFG values) of the IFG interval. If the carrier is detected during the final one third of the IFG interval, the STX module continues the IFG count and enables the transmitter after the IFG interval.
Page 902: Mac Transmit Interface Protocol
XMC4500 XMC4000 Family Ethernet MAC (ETH) bits ) before this Pause-time runs-out, a second Pause frame will be transmitted to the TFC module. The process will be repeated as long as the MTI flow control signal remains asserted. If the MTI flow control signal goes inactive prior to the sampling time, the FTX module will transmit a Pause frame with zero Pause Time to indicate to the remote end that the receive buffer is ready to receive new data frames.
Page 903 XMC4500 XMC4000 Family Ethernet MAC (ETH) If IEEE 1588 time stamping is enabled, the RPE takes a snapshot of the system time when any frame's SFD is detected on the MII. Unless the MAC filters out and drops the frame, this time stamp is passed on to the application. In MII mode, the RPE converts the received nibble data into bytes, then forwards the valid frame data to the RFC module The receive state machine of the RPE module decodes the Length/Type field of the...
Page 904 XMC4500 XMC4000 Family Ethernet MAC (ETH) Receive CRC Module The Receive CRC (CRX) interfaces to the RPE module to check for any CRC error in the receiving frame. This module calculates the 32-bit CRC for the received frame that includes the Destination address field through the FCS field.
Page 905 XMC4500 XMC4000 Family Ethernet MAC (ETH) Receive Frame Controller Module The Receive Frame Controller (RFC) receives the Ethernet frame data and status from the RPE module. The RFC module consists of a FIFO of parameterized depth (default set to 4 deep and 37 bits wide) and two state machines for writing and reading the FIFO. The FIFO holds the received Ethernet frame data and byte enables, along with a control bit to indicate the last data.
Page 906 XMC4500 XMC4000 Family Ethernet MAC (ETH) Receive Flow Control Module The Receive Flow Controller (FRX) detects the receiving Pause frame and pauses the frame transmission for the delay specified within the received Pause frame. The FRX module is enabled only in Full-Duplex mode. The Pause frame detection function can be ETH0_FLOW_CONTROL enabled or disabled with the .RFE bit.
Page 907 XMC4500 XMC4000 Family Ethernet MAC (ETH) RFC module. The address checking is based on different parameters (Frame Filter register) chosen by the Application. These parameters are inputs to the AFM module as control signals, and the AFM module reports the status of the address filtering based on the combination of these inputs.
Page 908 XMC4500 XMC4000 Family Ethernet MAC (ETH) to index the content of the Hash table. A value of 000000 selects Bit 0 of the selected register and a value of 111111 selects Bit 63 of the Hash Table register. If the corresponding bit is set to 1, then the multicast frame is said to have passed the Hash filter;...
Page 909 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-2 Destination Address Filtering Table Frame HPF HUC DAIF HMC PM DA Filter Operation Type Broadcast Pass Pass Fail Unicast Pass all frames. Pass on Perfect/Group filter match. Fail on Perfect/Group filter match. Pass on Hash filter match.
Page 910: Mac Transaction Layer (Mtl)
XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-2 Destination Address Filtering Table (cont’d) Frame HPF HUC DAIF HMC PM DA Filter Operation Type Fail on Hash filter match and drop PAUSE control frames if PCF = 0x. Fail on Hash or Perfect/Group filter match and drop PAUSE control frames if PCF = 0x.
Page 911 XMC4500 XMC4000 Family Ethernet MAC (ETH) out and transferred to the ETH core when triggered. When the end-of-frame is transferred, the status of the transmission is taken from the ETH core and transferred back to the DMA. The Transmit FIFO has a depth of 2K bytes. A 2 FIFO-fill level is indicated to the DMA so that it can initiate a data fetch in required bursts from the system memory, using the Bus interface.
Page 912 XMC4500 XMC4000 Family Ethernet MAC (ETH) There are no requirements for enabling the MTL. However, the ETH block and the DMA controller must be enabled individually through their respective CSRs. Single-Packet Transmit Operation During a transmit operation, the MTL block is slaved to the DMA controller. The general sequence of events for a transmit operation is as follows.
Page 913 XMC4500 XMC4000 Family Ethernet MAC (ETH) Retransmission During Collision While a frame is being transferred from the MTL to the ETH , a collision event occurs on the ETH line interface in Half-Duplex mode. The ETH then indicates a retry attempt to the MTL by giving the status even before the end-of-frame is transferred from MTL.
Page 914 XMC4500 XMC4000 Family Ethernet MAC (ETH) use of Ethernet is to encapsulate TCP and UDP over IP datagrams, the ETH has an Checksum Offload Engine (COE) to support checksum calculation and insertion in the transmit path, and error detection in the receive path. This section explains the operation of the Checksum Offload Engine for transmitted frames.
Page 915 XMC4500 XMC4000 Family Ethernet MAC (ETH) For IPv4 datagrams • The received Ethernet type is 0800 , but the IP header’s Version field does not equal • The IPv4 Header Length field indicates a value less than 5 (20 bytes) •...
Page 916: Receive Path
XMC4500 XMC4000 Family Ethernet MAC (ETH) Error status bit when it detects that the frame has been forwarded to the MAC Transmitter engine in Store-and-Forward mode without the end-of-frame being written to the FIFO, or when the packet ends before the number of bytes indicated by the Payload Length field in the IP Header is received.
Page 917 XMC4500 XMC4000 Family Ethernet MAC (ETH) valid frames are read out and forwarded to the application. In Cut-Through mode, some error frames are not dropped, because the error status is received at the end- of-frame, by which time the start of that frame has already been read out of the FIFO. Note: The time-stamp transfer takes two clock cycles and the lower 32-bit of the time- stamp is given out first.
Page 918: Dma Controller
XMC4500 XMC4000 Family Ethernet MAC (ETH) and RDES4 in Receive Descriptor, except that bits 31, 14, 9, and 8 of normal status is reserved and have a reset value of 0 . When the status of a partial frame due to overflow is given out, the Frame Length field in the status word is not valid. 15.2.3 DMA Controller The DMA has independent Transmit and Receive engines, and a CSR space.
Page 919: Initialization
XMC4500 XMC4000 Family Ethernet MAC (ETH) Ring Structure Chain Structure Buffer 1 Buffer 1 Descriptor 0 Descriptor 0 Buffer 2 Buffer 1 Descriptor 1 Buffer 2 Buffer 1 Descriptor 1 Buffer 1 Descriptor 2 Buffer 2 Buffer 1 Descriptor 2 Buffer 1 Descriptor n Buffer 2...
Page 920 XMC4500 XMC4000 Family Ethernet MAC (ETH) 4. Write Registers ETH0_TRANSMIT_POLL_DEMAND ETH0_RECEIVE_POLL_DEMAND , and Receive Descriptor List Address for desired filtering options. 5. Write to ETH0_MAC_CONFIGURATION Register to configure and enable the Transmit and Receive operating modes. The ETH0_MAC_CONFIGURATION bit is set based on the auto-negotiation result (read from the PHY). 6.
Page 921 XMC4500 XMC4000 Family Ethernet MAC (ETH) XMC4500 Data Buffer Alignment The Transmit and Receive data buffers do not have any restrictions on start address alignment. For example, the start address for the buffers can be aligned to any of the four bytes.
Page 922: Transmission
XMC4500 XMC4000 Family Ethernet MAC (ETH) bytes, even though the buffer size is programmed as 1024 bytes, due to the start address offset. DMA Arbiter The arbiter inside the DMA module performs the arbitration between the Transmit and Receive channel accesses to the Bus Master interface. Two types of arbitrations are possible: round-robin, and fixed-priority.
Page 923 XMC4500 XMC4000 Family Ethernet MAC (ETH) descriptor. If time stamping was not enabled for this frame, the DMA does not alter the contents of TDES2 and TDES3 8. Transmit Interrupt ( ETH0_STATUS .TI ) is set after completing transmission of a frame that has Interrupt on Completion (TDES1[31] ) set in its Last Descriptor.
Page 924 XMC4500 XMC4000 Family Ethernet MAC (ETH) Start TxDMA (Re-)fetch next descriptor Poll demand TxDMA suspended bit set? Transfer data from buffer (s) Frame transfer complete? Close intermediate Wait for Tx status descriptor Time stamp Write time stamp to TDES2 and TDES 3 present? Write status word to TDES 0...
Page 925 XMC4500 XMC4000 Family Ethernet MAC (ETH) Transmit Descriptor list for the second frame. If the second frame is valid, the transmit process transfers this frame before writing the first frame’s status information. In OSF mode, the Run state Transmit DMA operates in the following sequence: 1.
Page 926 XMC4500 XMC4000 Family Ethernet MAC (ETH) Start TxDMA (Re-)fetch next descriptor Poll demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) Time stamp present? Second Frame transfer Write time stamp to frame? complete? TDES2 & TDES3 for previous frame Close intermediate Wait for previous...
Page 927: Reception
XMC4500 XMC4000 Family Ethernet MAC (ETH) Frames can be data-chained and can span several buffers. Frames must be delimited by the First Descriptor (TDES1[29] ) and the Last Descriptor (TDES1[30] respectively. As transmission starts, the First Descriptor must have (TDES1[29] ) set.
Page 928 XMC4500 XMC4000 Family Ethernet MAC (ETH) 1. The CPU sets up Receive descriptors (RDES0 -RDES3 ) and sets the Own bit (RDES0[31 2. Once the ETH0_OPERATION_MODE .SR bit is set, the DMA enters the Run state. While in the Run state, the DMA polls the Receive Descriptor list, attempting to acquire free descriptors.
Page 929 XMC4500 XMC4000 Family Ethernet MAC (ETH) Start RxDMA (Re-)Fetch next Poll demand/ descriptor new frame available RxDMA suspended Frame transfer Own bit set? complete? Frame data Flush disabled? available? Flush the Write data to buffer(s) Wait for frame data remaining frame Fetch next descriptor Flush Own bit set...
Page 930 XMC4500 XMC4000 Family Ethernet MAC (ETH) Otherwise (that is, if time stamping is not enabled), the RDES2 and RDES3 remain unchanged. Receive Descriptor Acquisition The Receive Engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is satisfied: •...
Page 931: Interrupts
XMC4500 XMC4000 Family Ethernet MAC (ETH) Receive Process Suspended If a new Receive frame arrives while the Receive Process is in Suspend state, the DMA refetches the current descriptor in the XMC4500 memory. If the descriptor is now owned by the DMA, the Receive Process re-enters the Run state and starts frame reception. If the descriptor is still owned by the CPU, by default, the DMA discards the current frame at the top of the MTL Rx FIFO and increments the missed frame counter.
Page 932 XMC4500 XMC4000 Family Ethernet MAC (ETH) completes a transfer of a received frame to system memory without asserting the Receive Interrupt because it is not enabled in the corresponding Receive Descriptor (RDES1[31] in Table 7-3). When this timer runs out as per the programmed value, RI interrupt asserted corresponding...
Page 933: Dma Descriptors
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.2.4 DMA Descriptors This chapter describes the descriptor format used by the ETH DMA.The ETH DMA descriptors are held in RAM. To avoid confusion with the ETH registers the DMA descriptors use the subscript ] for example RDES0[0] 15.2.4.1 Descriptor Formats The DMA in the Ethernet subsystem transfers data based on a linked list of descriptors,...
Page 934 XMC4500 XMC4000 Family Ethernet MAC (ETH) is unknown). Before the RxDMA closes a descriptor, it will attempt to acquire the next descriptor even if no frames are received. In a single descriptor (receive) system, the subsystem will generate a descriptor error if the receive buffer is unable to accommodate the incoming frame and the next descriptor is not owned by the DMA.
Page 935 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-4 Receive Descriptor 0 (cont’d) Description 29:1 FL: Frame Length These bits indicate the byte length of the received frame that was transferred to XMC4500 memory (including CRC). This field is valid when Last Descriptor (RDES0[8] is set and either the Descriptor Error (RDES0[14] ) or Overflow...
Page 936 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-4 Receive Descriptor 0 (cont’d) Description VLAN: VLAN Tag When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame tagged by the ETH Core. FS: First Descriptor When set, this bit indicates that this descriptor contains the first buffer of the frame.
Page 937 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-4 Receive Descriptor 0 (cont’d) Description CE: CRC Error When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received frame. This field is valid only when the Last Descriptor (RDES0[8] ) is set.
Page 938 XMC4500 XMC4000 Family Ethernet MAC (ETH) RDES1 contains the buffer sizes and other bits that control the descriptor chain/ring. Note: See Buffer Size Calculations for further detail on calculating buffer sizes. Table 15-6 Receive Descriptor 1 Description Disable Interrupt on Completion When set, this bit will prevent the setting of the ETH0_STATUS .RI bit of the...
Page 939 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-7 Receive Descriptor 2 (Default Operation) Description 31:0 Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There are no limitations on the buffer address alignment except for the following condition: The DMA uses the configured value for its address generation when the RDES2 value is used to store the start of frame.
Page 940 XMC4500 XMC4000 Family Ethernet MAC (ETH) TDES0 Status Control Byte Count Byte Count TDES1 Bits Buffer 2 Buffer 1 TDES2 Buffer 1 Address Buffer 2 Address / Next Descriptor Address TDES3 Figure 15-8 Transmit Descriptor Format Transmit Descriptor 0 (TDES0 TDES0 contains the transmitted frame status and the descriptor ownership information.
Page 941 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-9 Transmit Descriptor 0 (cont’d) Description TTSS: Tx Time Stamp Status This status bit indicates that a time stamp has been captured for the corresponding transmit frame. When this bit is set, TDES2 and TDES3 have time stamp values that were captured for the transmit frame.
Page 942 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-9 Transmit Descriptor 0 (cont’d) Description LC: Loss of Carrier When set, this bit indicates that Loss of Carrier occurred during frame transmission . This is valid only for the frames transmitted without collision and when the ETH operates in Half-Duplex Mode.
Page 943 XMC4500 XMC4000 Family Ethernet MAC (ETH) Transmit Descriptor 1 (TDES1 TDES1 contains the buffer sizes and other bits which control the descriptor chain/ring and the frame being transferred. Note: See Buffer Size Calculations for further detail on calculating buffer sizes. Table 15-10 Transmit Descriptor 1 Description IC: Interrupt on Completion...
Page 944 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-10 Transmit Descriptor 1 (cont’d) Description TCH: Second Address Chained When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES1[24] is set, TBS2 (TDES1[21–11] ) are “don’t care”...
Page 945 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-12 Transmit Descriptor 3 Description 31:0 Buffer 2 Address Pointer (Next Descriptor Address) Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (TDES1[24] ) bit is set, this address contains the pointer to the physical memory where the Next Descriptor is present.
Page 946 XMC4500 XMC4000 Family Ethernet MAC (ETH) The following sections describe the details specific to receive and transmit descriptors in this mode. Reference Manual 15-54 V1.6, 2016-07 ETH, V1.71 Subject to Agreement on the Use of Product Information...
Page 947 XMC4500 XMC4000 Family Ethernet MAC (ETH) Receive Descriptor Receive Time Stamp The tables below describe the fields that have different meaning for RDES2 RDES3 when the receive descriptor is closed and time stamping is enabled. Note: When software disables time stamping feature (the...
Page 948 XMC4500 XMC4000 Family Ethernet MAC (ETH) Status [16:0] TDES0 Buffer 2 Byte Count Buffer 1 Byte Count Other Control TDES1 [21:11] [10:0] Fields Buffer 1 Address [31:0] TDES2 TDES3 Buffer 2 Address [31:0] or Next Descriptor Address [ 31:0] Figure 15-10 Transmit Descriptor Fields Transmit Time Stamp Control and Status Fields The value of this field shall be preserved by the DMA at the time of closing the descriptor.
Page 949 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-16 Transmit Time Stamp Control – Normal Descriptor Format Case (TDES1 Description TTSE: Transmit Time Stamp Enable When set, this field enables IEEE1588 hardware time stamping for the transmit frame described by the descriptor. This field is valid only when the First Segment control bit (TDES1[29] in the descriptor) is set.
Page 950 XMC4500 XMC4000 Family Ethernet MAC (ETH) • The normal descriptor structure allows data buffers of up to 2.048 bytes. The alternative descriptor structure has been implemented to support buffers of up to 8 KB (useful for Jumbo frames). • There is a re-assignment of control and status bits in TDES0, TDES1, RDES0 (Advanced time stamp or IPC full offload configuration), RDES1.
Page 951 XMC4500 XMC4000 Family Ethernet MAC (ETH) Ctrl Ctrl TDES0 Statu s [16:0] [30:26] [23:20] TDES1 Bu ffer 2 Byte Count [28:16] Buffe r 1 Byte Cou nt[12:0] TDES2 Bu ffer 1 Address [31:0] TDES3 Buffer 2 Address [31:0] o r Ne xt Descrip tor Add ress[31:0] Reserved TDES Reserved...
Page 952 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-19 Transmit Descriptor Word 0 (TDES0) Description OWN: Own Bit When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame transmission or when the buffers allocated in the descriptor are read completely.
Page 953 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-19 Transmit Descriptor Word 0 (TDES0) (cont’d) Description 23:22 CIC: Checksum Insertion Control These bits control the checksum calculation and insertion. Bit encodings are as shown below. • 2’b00: Checksum Insertion Disabled. • 2’b01: Only IP header checksum calculation and insertion are enabled.
Page 954 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-19 Transmit Descriptor Word 0 (TDES0) (cont’d) Description ES: Error Summary Indicates the logical OR of the following bits: • TDES0[14]: Jabber Timeout • TDES0[13]: Frame Flush • TDES0[11]: Loss of Carrier • TDES0[10]: No Carrier •...
Page 955 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-19 Transmit Descriptor Word 0 (TDES0) (cont’d) Description EC: Excessive Collision When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the DR (Disable Retry) bit in the GMAC Configuration register is set, this bit is set after the first collision, and the transmission of the frame is aborted.
Page 956 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-20 Transmit Descriptor Word 1 (TDES1) (cont’d) Description 15:13 Reserved 12:0 TBS1: Transmit Buffer 1 Size These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).
Page 957 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-24 Transmit Descriptor 7 (TDES7) Description 31:0 TTSH: Transmit Frame Time Stamp High This field is updated by DMA with the most significant 32 bits of the time stamp captured for the corresponding receive frame. This field has the time stamp only if the Last Segment bit (LS) in the descriptor is set and Time stamp status (TTSS) bit is set.
Page 958 XMC4500 XMC4000 Family Ethernet MAC (ETH) STATUS [30:0] RDES 0 R SVD Buffer2 Byte Count Buffer1 Byte Count CTRL RDES [30:29 [12:0] [ 28:16] [15:14 Buffer1 Address [31:0] RDES Buffer2 Address [31:0] or Next Descriptor Address [31:0] RDES Extended STATUS [31:0] RDES4 Reserved RDES5...
Page 959 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-25 Receive Descriptor Fields (RDES0) Description OWN: Own Bit When set, this bit indicates that the descriptor is owned by the DMA of the GMAC Subsystem. When this bit is reset, this bit indicates that the descriptor is owned by the Host.
Page 960 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-25 Receive Descriptor Fields (RDES0) (cont’d) Description LE: Length Error When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset.
Page 961 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-25 Receive Descriptor Fields (RDES0) (cont’d) Description RWT: Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and the current frame is truncated after the Watchdog Timeout.
Page 962 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-26 Receive Descriptor Fields 1 (RDES1) (cont’d) Description 28:16 RBS2: Receive Buffer 2 Size These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8, or 16, depending on the bus widths (32, 64, or 128, respectively), even if the value of RDES3 (buffer2 address pointer) is not aligned to bus width.
Page 963 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-27 Receive Descriptor Fields 2 (RDES2) Description 31:0 Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1. There are no limitations on the buffer address alignment except for the following condition: The DMA uses the configured value for its address generation when the RDES2 value is used to store the start of frame.
Page 964 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-29 Receive Descriptor Fields 4 (RDES4) Description 31:14 Reserved PTP Version When set, indicates that the received PTP message is having the IEEE 1588 version 2 format. When reset, it has the version 1 format. This is valid only if the message type is non-zero.
Page 965 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-29 Receive Descriptor Fields 4 (RDES4) (cont’d) Description IP Payload Error When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP checksum) that the core calculated does not match the corresponding checksum field in the received segment.
Page 966: Mac Management Counters
XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-31 Receive Descriptor Fields 7 (RDES7) Description 31:0 RTSH: Receive Frame Time Stamp High This field is updated by DMA with the most significant 32 bits of the time stamp captured for the corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]).
Page 967: Pmt Block Description
XMC4500 XMC4000 Family Ethernet MAC (ETH) When the power down mode is enabled in the PMT, then all received frames are dropped by the core and they are not forwarded to the application. The core comes out of the power down mode only when either a Magic Packet or a Remote Wake-up frame is received and the corresponding detection is enabled.
Page 968 XMC4500 XMC4000 Family Ethernet MAC (ETH) Wakeup fame filter reg0 Filter 0 Byte Mask Wakeup frame filter reg1 Filter 1 Byte Mask Wakeup frame filter reg2 Filter 2 Byte Mask Wakeup frame filter reg3 Filter 3 Byte Mask Filter 3 Filter 2 Filter 1 Filter 0...
Page 969: Remote Wake-Up Frame Detection
XMC4500 XMC4000 Family Ethernet MAC (ETH) Filter i CRC-16 This register contains the CRC_16 value calculated from the pattern, as well as the byte mask programmed to the wake-up filter register block. 15.2.6.2 Remote Wake-Up Frame Detection When the ETH is in sleep mode and the remote wake-up bit is enabled in PMT Control and Status register , normal operation is resumed after receiving a remote wake-up frame.
Page 970: System Considerations During Power-Down
XMC4500 XMC4000 Family Ethernet MAC (ETH) any breaks or interruptions. In case of a break in the 16 repetitions of the address, the FFFF FFFF FFFF pattern is scanned for again in the incoming frame. The 16 repetitions can be anywhere in the frame, but must be preceded by the synchronization stream (FFFF FFFF FFFF ).
Page 971: Phy Interconnect
XMC4500 XMC4000 Family Ethernet MAC (ETH) 6. Gate the application and transmit clock inputs to the core (and other relevant clocks in the system) to reduce power and enter Sleep mode. 7. On receiving a valid wake-up frame, the ETH asserts the power management interrupt signal and exits Power-Down mode.
Page 972: Station Management Functions
XMC4500 XMC4000 Family Ethernet MAC (ETH) External ETH SMI MDIO MAC Module Figure 15-14 SMA Interface Block 15.2.8.1 Station Management Functions The ETH initiates the Management Write/Read operation. The MDC clock is a divided clock from the ETH MAC clock . The divide factor depends on the clock range setting in the MII Address register.
Page 973: Station Management Write Operation
XMC4500 XMC4000 Family Ethernet MAC (ETH) REG ADDR Register address in the selected PHY Turnaround is Z0 for Read and 10 for Write Any 16-bit value. In a Write operation, the ETH drives DATA mdio; in a Read operation, PHY drives it. 15.2.8.2 Station Management Write Operation When the user sets the MII Write and Busy bits ( ETH0_GMII_ADDRESS...
Page 974: Media Independent Interface
XMC4500 XMC4000 Family Ethernet MAC (ETH) register address in PHY to the SMA to initiate a Read operation in the PHY registers. At this point, the SMA module starts a Read operation on the MII Management Interface using the Management Frame Format specified in the MII specifications (Section 22.2.4.5 of IEEE Standard).
Page 975: Reduced Media Independent Interface
XMC4500 XMC4000 Family Ethernet MAC (ETH) the current received packet. The two remaining control signals are MII collision detect (MII_COL) which is asserted by the PHY when an arbitration collision occurs and MII carrier sense (MII_CRS) which is asserted by the PHY when either Transmit or Receive are not idle.
Page 976: Rmii Block Diagram
XMC4500 XMC4000 Family Ethernet MAC (ETH) Ethernet MAC RMII_RX_CLK RMII_CRS_DV RMII_RXD[0..1] RMII_RX_ERR RMII_TXD[0..1] RMII_TX_ENA Figure 15-18 Reduced Media Independent Interface Note: The MAC Configuration.FES bit configures the RMII to operate at 10 Mbit/s or 100 Mbit/s. 15.2.10.1 RMII Block Diagram Figure 15-19 shows the position of the RMII block relative to the ETH and RMII PHY.
Page 977: Transmit Bit Ordering
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.2.10.3 Transmit Bit Ordering Each nibble from the MII must be transmitted on the RMII a di-bit at a time with the order of di-bit transmission shown in Figure 15-20 . The lower order bits (D1 and D0) are transmitted first followed by higher order bits (D2 and D3).
Page 978 XMC4500 XMC4000 Family Ethernet MAC (ETH) CLK_RX MII_TX_EN MII_TXD[3:0] CLK_RMII RMII_TX_EN RMII_TXD[1:0] Figure 15-21 Start of MII and RMII Transmission in 100 Mbit/s Mode Figure 15-22 shows the end of frame transmission for MII and RMII in 100 Mbit/s mode. CLK_RX MII_TX_EN MII_TXD[3:0]...
Page 979 XMC4500 XMC4000 Family Ethernet MAC (ETH) CLK_RX MII_TX_EN MII_TXD[3:0] RMII CLK RMII_TX_EN RMII_TXD[1:0] Figure 15-23 Start of MII and RMII Transmission in 10 Mbit/s Mode Figure 15-24 shows the end of MII transmission and RMII transmission in 10 Mbit/s mode. CLK_RX MII_TX_EN MII_TXD[3:0]...
Page 980: Ieee 1588-2002 Overview
XMC4500 XMC4000 Family Ethernet MAC (ETH) Di-Bit Stream mii_rxd[3:0] Nibble Stream Figure 15-25 Receive Bit Ordering 15.2.11 IEEE 1588-2002 Overview The IEEE 1588 standard defines a protocol enabling precise synchronization of clocks in measurement and control systems implemented with technologies such as network communication, local computing, and distributed objects.
Page 981 XMC4500 XMC4000 Family Ethernet MAC (ETH) Figure 15-26 Networked Time Synchronization 1. The master broadcasts PTP Sync messages to all its nodes. The Sync message contains the master’s reference time information. The time at which this message leaves the master’s system is t1 and must, for Ethernet ports, be captured at the MII. 2.
Page 982: Reference Timing Source
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.2.11.1 Reference Timing Source To get a snapshot of the time, the core requires a reference time in 64-bit format (split into two 32-bit channels, with the upper 32-bits providing time in seconds, and the lower 32-bits indicating time in nanoseconds) as defined in the IEEE 1588 specification.
Page 983: Time Stamp Error Margin
XMC4500 XMC4000 Family Ethernet MAC (ETH) to the descriptors (RDES2 and RDES3), indicating that time stamp is not correct. If the software uses a control register bit to disable time stamping, the DMA does not alter RDES2 or RDES3. Note: When the alternate (enhanced) descriptor is selected, the 64-bit time-stamp is written in RDES6 and RDES7, respectively.
Page 984: Advanced Time Stamp Feature Support
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.2.11.6 Advanced Time Stamp Feature Support In addition to the basic features for time stamp mentioned in Receive Time Stamp , the advanced time stamp option has the following features. • Support for the IEEE 1588-2008 (Version 2) timestamp format. •...
Page 985 XMC4500 XMC4000 Family Ethernet MAC (ETH) Figure 15-27 Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction The link delay measurement starts with port-1 issuing a “Pdelay_Req” message and generating a timestamp, for the Pdelay_Req message. Port-2 receives the “Pdelay_Req” message and generates a timestamp, t2, for this message. Port-2 returns a Pdelay_Resp message and generates a timestamp, t3, for this message.
Page 986: Clock Types
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.2.11.8 Clock Types The type of clock nodes supported in IEEE 1588-2008 is described in this section. The corresponding support provided by the advanced time stamp feature for each of the clock type is also mentioned. 1.
Page 987: Ptp Processing And Control
XMC4500 XMC4000 Family Ethernet MAC (ETH) timestamp is not required). The message type statuses provided helps you to quickly identity the message and update the correctionField. The message type status provided will also help in taking appropriate action depending on the type of PTP message received. 4.
Page 988 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-35 Message Format Defined in IEEE 1588-2008 BITS OCTETS OFFSET transportSpecific messageType Reserved versionPTP messageLength domainNumber Reserved flagField correctionField Reserved sourcePortIdentity sequenceId controlField logMessageInterva controlField is used in version 1. For version 2, messageType field will be used for detecting different message types.
Page 989 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-36 IPv4-UDP PTP Frame Fields Required for Control and Status (cont’d) Field Matched Octet Matched Value Description Position IP Multicast address 30, 31, 32, Multicast IPv4 addresses (IEEE 1588 version allowed. (or 82 or 83 224.0.1.129 224.0.1.130...
Page 990 XMC4500 XMC4000 Family Ethernet MAC (ETH) Table 15-37 IPv6-UDP PTP Frame Fields Required for Control and Status Field Matched Octet Matched Value Description Position MAC Frame type 12, 13 86DD IP datagram IP version 14 (bits IP version is IPv6 [7:4]) Layer-4 protocol PTP Multicast...
Page 991: Reference Timing Source (For Advance Timestamp Feature)
XMC4500 XMC4000 Family Ethernet MAC (ETH) for tagged frames will be offset by 4. This is based on Appendix-E of the IEEE 1588-2008 standard and the message format defined in Table 15-35 Table 15-38 Ethernet PTP Frame Fields Required for Control And Status Field Matched Octet Matched Value...
Page 992: Transmit Path Functions
XMC4500 XMC4000 Family Ethernet MAC (ETH) b) UInteger32-nanoseconds field The “seconds” field is the integer portion of the timestamp in units of seconds. The “nanoseconds” field is the fractional portion of the timestamp in units of nanoseconds. E.g. 2.000000001 seconds is represented as secondsField = 0000 0000 0002 and nanoSeconds = 0000 0001 .
Page 993: System Time Register Module
XMC4500 XMC4000 Family Ethernet MAC (ETH) Note that PTP messages over VLAN frames are also supported. 15.2.12 System Time Register Module A system time clock is maintained in this module. A 64 bit timer is incremented using the PTP clock ( ) as reference.
Page 994 XMC4500 XMC4000 Family Ethernet MAC (ETH) addend _val[31:0] addend _ updt Addend register Accumulator register Constant value Increment Sub Second Register Sub-second register Increment Second Register Second register Figure 15-28 System Time Update Using Fine Method The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns accuracy.
Page 995: Application Bus Interface
XMC4500 XMC4000 Family Ethernet MAC (ETH) Figure 15-28 , the constant value used to accumulate the sub-second register is decimal 43, which achieves an accuracy of 20 ns in the system time (in other words, it is incremented in 20-ns steps). Two different methods are used to update the System Time register, depending on which configuration you choose (See Block Diagram The software must calculate the drift in frequency based on the Sync messages and...
Page 996 XMC4500 XMC4000 Family Ethernet MAC (ETH) CSR space. The DMA can be used in applications where DMA is required to optimize data transfer between the ETH and system memory. The Bus Master interface converts the internal DMA request cycles into Bus cycles. Characteristics of this interface include the following: •...
Page 997: Service Request Generation
XMC4500 XMC4000 Family Ethernet MAC (ETH) The Bus 32-bit Slave interface provides access to the DMA and ETH CSR space. Characteristics of this interface include the following: • Supports single and INCR4/8transfers • Supports busy and early terminations • Supports 32-bit, 16-bit, and 8-bit write/read transfers to the CSR; 32-bit access to the CSR are recommended to avoid any SW synchronization problems.
Page 998: Dma Service Requests
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.3.1 DMA Service Requests The ETH DMA has two groups of Service Request, Normal and Abnormal requests. Each Service Request source is enabled in the ETH0_INTERRUPT_ENABLE register. Each group of Service Requests must also be enabled by setting the Normal Interrupt enable and Abnormal Interrupt enable bits in the same register.
Page 999: Debug
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.4 Debug Module specific debug behavior TBD In addition the ETH has a number of intrinsic features to assist debugging, these are described below. • DEBUG register provides flags which indicate the operating status of the ETH MAC and MTL.
Page 1000: Eth Registers
XMC4500 XMC4000 Family Ethernet MAC (ETH) 15.6 ETH Registers The application controls the ETH by reading from and writing to the Control and Status Registers (CSRs) through the BUS Slave interface. These registers are 32 bits wide and the addresses are 32-bit block aligned 15.6.1 Register Description ETH Register Map...

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