A2 Front Panel Processor; A9 Cpu/A10 Digital If; Main Cpu - HP 8753D Option 011 Service Manual

as communications between the analyzer and an external controller and/or peripherals.
Figure 12-3 is a simpli ed block diagram of the digital control functional group.
Figure DIBLK12 here.
Figure 12-3. igital Control Group, Simplified Block iagram
A1 Front Panel
The A1 front panel assembly provides user interface with the analyzer. It includes the
keyboard for local user inputs, and the front panel LEDs that indicate instrument status. The
RPG (rotary pulse generator) is not electrically connected to the front panel, but provides
user inputs directly to the front panel processor.

A2 Front Panel Processor

The A2 front panel processor detects and decodes user inputs from the front panel and the
RPG, and transmits them to the CPU. It has the capability to interrupt the CPU to provide
information updates. It controls the front panel LEDs that provide status information to the
user.

A9 CPU/A10 Digital IF

The A9 CPU assembly contains the main CPU (central processing unit), the digital signal
processor, memory storage, and interconnect port interfaces. The main CPU is the master
controller for the analyzer, including the other dedicated microprocessors. The memory
includes EEPROM, RAM, EPROM, and ROM.
Data from the receiver is serially clocked into the A9 CPU assembly from the A10 digital IF.
The data taking sequence is triggered either from the A14 fractional-N assembly, externally
from the rear panel, or by software on the A9 assembly.

Main CPU

The main CPU is a 16-bit microprocessor that maintains digital control over the entire
instrument through the instrument bus. The main CPU receives external control information
from the front panel or P-IB, and performs processing and formatting operations on the raw
RAFT Theory of Operation 12-7
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