Cortex ® -M3/4/7 Case; Figure 40. Cortex ® -M3 Scb_Ccr Description; Figure 41. Cortex-M3 Scb_Cfsr Description - STMicroelectronics STM32 Application Note

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6.3.2 Cortex
For targets that support hardware division instructions, Trapping of DIV0 operation is
possible by configuring System Control Block (SCB) registers, accessible through CMSIS
library.
For example on Cortex
SCB_CCR register description is provided in
Refer to STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual (PM0056).
Setting bit 5 of SCB_CCR register
SCB->CCR |= 0x10; // enable div-by-0 trap
When Div0 occurs it is trapped in HardFault_Handler.
With breakpoint on while instruction into HardFault_Handler, CallStack point to the offended
line and SCB->CFSR register explicits the type of fault
SCB_CFSR register description is provided in
The following sections describe the management of SCB registers as a function of the
selected IDE.
®
-M3/4/7 case
®
-M3:
Figure 40. Cortex

Figure 41. Cortex-M3 SCB_CFSR Description

Figure 40.
®
-M3 SCB_CCR Description
Figure 41.
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