Mitsubishi Electric MELSEC iQ-R Series User Manual page 149

Channel isolated thermocouple input module/channel isolated rtd input module
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CH1 Rate alarm lower limit value
Set a lower limit on the change rate of measured temperature values for rate alarm detection.
For details on the alert output function, refer to the following.
Page 27 Alert Output Function
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Rate alarm lower limit value
CH Rate alarm lower limit value (in Q
compatible mode)
■Setting range
The possible range is from -32768 to 32767 (-3276.8 to 3276.7). (can be set in a unit of 0.1)
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9) to enable the setting.
■Default value
The default value is 0 for all the channels.
• When using the rate alarm, configure the 2-step settings for the rate alarm upper limit value and lower limit
value.
• A channel where the set values do not satisfy the condition "Rate alarm lower limit value  Rate alarm upper
limit value" causes a rate alarm upper/lower limit setting value inversion error (error code: 1BAH).
• Since the default value is 0, change the setting value.
CH1 Disconnection detection enable/disable setting
Set whether to enable or disable the disconnection detection function.
For details on the disconnection detection function, refer to the following.
Page 34 Disconnection Detection Function
Setting value
0
1
Setting a value other than the above causes a disconnection detection enable/disable setting range error (error code:
1C5H).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Disconnection detection enable/disable
setting
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9) to enable the setting.
■Default value
The default value is Disable (0) for all the channels.
CH1
CH2
CH3
526
726
926
135
137
139
Setting content
Enable
Disable
CH1
CH2
CH3
530
730
930
CH4
CH5
CH6
1126
1326
1526
141
143
145
CH4
CH5
CH6
1130
1330
1530
Appendix 3 Buffer Memory Areas
CH7
CH8
1726
1926
147
149
A
CH7
CH8
1730
1930
APPX
147

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