6.3 X2 Connector Signal Descriptions (XTX
Table 8
Signal
LPC_AD[0..3]
LPC_FRAME#
LPC_DRQ[0..1]#
Table 9
Signal
SATA0_RX+
SATA0_RX-
SATA0_TX+
SATA0_TX-
SATA1_RX+
SATA1_RX-
SATA1_TX+
SATA1_TX-
SATA2_RX+
SATA2_RX-
SATA2_TX+
SATA2_TX-
SATA3_RX+
SATA3_RX-
SATA3_TX+
SATA3_TX-
IL_SATA#
SATALED#
Copyright © 2006 congatec AG
LPC Interface Signal Descriptions
Description
Multiplexed Command, Address and Data. I/O3.3V
Frame: Indicates start of a new cycle or
termination of a broken cycle.
Encoded DMA/Bus Master Request.
Serial ATA Signal Descriptions
Description
Serial ATA channel 0, Receive Input
differential pair.
Serial ATA channel 0, Transmit Output
differential pair.
Serial ATA channel 1, Receive Input
differential pair.
Serial ATA channel 1, Transmit Output
differential pair.
Serial ATA channel 2, Receive Input
differential pair.
Serial ATA channel 2, Transmit Output
differential pair.
Serial ATA channel 3, Receive Input
differential pair.
Serial ATA channel 3, Transmit Output
differential pair.
Serial ATA Interlock Switch Input.
Serial ATA Led. Open collector output pin
driven during SATA command activity.
I/O
O 3.3V
I 3.3V
I/O
I SATA
O SATA
I SATA
O SATA
N.C.
N.C.
N.C.
N.C.
I
OC 3.3V
X800m12
™
extension)
PU/PD
Comment
PU 10k
3.3V
PU 10k
3.3V
PU 10k
LPC_DRQ1 not supported
3.3V
PU/PD
Comment
Supports Serial ATA
specification, Revision
1.0
Supports Serial ATA
specification, Revision
1.0
Supports Serial ATA
specification, Revision
1.0
Supports Serial ATA
specification, Revision
1.0
Not supported
Not supported
Not supported
Not supported
Not supported
35/72
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