STMicroelectronics ST10 Series Programming Manual page 81

EXTSR
Syntax
Operation
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes
all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes being made to the
Extended SFR space for a specified number of instructions. During their execution, both standard and
PEC interrupts and class A hardware traps are locked. The EXTSR instruction becomes immediately
active such that no additional NOPs are required. For any long ('mem') or indirect ([...]) address in an
EXTSR instruction sequence, the value of op1 determines the 8-bit segment (address bits A23-A16) valid
for the corresponding data access. The long or indirect address itself represents the 16-bit segment offset
(address bits A15-A0). The value of op2 defines the length of the effected instruction sequence.
Note: The EXTSR instruction must be used carefully (see Section 2.7 - ATOMIC and EXTended instruc-
tions on page 38).
Flags
E
-
E Not affected
Z Not affected
V Not affected
C Not affected
N Not affected
Addressing Modes
Mnemonic
EXTSR
EXTSR
Begin EXTended Segment & Register Sequence
EXTSR
(count)
Disable interrupts and Class A traps
Data_Segment = (op1) AND SFR_range = Extended
DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE)
Next Instruction
(count)
END WHILE
(count) = 0
Data_Page = (DPPx) AND SFR_range = Standard
Enable interrupts and traps
Z
-
Rwm, #data
2
#seg, #data
2
ST10 FAMILY PROGRAMMING MANUAL
op1, op2
[1 ≤ op2 ≤ 4]
<-- (op2)
<-- (count) - 1
V
-
Format
DC 10##:m
D7 10##:0 ss 00
C N
- -
Bytes
2
4
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