STMicroelectronics ST10 Series Programming Manual page 131

CoADD(2)
Group
Syntax
Operation
Syntax
Operation
Data Types
Result
Description
Adds a 40-bit operand to the 40-bit Accumulator contents and store the result in the accumulator. The
40-bit operand results from the concatenation of the two source operands op1 (LSW) and op2 (MSW)
which is then sign-extended. "2" option indicates that the 40-bit operand is also multiplied by two prior
being added to ACC. When the MS bit of the MCW register is set and when a 32-bit overflow or underflow
occurs, the obtained result becomes 00 7FFF FFFF
repeatable with indirect addressing modes and allows up to two parallel memory reads.
MAC Flags
N
*
N Set if the most significant bit of the result is set. Cleared otherwise.
Z Set if the result equals zero. Cleared otherwise.
C Set if a carry is generated. Cleared otherwise.
SV Set if an arithmetic overflow occurred. Not affected otherwise.
E Set if MAE is used. Cleared otherwise.
SL Set if the contents of the ACC is automatically saturated. Not affected otherwise.
Note : The E-flag is set when the nine highest bits of the accumulator are not equal. The SV-flag is set,
when a 40-bit arithmetic overflow/ underflow occurs.
Addressing Modes
Mnemonic
CoADD Rw , Rw
n
CoADD2 Rw , Rw
n
CoADD [IDX
CoADD2 [IDX
CoADD Rw , [Rw
n
CoADD2 Rw , [Rw
n
Add
40-bit Arithmetic Instructions
CoADD
(tmp)
(ACC)
CoADD2
(tmp)
(ACC)
DOUBLE WORD
40-bit signed value
Z C
*
m
m
⊗], [Rw ⊗]
i m
⊗], [Rw ⊗]
i m
⊗]
m
⊗]
m
ST10 FAMILY PROGRAMMING MANUAL
op1, op2
<-- (op2)\(op1)
<-- (ACC) + (tmp)
op1, op2
<-- 2 * (op2)\(op1)
<-- (ACC) + (tmp)
or FF 8000 0000
h
SV
* *
Rep Format
No A3 nm 02 00
No A3 nm 42 00
Yes 93 Xm 02 rrrr:rqqq
Yes 93 Xm 42 rrrr:rqqq
Yes 83 nm 02 rrrr:rqqq
Yes 83 nm 42 rrrr:rqqq
, respectively. This instruction is
h
E
*
SL
*
Bytes
4
4
4
4
4
4
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