Revision 4 - revision 3
Instructions: CoMULsu(-), CoMULus(-),
CoMAC(r)su(-), CoMAC(r)us(-), CoMACM(r)su(-),
CoMAC(r)us(-), CoNOP, CoSHL, CoSHR, CoASHR,
CoSTORE
Instructions JBC and JNBS:
Table 22: Instruction set ordered by Hex code :
Instruction CoMULus(-):
Table 5: Branch target address summary :
Table 24: Condition codes :
Section 2.4.6: Repeated instruction syntax :
Instruction CoSHL:
Instruction CoNOP:
Instruction BCLR:
MAC instruction descriptions:
Section 2.1: Addressing modes :
Section 1.2.1: Definition of measurement units :
Revision 3 - revision 2
CoSUB2r replaced CoSUBr2.
In MAC instructions, lower case r has replaced upper case R for optional repeat.
Revision 2 - revision 1
"Definition of measurement units" on page 12, ALE Cycle Time corrected.
"Integer Addition with Carry" on page 59: instruction name changed from ADDBC to ADDCB.
ST10 FAMILY PROGRAMMING MANUAL
Addressing modes corrected.
Function code in Table 30 corrected.
Condition flags corrected.
Updated to include section C0-FF, MAC
instructions and working register indexes.
Example corrected.
Seg address range corrected.
Condition Code Mnemonic cc_N corrected.
Sentence added.
Description clarified: "Only shift values from 0
to 8 (inclusive)".
⊗] addressing mode and example
[IDX
i
removed. Reference to this addressing mode
removed from Table 29.
Condition flag Z corrected.
Ordered Alphabetically.
Paragraph added.
[Fcpu] changed to 0-50MHz.
171/172
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