Atomic And Extended Instructions - STMicroelectronics ST10 Series Programming Manual

ST10 FAMILY PROGRAMMING MANUAL
Number of bytes Specifies the size of an instruc-
tion in bytes. All ST10 instructions are either 2 or 4
bytes. Instructions are classified as either single
word or double word instructions (see Figure 3).

2.7 - ATOMIC and EXTended instructions

ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR
instructions disable standard and PEC interrupts
and class A traps during a sequence of the follow-
ing 1...4 instructions. The length of the sequence
is determined by an operand (op1 or op2, depend-
ing on the instruction). The EXTended instructions
also change the addressing mechanism during
this sequence (see detailed instruction descrip-
tion).
The ATOMIC and EXTended instructions become
active immediately, so no additional NOPs are
required. All instructions requiring multiple cycles
or hold states to be executed are regarded as one
instruction in this sense. Any instruction type can
Figure 3 : Instruction format representation
Representation in the
Assembler Listing:
Internal Organization:
38/172
be used with the ATOMIC and EXTended instruc-
tions.
CAUTION: When a Class B trap interrupts an
ATOMIC or EXTended sequence, this sequence is
terminated, the interrupt lock is removed and the
standard condition is restored, before the trap rou-
tine is executed! The remaining instructions of the
terminated sequence that are executed after
returning from the trap routine, will run under stan-
dard conditions!
CAUTION:
EXTended instructions with other system control
or branch instructions.
CAUTION: When using nested ATOMIC and
EXTended instructions. There is ONE counter to
control the length of this sort of sequence, i.e.
issuing an ATOMIC or EXTended instruction
within a sequence will reload the counter with
value of the new instruction.
N2-N1 N4-N3
High Byte 1st word
Low Byte 1st word
MSB
N8 N7 N6 N5
When using the
N6-N5 N8-N7
High Byte 2nd word
Low Byte 2nd word
Bits in ascending order LSB
N4 N3 N2
ATOMIC and
N1