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2.6.8 - Addressing modes
Specifies available combinations of addressing
modes. The selected addressing mode combina-
tion is generally specified by the opcode of the
corresponding instruction.
However, there are some arithmetic and logical
instructions where the addressing mode combina-
tion is not specified by the (identical) opcodes but
by particular bits within the operand field.
In the individual instruction description, the
addressing mode is described in terms of mne-
monic, format and number of bytes.
Table 26 : Instruction format symbols
00
through FF
h
h
0, 1
:....
:..ii
ss
:..##
:.###
c
n
m
q
z
#
QQ
rr
RR
ZZ
##
@@
pp 0:00pp
MM MM
## ##
Constant Values
Each of the 4 characters immediately following a colon represents a single bit
2-bit short GPR address (Rw
8-bit code segment number (seg).
2-bit immediate constant (#data
3-bit immediate constant (#data
4-bit condition code specification (cc)
4-bit short GPR address (Rw
4-bit short GPR address (Rw
4-bit position of the source bit within the word specified by QQ
4-bit position of the destination bit within the word specified by ZZ
4-bit immediate constant (#data
8-bit word address of the source bit (bitoff)
8-bit relative target address word offset (rel)
8-bit word address reg
8-bit word address of the destination bit (bitoff)
8-bit immediate constant (#data
8-bit immediate constant (#mask
10-bit page address (#pag10)
16-bit address (mem or caddr; low byte, high byte)
16-bit immediate constant (#data
ST10 FAMILY PROGRAMMING MANUAL
– Mnemonic gives an example of which operands
the instruction will accept.
– Format specifies the format of the instruction as
used in the assembler listing. Figure 3 shows
the reference between the instruction format
representation of the assembler and the corre-
sponding internal organization of the instruction
format (N = nibble = 4 bits). The following sym-
bols are used to describe the instruction for-
mats:
Instruction Opcodes
)
i
)
2
)
3
or Rb
)
n
n
or Rb
)
m
m
)
4
)
8
)
8
; low byte, high byte)
16
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