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ST10 FAMILY PROGRAMMING MANUAL
DIVLU
Syntax
Operation
Data Types
Description
Performs an extended unsigned 32-bit by 16-bit division of the two words stored in the MD register by the
source word operand op1. The unsigned quotient is then stored in the low order word of the MD register
(MDL) and the remainder is stored in the high order word of the MD register ( MDH).
Flags
E
0
E
Always cleared.
Z
Set if result equals zero. Cleared otherwise.
V
Set if an arithmetic overflow occurred, i.e. the result cannot be represented in a word data
type, or if the divisor (op1) was zero. Cleared otherwise.
C
Always cleared.
N
Set if the most significant bit of the result is set. Cleared otherwise.
Addressing Modes
Mnemonic
DIVLU
72/172
32-by-16 Unsigned Division
DIVLU
(MDL)
(MDH)
WORD, DOUBLEWORD
Z
*
Rw
n
op1
<-- (MD) / (op1)
<-- (MD) mod (op1)
V
S
Format
7B nn
C
N
0
*
Bytes
2
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