Instruction Set Ordered By Opcodes - STMicroelectronics ST10 Series Programming Manual

ST10 FAMILY PROGRAMMING MANUAL

2.5 - Instruction set ordered by opcodes

The following pages list the instruction set ordered
by their hexadecimal opcodes. This is used to
identify specific instructions when reading execut-
able code, i.e. during the debugging phase.
Notes for Opcode Lists
1. Some instructions are encoded by means of
additional bits in the operand field of the instruction
x0h - x7h:Rw, #data
x8h - xBh:Rw, [Rw]
xCh - xFh Rw, [Rw+] or Rb, [Rw+]
For these instructions only the lowest four GPRs,
R0 to R3, can be used as indirect address
pointers.
2. Some instructions are encoded by means of
additional bits in the operand field of the instruc-
tion.
00xx.xxxx: EXTS
01xx.xxxx: EXTP
Table 21 : Instruction set ordered by Hex code
Hex- code Number of Bytes
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
26/172
or Rb, #data
3
or Rb, [Rw]
or ATOMIC
Mnemonic
2 ADD
2 ADDB
4 ADD
4 ADDB
4 ADD
4 ADDB
4 ADD
4 ADDB
2 ADD
2 ADDB
4 BFLDL
2 MUL
2 ROL
2 JMPR
2 BCLR
2 BSET
2 ADDC
2 ADDCB
00xx.xxxx: EXTS
10xx.xxxx: EXTSR
11xx.xxxx: EXTPR
Notes on the JMPR instructions
The condition code to be tested for the JMPR
instructions is specified by the opcode. Two mne-
monic representation alternatives exist for some
of the condition codes.
3
Notes on the BCLR and BSET instructions
The position of the bit to be set or to be cleared is
specified by the opcode. The operand "bitaddr
(where q=0 to 15) refers to a particular bit within a
bit-addressable word.
Notes on the undefined opcodes
A hardware trap occurs when one of the unde-
fined opcodes signified by '----' is decoded by the
CPU.
Rw , Rw
n m
Rb , Rb
n m
reg, mem
reg, mem
mem, reg
mem, reg
reg, #data
16
reg, #data
16
Rw , [Rw +] or Rw
n i
Rb , [Rw +] or Rb
n i
bitoff , #mask
Q
Rw , Rw
n m
Rw , Rw
n m
cc_UC, rel
bitaddr
Q.0
bitaddr
Q.0
Rw , Rw
n m
Rb , Rb
n m
or ATOMIC
or EXTR
Operand
, [Rw ] or Rw , #data
n i n
, [Rw ] or Rb , #data
n i n
, #data
8 8
"
Q.q
3
3