External Sdram Interface - Renesas M3A-HS64 User Manual

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2.3.3 External SDRAM Interface

The M3A-HS64 comes standard with an SDRAM listed in the table below. The SDRAM is controlled by the SH7264 on-chip Bus
State Controller (BSC). The M3A-HS64 allows 16-bit bus access only.
The figure below shows the SDRAM block diagram, and Table 2.3.5 lists the DIP switches setting (SW5-4).
Item
Part number
Configuration
Capacity
Access time
CAS latency
Refresh
Row address
Column address
Number of banks
SH7264
PD15-PD4/D15-D4
PD3-PD0/D3-D0
PB14-PB13/A14-A13
PB12-PB1/A12-A1
PC2/RD/WR#
PC3/WE0#/DQML
PC4/WE1#/DQMU/WE#
PC5/RAS#/TIOC4A/IRQ4
PC6/CAS#/TIOC4B/IRQ5
PC7/CKE/TIOC4C/IRQ6
PC8/CS3#/TIOC4D/IRQ7
Note: Pin names in red indicate the function used.
Rev. 1.00 Apr 30, 2009
REJ11J0034-0100
Table 2.3.4 SDRAM Specifications
EDS1216AHTA-75E
16 MB (Bus size: 16-bit) x 1
16 MB
7.5 ns
2 (When the system clock works at 72 MHz)
4096 cycles every 64 ms
A11 to A0
A8 to A0
4 (controlled by BA0, and BA1)
NAND flash memory
CKIO
SDRAM
D1
D2
D3
D4
MUX
EN#
3.3 V
DIP
SW5-4
Figure 2.3.3 External SDRAM Block Diagram
Description
12
4
2
12
3.3 V
3.3 V
or MTU2
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
IN
Expansion connector
4
M3A-HS64 Functions
2.3.3 External SDRAM Interface
EDS1216AHTA-75E
16 MB
(2 M × 16-bit × 4 banks)
DQ15-DQ4
DQ3-DQ0
BA1-BA0
A11-A0
CLK
WE#
LDQM
UDQM
3.3 V
RAS#
CAS#
CKE
CS#
MTU2 output (M3A-HS64G02)
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