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4
4.10 PWM Interface
The SH7264 includes two channels of on-chip Motor Control Pulse Width Modulator (PWM) timer with a maximum of eight
pulse outputs per channel. The SH7264 PWM output pin is connected to a 20-pin MIL-spec connector on the M3A-HS64G02 via
the voltage level shifter. The PWM output pin is also used as the SDHI pin and SSIF channel 0 pin.
The figure below shows the PWM interface block diagram. The table below lists the jumper setting (JP3).
SH7264
PK0/PWM1A/SD_D2
PK1/PWM1B/SD_D3
PK2/PWM1C/SD_CMD
PK3/PWM1D/SD_CLK
PK4/PWM1E/SD_D0
PK5/PWM1F/SD_D1
PK6/PWM1G/SD_WP
PK7/PWM1H/SD_CD
PK8/PWM2A/SSICK0
PK9/PWM2B/SSIWS0
PK10/PWM2C/SSIRxD0
PK11/PWM2D/SSITxD0
PJ8/PWM2E
PJ9/PWM2F/TEND1
PJ10/PWM2G/DREQ1
PJ11/PWM2H/DACK1
Note: Pin names
in red
indicate the function used.
Number
Connected to the PWM interface (default)
JP3
Rev. 1.00 Apr 30, 2009
REJ11J0034-0100
PWM
or SD
Expansion connector
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
MUX
EN#
IN
PWM
or SD
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
MUX
EN#
IN
PWM
or SSIF
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
MUX
EN#
IN
PWM
or PORT
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
MUX
EN#
IN
3.3 V
JP3
3
2
1
Figure 4.10.1 PWM Interface Block Diagram
Table 4.10.1 Jumper Setting (JP3)
1-2 (Low)
M3A-HS64G02 Functions
8
SDHI
4
SSIF
3.3 V
4
PORT interface
Character LCD interface
HD151015
1A
Level shifter
1B
1A
A0
1C
1B
A1
1C
A2
1D
1D
A3
1E
A4
1F
A5
1G
A6
3.3 V
1H
A7
A8
1E
DIR
1F
VccA
1G
1H
3.3 V
HD151015
Level shifter
2A
2A
A0
2B
A1
2B
2C
A2
2C
2D
A3
2E
A4
2D
2F
A5
2G
A6
3.3 V
2H
A7
A8
DIR
VccA
2E
2F
2G
2H
2-3 (High)
Connected to the SDHI/SSIF/PORT interface
4.10 PWM Interface
20-pin
MIL-spec connector
B0
B1
B2
B3
B4
B5
B6
B7
A8
5 V
G#
VccB
B0
B1
B2
5 V
B3
VCC
B4
GND
B5
B6
B7
A8
5 V
G#
VccB
4-23
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