Renesas M3A-HS64 User Manual page 51

2
Number
SW6-1 NOR flash memory is write-enabled (default)
The figure below shows the write and read access timing example of the NOR flash memory. The table below lists the bus state
controller settings (write/read) when the SH7264 bus clock works at 72 MHz.
Write and read timing
Write1
Th T1 Tw 1 Tw 2 Tw 3
CKIO
tWC tWC
tAD1
A21-A1
tCSD1
CS0#
RD#
tWED1
tCS
tAS tWP tWP
WE0#
tDS
tWDD1
D15-D0 DATA
Table 2.3.3 Bus State Controller Setting (Write and read the NOR flash memory)
User area Target device
CS0 S29GL032N90TFI020 CS0 Space Bus Control Register (CS0BCR):
Rev. 1.00 Apr 30, 2009
REJ11J0034-0100
Table 2.3.2 DIP Switches Setting (SW6-1)
OFF (High)
Tw 4 T2 Tf Taw 1 Taw 2 Th T1
tAD1 tAD1
tCSD1 tCSD1
tWED1 tWED1
tCH
tAH tAS
tWPH tWPH
tDH
tWDH1 tWDD1
Figure 2.3.2 NOR Flash Memory write/read Access Timing Example
Initial value: H'36DB 0400 (MD = Low)
Recommended value: H'1240 0400
• Idle Cycles between Write-Read Cycles and Write-Write Cycles
IWW[2:0] = B'001; 1 idle cycle inserted
• Idle Cycles for Another Space Read-Write
IWRWD[2:0] = B'001; 1 idle cycle inserted
• Idle Cycles for Read-Write in the Same Space
IWRWS[2:0] = B'001; 1 idle cycle inserted
• Data bus width
BSZ[1:0] = B'10; 16-bit
CS0 Space Wait Control Register (CS0WCR):
Initial value: H'0000 0500
Recommended value: H'0000 0B41
• Number of Delay Cycles from address, CS0# Assertion to RD#, WEn# Assertion:
SW[1:0] = B'01; 1.5 cycles
• Number of Access Wait Cycles
WR[3:0] = B'0110; 6 cycles
• External WAIT Mask Specification
WM = B'1; Ignore external WAIT input
• Number of Delay Cycles from RD#, WEn# Negation to address, CS0# Negation
HW[1:0] = B'01; 1.5 cycles
Function
NOR flash memory is write-protected
Write2
Tw 1 Tw 2 Tw 3 Tw 4 T2 Tf Taw 1 Taw 2
tAD1
tCSD1
tWED1
tCH
tAH
tWP tWP tOEH
tDS
tDH
tWDH1
DATA
Setting
M3A-HS64 Functions
2.3.2 NOR Flash Memory Interface
ON (Low)
Read1
Th T1 Tw 1 Tw 2 Tw 3 Tw 4 T2
tRC tRC
tAD1
tCSD1
tRSD tRSD
ta(OE)
ta(AD)
tRDS1
tDF(CE)
DATA
Tf
tAD1
tCSD1
tDF(C
tRDH1
tDF(OE)
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