Renesas M3A-HS64 User Manual page 54

2
User Area Target Device
CS3 EDS1216AHTA-75E
Rev. 1.00 Apr 30, 2009
REJ11J0034-0100
Table 2.3.6 Bus State Controller Setting (Read and Write the SDRAM)
CS3 space bus control register (CS3BCR):
Initial value: H'36DB 0400
Recommended value: H'0000 4400
• Memory
TYPE[2:0] = B'100; SDRAM
• Data bus width
BSZ[1:0] = B'10; 16-bit
CS3 space wait control register (CS3WCR):
Initial value: H'0000 0500, Recommended value: H'0000 288A
• Number of Auto-Precharge Completion Wait Cycles:
WTRP[1:0] = B'01; 1 cycle
• Number of Wait Cycles between ACTV Command and READ
(A)/WRIT(A) Command
WTRC [1:0] = B'10; 2 cycles
• CAS Latency for Area 3
A3CL[1:0] = B'01; 2 cycles
• Number of Auto-Precharge Startup Wait Cycles
TRWL[1:0] = B'01; 1 cycle
• Number of Idle Cycles from REF Command/Self-Refresh Release to
ACTV/REF/MRS Command:
WTRC [1:0] = B'10; 5 cycles
SDRAM control register (SDCR):
Initial value: H'0000 0000, Recommended value: H'0000 0809
• Refresh Control
RFSH = B'1; SDRAM is refreshed
• Refresh Control
RMODE = B'0; Auto-refreshed
• Bank Active Mode
BACTV = B'0; Auto-precharge mode
• Number of Bits of Row Address for Area 3
A3ROW[1:0] = B'01; 12 bits
• Number of Bits of Column Address for Area 3
A3COL[1:0] = B'01; 9 bits
Refresh Timer Control/Status Register (RTCSR):
Initial value: H'0000 0000, Recommended value: H'A55A 0010
• Clock Select
CKS[2:0] = B'010; BΦ/16
• Refresh Count
RRC[2:0] = B'000; 1 time
Refresh Time Constant Register (RTCOR):
Initial value: H'0000 0000, Recommended value: H'A55A 0046
The refresh request interval when the clock select is set to BΦ/16 is as
follows:
1 cycle: 222 nsec (72 MHz/16 = 4.5 MHz)
Refresh request interval in this SDRAM: 15.625 μsec/time
15.625 usec/222 nsec = 70 (0x46) cycles/refresh counts
M3A-HS64 Functions
2.3.3 External SDRAM Interface
Setting
2-16