Renesas M3A-HS64 User Manual page 106

4
Peripheral
Pin Name
Function
MTU2 TIOC4D
TIOC4C
TIOC4B
TIOC4A
TIOC3D
TIOC3C
TIOC2B
TIOC2A
TIOC1B
TIOC1A
TIOC0D
TIOC0C
TIOC0B
TIOC0A
TCLKD
TCLKC
TCLKB
TCLKA
Peripheral
Pin Name
Function
SSIF SSITxD0
SSIWS0
SSISCK0
Peripheral
Pin Name
Function
ADC AN7
AN3
AN2
AN1
AN0
Rev. 1.00 Apr 30, 2009
REJ11J0034-0100
Table 4.2.16 SH7264 Multiplex Pin Functions (MTU2)
SH7264 Port Control Register
Register Name MD bit Setting
PCCR2 PC8MD[1:0] = B'10
PCCR1 PC7MD[1:0] = B'10
PCCR1 PC6MD[1:0] = B'10
PCCR1 PC5MD[1:0] = B'10
PFCR3 PF12MD[2:0] = B'100
PFCR2 PF11MD[2:0] = B'100
PCCR2 PC10MD0 = B'1
PCCR2 PC9MD0 = B'1
PJCR1 PJ7MD[1:0] = B'01
PJCR1 PJ6MD[1:0] = B'01
PGCR6 PG24MD[1:0] = B'10
PGCR5 PG23MD[1:0] = B'10
PGCR5 PG22MD[1:0] = B'10
PGCR5 PG21MD[1:0] = B'10
PFCR1 PF7MD[2:0] = B'100
PFCR1 PF5MD[2:0] = B'100
PFCR1 PF6MD[2:0] = B'100
PECR0 PE1MD[2:0] = B'100
Table4.2.17 SH7264 Multiplex Pin Functions (SSIF)
SH7264 Port Control Register
Register Name MD bit Setting
PKCR2 PK11MD[1:0] = B'10
PKCR2 PK9MD[1:0] = B'10
PKCR2 PK8MD[1:0] = B'10
Table 4.2.18 SH7264 Multiplex Pin Functions (ADC)
SH7264 Port Control Register
Register Name MD bit Setting
PHCR1 PH7MD0 = B'1
PHCR0 PH3MD0 = B'1
PHCR0 PH2MD0 = B'1
PHCR0 PH1MD0 = B'1
PHCR0 PH0MD0 = B'1
4.2.4 SH7264 Multiplex Pins Used on the M3A-HS64G02
Multiplex Pin Name
PC8/CS3#/TIOC4D/IRQ7
PC7/CKE/TIOC4C/IRQ6
PC6/CAS#/TIOC4B/IRQ5
PC5/RAS#/TIOC4A/IRQ4
PF12/BS#/MISO0/TIOC3D/SPDIF_OUT
PF11/A25/SSIDATA3/MOSI0/TIOC3C/SPDIF_IN
PC10/TIOC2B
PC9/TIOC2A
PJ7/TIOC1B/CTS3#
PJ6/TIOC1A/SCK3
PG24/MISO1/TIOC0D
PG23/MOSI1/TIOC0C
PG22/SSL10/TIOC0B
PG21/RSPCK1/TIOC0A
PF7/CE2A#/SSIWS3/DV_DATA7/TCLKD
PF5/CS5#/CE1A#/SSIDATA2/DV_DATA5/TCLKC/
AUDATA3
PF6/CS6#/CE1B#/SSISCK3/DV_DATA6/TCLKB
PE1/SDA0/IOIS16#/IRQ1/TCLKA/ADTRG#
Multiplex Pin Name
PK11/PWM2D/SSITxD0
PK9/PWM2B/SSIWS0
PK8/PWM2A/SSISCK0
Multiplex Pin Name
PH7/AN7
PH3/AN3
PH2/AN2
PH1/AN1
PH0/AN0
M3A-HS64G02 Functions
SH7264
SH7264
SH7264
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