Renesas M3A-HS64 User Manual page 53

2
Number
Connected to the SDRAM (default)
SW5-4
The following figure shows the single read and write timing example of the SDRAM. Table 2.3.6 lists the bus state controller
setting when the SH7264 bus clock works at 72 MHz.
ACT
T r T rw
CKIO
CKE
tSI
tCSD1
CS3#
tHI
tSI
tRASD1
RASL#
CASL#
RD/WR#
tDQMD1
DQMUU-LL
tAD1
A11-A2(A9-A0)
tAD1
A12(A10/AP)
tAD1
A15,A14(BA1,0)
D0-31
Rev. 1.00 Apr 30, 2009
REJ11J0034-0100
Table 2.3.5 DIP Switches Setting (SW5-4)
OFF(High)
SDRAM SINGLE READ
tRC tRC
tRAS tRAS
tRCD tRCD
READA
T c1 T cw T d1
tRASD1
tHI
tSI
tCASD1
tCASD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tRDS2
tLZ tOH
tAC
Data
Figure 2.3.4 SDRAM Single Read/Write Timing Example
Function
Connected to the MTU2 interface
tRP tRP
ACT
T de T ap T r T rw
tSI
tHI
tCSD1 tCSD1
tRASD1
tRASD1
tDQMD1 tDQMD1
tAD1
tAD1
tRDH2
tOHZ
M3A-HS64 Functions
2.3.3 External SDRAM Interface
ON (Low)
SDRAM SINGLE WRITE
tRC tRC
tRAS tRAS
tRCD tRCD tDPL tDPL
tDAL tDAL
WRIT EA
T c1 T rw11 T rw12
tHI
tCSD1
tCASD1
tCASD1
tRWD1
tRWD1
tDQMD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tHI
tSI
tWDH2
Data
tRP tRP
ACT
T ap T r
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