Ethernet Interface - Analog Devices ADSP-BF518F EZ-Board Manual

Ethernet Interface

clockwise for the down function, or can be pushed towards the center of
the board to clear the counter.
The rotary switch is a two-bit quadrature (gray code) counter with a
detent, meaning that both the down signal (
gle when the count register increases on a rotation to the right. Upon
rotating to the left,
If the processor pins are needed for the expansion interface II, disconnect
the rotary encoder switch via the three-position rotary enable switch
( ). For more information, see "Encoder Enable Switch (SW19)" on
SW19
page 2-13.
An example program is included in the EZ-Board installation directory to
demonstrate how to set up and access the rotary encoder interface.
Ethernet Interface
The ADSP-BF518F processor has an integrated Ethernet MAC with a
media independent interface (MII), which connects to an external PHY
device. The EZ-Board provides a National Semiconductor DP83848C
Ethernet PHY with auto-MDIX, fully compliant with IEEE 802.3u stan-
dards. The DP83848C chip supports 10BASE-T and 100BASE-TX
operations. The part is attached gluelessly to the processor.
The Ethernet signals are shared with the PPI signals, connected to the
expansion interface II, and two MII connectors that can be used to inter-
face with other PHY evaluation boards.
The PHY can be put into a power-down mode by installing
power-down mode should be used whenever the PHY is not used, and the
expansion interface signals are used. See
(JP17)" on page 2-16
late mode by installing
the PHY is not used, and another PHY is connected to one of the MII
1-20
and toggle, and the overall count decreases.
CDG CUD
for more information. The PHY can be put into iso-
. The isolate mode should be used whenever
JP18
ADSP-BF518F EZ-Board Evaluation System Manual
) and up signal (
CDG
"Ethernet Power Down Jumper
) tog-
CUD
. The
JP17