UPS5000-E-(50 kVA-300 kVA)
User Manual (50 kVA Power Modules)
Item
Total harmonic
distortion of output
voltage (THDv)
Output PF
Transfer time
Output voltage
unbalance
Overload capability
8.9 System Electrical Specifications
Item
Redundancy design
ECO in a parallel
system
Issue 11 (2019-12-20)
200K
≤ 1% (full linear load)
≤ 4% (full non-linear load)
1
0 ms (uninterruptible transfer)
≤ 20 ms (interruptible transfer)
Voltage unbalance: ± 3%; phase unbalance: 120± 2°
Inverter overload capability:
100% < load ≤ 110%: transfer to bypass mode after 60 min
110% < load ≤ 125%: transfer to bypass mode after 10 min
(tolerance ± 0.1 min)
125% < load ≤ 150%: transfer to bypass mode after 1 min
Load > 150% or a short circuit occurs: run for 200 ms
Bypass overload capability:
Temperature ≤ 30°C, load ≤ 135%: run for a long time
Temperature ≤ 40°C, load ≤ 125%: run for a long time
Load > 1000%: run for 100 ms
200K
The auxiliary power supplies, centralized controllers, and parallel
signals use redundancy design.
Supported
Copyright © Huawei Technologies Co., Ltd.
8 Technical Specifications
300K
300K
252