Clear Interrupt And Fifo - Base+8 And Base+9; D/A Output Channel 0 - Base+10 And Base+11; Table C-9: Register To Clear Interrupt And Fifo; Table C-10: Register For Load D/A Channel 0 Data - Advantech MIC-3716 Manual

C.9 Clear Interrupt and FIFO — BASE+8 and BASE+9
Writing data to either of these two bytes clears the interrupt or the
FIFO.

Table C-9: Register to clear interrupt and FIFO

Write
Bit #
BASE + 9
BASE + 8
C.10 D/A Output Channel 0 — BASE+10 and BASE+11
The MIC-3716 provides an innovative design as gate control for the
Analog Output function. It works as a general Analog Output function
when you disable the flag (bit 3 (DA0_LDEN) of BASE+14). That
means data will be output immediately. However, when you enable the
flag, you need to read these two registers BASE+10 and BASE+11 to
output the data to the Analog Output channel.

Table C-10: Register for load D/A channel 0 data

Read
Bit #
BASE + 11
BASE + 10
90
7 6 5
7 6 5
Clear Interrupt and FIFO
4 3
Clear FIFO
Clear Interrupt
Load D/A Channel 0 data
4 3
2 1 0
2 1 0