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Analog Output
Channels
Resolution
Operation mode
Throughput
Using Internal
Output Range
Reference
( Internal &
External
Using External
Reference)
Reference
Accuracy
Dynamic
Setting Time
Performance
Slew Rate
Drift
Driving
Capability
Output
Impedance
Digital Input/Output
Input Channels
Input Voltage
Input Load
Output Channels
Output Voltage
Counter/Timer
Channels
Resolution
Compatibility
Base Clock
Max. Input
Frequency
Clock Input
Gate Input
Counter Output
2
16-bit
Single output
200 KS/s max. per channel ( FSR)
0 ~ +5V, 0 ~ +10V, - 5V ~ + 5V, - 10V ~
0 ~ +x V @ + x V ( - 10 ≦ x ≦ 10 )
- x~ +x V @ + x V ( - 10 ≦ x ≦ 10 )
DNLE: ± 1 LSB (monotonic)
DC
Zero (Offset) error: Adjustable to ± 1 LSB
Gain (Full-scale) error: Adjustable to ± 1
5 µs ( to 4 LSB of FSR )
10 ppm / °C
±20mA
0.1O max.
16
Low
High
Low
0.4 V max. @ - 0.2mA
High
2.7V min. @ 20µ A
16
Low
0.4 V max. @ + 8.0 mA (sink)
High
2.4V min. @ - 0.4 mA (source)
3 channels, 2 channels are permanently
configured as programmable pacers;1 channel
is free for user application
16-bit
TTL level
Channel 2:Takes input from output of channel 1
Channel 1:1MHz
Channel 0: Internal 1MHz or external clock ( 10
MHz ) max Selected by software
1 M Hz
Low
High
Low
High
Low
0.5 V max. @ +24mA
High
2.4 V min. @ -15mA
+10V
INLE: ± 1 LSB
LSB
20 V / µs
0.4 V max.
2.4V min.
0.8 V max.
2.0 V min.
0.8 V max.
2.0 V min.
69
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