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Appendix A. Specifications
Analog Input
Channels
Resolution
FIFO Size
Max. Sampling
Rate
Conversion Time
Input range and
Unipolar
Gain List
Bipolar
Small Signal
Bandwidth for
Bandwidth
PGA
Common mode
Voltage
Max. Input
Voltage
Input Protect
Input Impedance
Trigger Mode
Accuracy
Trigger
Clocking and
Trigger Inputs
External
trigger
68
16 Single-Ended or 8rdiggerential or combination
16-bit
1K samples
250 KS/s max.
2.5 µs
Gain
0.5
1
N/A
0~10
±5V
±10V
Gain
0.5
1
4.0 M Hz 4.0 M Hz 2.0 M Hz 1.5 M Hz
± 11 V max. ( operational )
±20V
30 Vp-p
100 MO / 10 pF(Off) ; 100 MO / 10 0pF(On)
Software, On-board Programmable Pacer or external
INLE: ± 1 LSB
DNLE: ± 1 LSB
Zero (Offset) error: Adjustable to ± 1 LSB
DC
Gain
0.5
Gain
0.03
error
(%FSR)
AC
ENOB: 13.5 bits
Software, on-board programmable pacer or external
Mode
A/D
pacer
250 k Hz (max.) ; 58 µs Hz (min.)
clock
A/D
Min. pulse width: 2µs (high); 2µs ( low)
Max. frequency: 250kHz
Clock
2
4
8
0~5
0~2.5
0~1.25
±2.5V
±1.25V
±0.625V
2
4
8
0.65 M
Hz
1
2
4
0.02
0.02
0.03
0.04
SNR : 82 dB
8
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