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GD32F20 Series
GigaDevice Semiconductor GD32F20 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32F20 Series. We have
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GigaDevice Semiconductor GD32F20 Series manuals available for free PDF download: User Manual, Hardware Development Manual
GigaDevice Semiconductor GD32F20 Series User Manual (950 pages)
ARM Cortex-M3 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 13 MB
Table of Contents
Table of Contents
2
List of Figures
20
List of Tables
28
System and Memory Architecture
32
ARM Cortex-M3 Processor
32
Figure 1-1. Cortex™-M3 Block Diagram
32
System Architecture
33
Memory Map
34
Figure 1-2. Gd32F20X Connectivity Line Series System Architecture
34
Table 1-1 Memory Map of Gd32F20X Devices
35
Bit-Banding
38
On-Chip SRAM Memory
39
On-Chip Flash Memory
39
Boot Configuration
39
Table 1-2. each Block of SRAM
39
Device Electronic Signature
40
Table 1-3. Boot Modes
40
Table 1-4. Bootloader Supported Peripherals
40
Memory Size Information
41
Unique Device ID (96 Bits)
41
System Configuration Registers
42
Flash Memory Controller (FMC)
44
Overview
44
Characteristics
44
Function Overview
44
Flash Memory Architecture
44
Read Operations
45
Unlock the Fmc_Ctlx Registers
45
Table 2-1. Gd32F20X_Cl
45
Page Erase
46
Mass Erase
47
Figure 2-1. Process of Page Erase Operation
47
Figure 2-2. Process of Mass Erase Operation
48
Main Flash Programming
49
Option Bytes Erase
50
Figure 2-3. Process of Word Program Operation
50
Option Bytes Modify
51
Option Bytes Description
51
Table 2-2. Option Byte
52
Page Erase/Program Protection
53
Security Protection
53
Register Definition
53
Wait State Register (FMC_WS)
53
Unlock Key Register 0(FMC_KEY0)
54
Option Byte Unlock Key Register (FMC_OBKEY)
54
Status Register 0 (FMC_STAT0)
55
Control Register 0(FMC_CTL0)
56
Address Register 0 (FMC_ADDR0)
57
Option Byte Status Register (FMC_OBSTAT)
57
Erase/Program Protection Register (FMC_WP)
58
Unlock Key Register 1(FMC_KEY1)
58
Status Register 1 (FMC_STAT1)
59
Control Register 1(FMC_CTL1)
60
Address Register 1 (FMC_ADDR1)
61
Wait State Enable Register (FMC_WSEN)
61
Product ID Register (FMC_PID)
62
Power Management Unit (PMU)
63
Overview
63
Characteristics
63
Function Overview
63
Figure 3-1. Power Supply Overview
63
Battery Backup Domain
64
VDD /V Dda
65
Figure 3-2. Waveform of the POR/PDR
65
Figure 3-3. Waveform of the LVD Threshold
66
Power Domain
67
Power Saving Modes
67
Table 3-1. Power Saving Mode Summary
68
Register Definition
70
Control Register (PMU_CTL)
70
Control and Status Register (PMU_CS)
71
Backup Registers (BKP)
73
Overview
73
Characteristics
73
Function Overview
73
RTC Clock Calibration
73
Tamper0 Detection
74
Tamper1 Detection
74
Waveform Detection
74
Register Definition
75
Backup Data Register X (Bkp_Datax) (X= 0
75
RTC Signal Output Control Register (BKP_OCTL)
75
Tamper Pin Control Register0 (BKP_TPCTL0)
76
Tamper Control and Status Register (BKP_TPCS)
76
Tamper Pin Control Register1 (BKP_TPCTL1)
78
Reset and Clock Unit (RCU)
80
Reset Control Unit (RCTL)
80
Overview
80
Function Overview
80
Clock Control Unit (CCTL)
81
Overview
81
Figure 5-1. the System Reset Circuit
81
Figure 5-2. Clock Tree
82
Characteristics
83
Function Overview
83
Figure 5-3. HXTAL Clock Source
84
Table 5-1. Clock Output 0 Source Select
86
Table 5-2. Clock Output 1 Source Select
87
Table 5-3. 1.2V Domain Voltage Selected in Deep-Sleep Mode
87
Register Definition
88
Control Register (RCU_CTL)
88
Configuration Register 0 (RCU_CFG0)
90
Interrupt Register (RCU_INT)
93
APB2 Reset Register (RCU_APB2RST)
96
APB1 Reset Register (RCU_APB1RST)
99
AHB1 Enable Register (RCU_AHB1EN)
101
APB2 Enable Register (RCU_APB2EN)
103
APB1 Enable Register (RCU_APB1EN)
106
Backup Domain Control Register (RCU_BDCTL)
109
Reset Source/Clock Register (RCU_RSTSCK)
110
AHB1 Reset Register (RCU_AHB1RST)
112
Configuration Register 1 (RCU_CFG1)
112
Deep-Sleep Mode Voltage Register (RCU_DSV)
114
AHB2 Enable Register (RCU_AHB2EN)
115
APB2 Additional Enable Register (RCU_ADDAPB2EN)
116
APB1 Additional Enable Register (RCU_ADDAPB1EN)
117
AHB2 Reset Register (RCU_AHB2RST)
117
APB2 Additional Reset Register (RCU_ADDAPB2RST)
118
APB1 Additional Reset Register (RCU_ADDAPB1RST)
119
Configuration Register 2 (RCU_ CFG2)
120
PLLT Control Register (RCU_PLLTCTL)
121
PLLT Interrupt Register (RCU_PLLTINT)
122
PLLT Configuration Register (RCU_PLLTCFG)
122
Interrupt/Event Controller(EXTI)
125
Overview
125
Characteristics
125
Interrupts Function Overview
125
Table 6-1. NVIC Exception Types in Cortex-M3
126
Table 6-2. Interrupt Vector Table
126
External Interrupt and Event (EXTI) Block Diagram
129
External Interrupt and Event Function Overview
129
Figure 6-1. Block Diagram of EXTI
129
Table 6-3. EXTI Source
130
Register Definition
131
Interrupt Enable Register (EXTI_INTEN)
131
Event Enable Register (EXTI_EVEN)
131
Rising Edge Trigger Enable Register (EXTI_RTEN)
132
Falling Edge Trigger Enable Register (EXTI_FTEN)
132
Software Interrupt Event Register (EXTI_SWIEV)
132
Pending Register (EXTI_PD)
133
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
134
Overview
134
Characteristics
134
Function Overview
134
Figure 7-1. the Basic Structure of a Standard I/O and Five-Volt Tolerant I/O Port
135
Table 7-1. GPIO Configuration Table
135
GPIO Pin Configuration
136
External Interrupt/Event Lines
136
Alternate Functions (AF)
136
Input Configuration
136
Output Configuration
137
Figure 7-2. Input Configuration
137
Figure 7-3. Output Configuration
137
Analog Configuration
138
Alternate Function (AF) Configuration
138
Figure 7-4. Analog Configuration
138
Figure 7-5. Alternate Function Configuration
138
IO Pin Function Selection
139
GPIO Locking Function
139
Remapping Function I/O and Debug Configuration
140
Introduction
140
Main Features
140
JTAG/SWD Alternate Function Remapping
140
Table 7-2. Debug Interface Signals
140
ADC AF Remapping
141
Table 7-3. Debug Port Mapping
141
Table 7-4. ADC0 External Trigger Inserted Conversion AF Remapping
141
Table 7-5. ADC0 External Trigger Regular Conversion AF Remapping
141
Table 7-6. ADC1 External Trigger Inserted Conversion AF Remapping
141
Table 7-7. ADC1 External Trigger Regular Conversion AF Remapping
141
TIMER AF Remapping
142
Table 7-8. TIMER0 Alternate Function Remapping
142
Table 7-9. TIMER1 Alternate Function Remapping
142
Table 7-10. TIMER2 Alternate Function Remapping
142
Table 7-11. TIMER3 Alternate Function Remapping
142
Table 7-12. TIMER4 Alternate Function Remapping
143
Table 7-13. TIMER7 Alternate Function Remapping
143
Table 7-14. TIMER8 Alternate Function Remapping
143
Table 7-15. TIMER9 Alternate Function Remapping
143
Table 7-16. TIMER10 Alternate Function Remapping
143
USART AF Remapping
144
Table 7-17. TIMER11 Alternate Function Remapping
144
Table 7-18. TIMER12 Alternate Function Remapping
144
Table 7-19. TIMER13 Alternate Function Remapping
144
Table 7-20. USART0 Alternate Function Remapping
144
Table 7-21. USART1 Alternate Function Remapping
144
Table 7-22. USART2 Alternate Function Remapping
144
I2C AF Remapping
145
Table 7-23. UART3 Alternate Function Remapping
145
Table 7-24. USART5 Alternate Function Remapping
145
Table 7-25. UART6 Alternate Function Remapping
145
Table 7-26. I2C0 Alternate Function Remapping
145
Table 7-27. I2C1 Alternate Function Remapping
145
Table 7-28. I2C2 Alternate Function Remapping
145
SPI AF Remapping
146
CAN AF Remapping
146
Table 7-29. SPI0 Alternate Function Remapping
146
Table 7-30. SPI1/I2S1 Alternate Function Remapping
146
Table 7-31. SPI2/I2S2 Alternate Function Remapping
146
Ethernet AF Remapping
147
Table 7-32. CAN0 Alternate Function Remapping
147
Table 7-33. CAN1 Alternate Function Remapping
147
Table 7-34. ENET Alternate Function Remapping
147
DCI AF Remapping
148
TLI AF Remapping
148
Table 7-35. DCI Alternate Function Remapping
148
Table 7-36. TLI Alternate Function Remapping
148
CLK Pins AF Remapping
149
Table 7-37. OSC32 Pins Configuration
149
Table 7-38. OSC Pins Configuration 1
150
Table 7-39. OSC Pins Configuration 2
150
Register Definition
151
Port Control Register 0 (Gpiox_Ctl0, X=A
151
Port Control Register 1 (Gpiox_Ctl1, X=A
153
Port Input Status Register (Gpiox_Istat, X=A
154
Port Output Control Register (Gpiox_Octl, X=A
155
Port Bit Operate Register (Gpiox_Bop, X=A
155
Port Bit Clear Register (Gpiox_Bc, X=A
156
Port Configuration Lock Register (Gpiox_Lock, X=A
156
Event Control Register (AFIO_EC)
157
AFIO Port Configuration Register 0 (AFIO_PCF0)
158
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
162
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
163
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
165
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
166
AFIO Port Configuration Register 1 (AFIO_PCF1)
167
AFIO Port Configuration Register 2 (AFIO_PCF2)
169
AFIO Port Configuration Register 3 (AFIO_PCF3)
171
AFIO Port Configuration Register 4 (AFIO_PCF4)
175
AFIO Port Configuration Register 5 (AFIO_PCF5)
178
CRC Calculation Unit (CRC)
183
Overview
183
Characteristics
183
Figure 8-1. Block Diagram of CRC Calculation Unit
183
Function Overview
184
Register Definition
185
Data Register (CRC_DATA)
185
Free Data Register (CRC_FDATA)
185
Control Register (CRC_CTL)
186
True Random Number Generator (TRNG)
187
Overview
187
Characteristics
187
Function Overview
187
Figure 9-1. TRNG Block Diagram
187
Operation Flow
188
Error Flags
188
Register Definition
189
Control Register (TRNG_CTL)
189
Status Register (TRNG_STAT)
189
Data Register (TRNG_DATA)
190
Cryptographic Acceleration Unit (CAU)
192
Overview
192
Characteristics
192
CAU Data Type and Initialization Vectors
193
Data Type
193
Figure 10-1. DATAM no Swapping and Half-Word Swapping
193
Initialization Vectors
194
Cryptographic Acceleration Processor
194
Figure 10-2. DATAM Byte Swapping and Bit Swapping
194
Figure 10-3. CAU Diagram
194
DES/TDES Cryptographic Acceleration Processor
195
Figure 10-4. DES/TDES ECB Encryption
196
Figure 10-5. DES/TDES ECB Decryption
197
Figure 10-6. DES/TDES CBC Encryption
198
AES Cryptographic Acceleration Processor
199
Figure 10-7. DES/TDES CBC Decryption
199
Figure 10-8. AES ECB Encryption
200
Figure 10-9. AES ECB Decryption
200
Figure 10-10. AES CBC Encryption
201
Figure 10-11. AES CBC Decryption
202
Figure 10-12. Counter Block Structure
202
Figure 10-13. AES CTR Encryption/Decryption
202
Operating Modes
203
CAU DMA Interface
204
CAU Interrupts
205
CAU Suspended Mode
205
Register Definition
207
CAU Control Register (CAU_CTL)
207
CAU Status Register 0 (CAU_STAT0)
208
CAU Data Input Register (CAU_DI)
209
CAU Data Output Register (CAU_DO)
210
CAU DMA Enable Register (CAU_DMAEN)
210
CAU Interrupt Enable Register (CAU_INTEN)
211
CAU Status Register 1 (CAU_STAT1)
211
CAU Interrupt Flag Register (CAU_INTF)
212
CAU Key Registers (CAU_KEY0
212
CAU Initial Vector Registers (CAU_IV0
215
Hash Acceleration Unit (HAU)
217
Overview
217
Characteristics
217
HAU Data Type
217
Figure 11-1. DATAM no Swapping and Half-Word Swapping
218
Figure 11-2. DATAM Byte Swapping and Bit Swapping
218
HAU Core
219
Automatic Data Padding
219
Figure 11-3. HAU Block Diagram
219
Digest Computing
220
Hash Mode
221
HMAC Mode
221
HAU Interrupt
221
Register Definition
223
HAU Control Register (HAU_CTL)
223
HAU Data Input Register (HAU_DI)
224
HAU Configuration Register (HAU_CFG)
225
HAU Data Output Register (HAU_DO0
226
HAU Interrupt Enable Register (HAU_INTEN)
228
HAU Status and Interrupt Flag Register (HAU_STAT)
228
Direct Memory Access Controller (DMA)
230
Overview
230
Characteristics
230
Block Diagram
231
Function Overview
231
DMA Operation
231
Figure 12-1. Block Diagram of DMA
231
Table 12-1. DMA Transfer Operations (Normal Mode)
232
Peripheral Handshake
233
Figure 12-2. Handshake Mechanism
233
Table 12-2. DMA Transfer Operations (Full_Data Mode)
233
Arbitration
234
Address Generation
234
Circular Mode
234
Memory to Memory Mode
235
Channel Configuration
235
Interrupt
235
Table 12-3. Interrupt Events
235
DMA Request Mapping
236
Figure 12-3. DMA Interrupt Logic
236
Figure 12-4. DMA0 Request Mapping
236
Table 12-4. DMA0 Requests for each Channel
236
Table 12-5. DMA1 Requests for each Channel
236
Figure 12-5. DMA1 Request Mapping
238
Register Definition
240
Interrupt Flag Register (DMA_INTF)
240
Interrupt Flag Clear Register (DMA_INTC)
240
Channel X Control Register (Dma_Chxctl)
241
Channel X Counter Register (Dma_Chxcnt)
243
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
244
Channel X Memory Base Address Register (Dma_Chxmaddr)
244
DMA Additional Configuration Register (DMA_ACFG)
245
Debug (DBG)
246
Overview
246
JTAG/SW Characteristics
246
Switch JTAG or SW Interface
246
Pin Assignment
246
JTAG Daisy Chained Structure
247
Debug Reset
247
JEDEC-106 ID Code
247
Debug Hold Function Overview
247
Debug Support for Power Saving Mode
247
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
248
Register Definition
249
ID Code Register (DBG_ID)
249
Control Register (DBG_CTL)
249
Analog-To-Digital Converter (ADC)
253
Overview
253
Characteristics
253
Pins and Internal Signals
254
Figure 14-1. ADC Module Block Diagram
254
Table 14-1. ADC Internal Signals
254
Table 14-2. ADC Pins Definition
254
Function Overview
255
Calibration (CLB)
255
ADC Clock
256
ADCON Switch
256
Regular and Inserted Channel Groups
256
Conversion Modes
256
Figure 14-2. Single Conversion Mode
257
Figure 14-3. Continuous Conversion Mode
258
Figure 14-4. Scan Conversion Mode, Continuous Disable
259
Figure 14-5. Scan Conversion Mode, Continuous Enable
260
Figure 14-6. Discontinuous Conversion Mode
260
Inserted Channel Management
261
Figure 14-7. Auto-Insertion, CTN = 1
261
Analog Watchdog
262
Data Alignment
262
Figure 14-8. Triggered Insertion
262
Figure 14-9. Data Alignment of 12-Bit Resolution
263
Figure 14-10. Data Alignment of 10-Bit Resolution
263
Figure 14-11. Data Alignment of 8-Bit Resolution
263
Programmable Sample Time
264
External Trigger
264
Figure 14-12. Data Alignment of 6-Bit Resolution
264
Table 14-3. External Trigger for Regular Channels for ADC0 and ADC1
264
DMA Request
265
Table 14-4. External Trigger for Inserted Channels for ADC0 and ADC1
265
Table 14-5. External Trigger for Regular Channels for ADC2
265
Table 14-6. External Trigger for Inserted Channels for ADC2
265
Temperature Sensor, and Internal Reference Voltage
266
Refint
266
Programmable Resolution (DRES) - Fast Conversion Mode
266
On-Chip Hardware Oversampling
267
Figure 14-13. 20-Bit to 16-Bit Result Truncation
267
Table 14-7. T CONV Timings Depending on Resolution
267
ADC Sync Mode
268
Figure 14-14. Numerical Example with 5-Bits Shift and Rounding
268
Table 14-8. Maximum Output Results Vs N and M Grayed Values Indicates Truncation
268
Free Mode
270
Regular Parallel Mode
270
Figure 14-15. ADC Sync Block Diagram
270
Inserted Parallel Mode
271
Follow-Up Fast Mode
271
Figure 14-16. Regular Parallel Mode on 16 Channels
271
Figure 14-17. Inserted Parallel Mode on 4 Channels
271
Follow-Up Slow Mode
272
Figure 14-18. Follow-Up Fast Mode on 1 Channel in Continuous Conversion Mode
272
Trigger Rotation Mode
273
Figure 14-19. Follow-Up Slow Mode on 1 Channel
273
Figure 14-20. Trigger Rotation: Inserted Channel Group
273
Combined Regular Parallel & Inserted Parallel Mode
274
Combined Regular Parallel & Trigger Rotation Mode
274
Figure 14-21. Trigger Rotation: Inserted Channels in Discontinuous Mode
274
Figure 14-22. Regular Parallel & Trigger Rotation Mode
274
Combined Inserted Parallel & Follow-Up Mode
275
ADC Interrupts
275
Figure 14-23. Trigger Occurs During Inserted Conversion
275
Figure 14-24. Follow-Up Single Channel with Inserted Sequence CH1, CH2
275
Register Definition
276
Status Register (ADC_STAT)
276
Control Register 0 (ADC_CTL0)
277
Control Register 1 (ADC_CTL1)
279
Sample Time Register 0 (ADC_SAMPT0)
281
Sample Time Register 1 (ADC_SAMPT1)
282
Inserted Channel Data Offset Register X (Adc_Ioffx) (X=0
283
Watchdog High Threshold Register (ADC_WDHT)
284
Watchdog Low Threshold Register (ADC_WDLT)
284
Regular Sequence Register 0 (ADC_RSQ0)
285
Regular Sequence Register 1 (ADC_RSQ1)
285
Regular Sequence Register 2 (ADC_RSQ2)
286
Inserted Sequence Register (ADC_ISQ)
286
Inserted Data Register X (Adc_Idatax) (X= 0
287
Regular Data Register (ADC_RDATA)
288
Oversample Control Register (ADC_OVSAMPCTL)
288
Digital-To-Analog Converter (DAC)
291
Overview
291
Characteristics
291
Figure 15-1. DAC Block Diagram
291
Function Overview
292
DAC Enable
292
DAC Output Buffer
292
Table 15-1. DAC Pins
292
DAC Data Configuration
293
DAC Trigger
293
DAC Conversion
293
DAC Noise Wave
293
Table 15-2. External Triggers of DAC
293
DAC Output Voltage
294
Figure 15-2. DAC LFSR Algorithm
294
Figure 15-3. DAC Triangle Noise Wave
294
DMA Request
295
DAC Concurrent Conversion
295
Register Definition
296
Control Register (DAC_CTL)
296
Software Trigger Register (DAC_SWT)
298
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)
299
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)
299
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)
300
DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12DH)
300
DAC1 12-Bit Left-Aligned Data Holding Register (DAC1_L12DH)
301
DAC1 8-Bit Right-Aligned Data Holding Register (DAC1_R8DH)
301
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
302
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
302
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
303
DAC0 Data Output Register (DAC0_DO)
303
DAC1 Data Output Register (DAC1_DO)
304
Watchdog Timer (WDGT)
305
Free Watchdog Timer (FWDGT)
305
Overview
305
Charateristics
305
Function Overview
305
Figure 16-1. Free Watchdog Block Diagram
306
Table 16-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
306
Register Definition
308
Window Watchdog Timer (WWDGT)
311
Overview
311
Charateristics
311
Function Overview
311
Figure 16-2. Window Watchdog Timer Block Diagram
312
Figure 16-3. Window Watchdog Timing Diagram
313
Table 16-2. Min/Max Timeout Value at 60 Mhz
313
Register Definition
314
Real-Time Clock(RTC)
316
Overview
316
Characteristics
316
Function Overview
316
RTC Reset
317
RTC Reading
317
Figure 17-1. Block Diagram of RTC
317
RTC Configuration
318
RTC Flag Assertion
318
Register Definition
320
RTC Interrupt Enable Register(RTC_INTEN)
320
RTC Control Register(RTC_CTL)
320
RTC Prescaler High Register (RTC_PSCH)
321
RTC Prescaler Low Register(RTC_PSCL)
322
RTC Divider High Register (RTC_DIVH)
322
RTC Divider Low Register (RTC_DIVL)
322
RTC Counter High Register(RTC_CNTH)
323
RTC Counter Low Register (RTC_CNTL)
323
RTC Alarm High Register(RTC_ALRMH)
324
RTC Alarm Low Register (RTC_ALRML)
324
Timer
326
Table 18-1. Timers (Timerx) Are Divided into Five Sorts
326
Advanced Timer (Timerx, X=0, 7)
327
Overview
327
Characteristics
327
Block Diagram
328
Figure 18-1. Advanced Timer Block Diagram
328
Function Overview
330
Figure 18-2. Normal Mode, Internal Clock Divided by 1
330
Figure 18-3. Counter Timing Diagram with Prescaler Division Change from 1 to
331
Figure 18-4. Up-Counter Timechart, PSC=0/1
332
Figure 18-5. Up-Counter Timechart, Change Timerx_Car on the Go
333
Figure 18-6. Down-Counter Timechart, PSC=0/1
334
Figure 18-7. Down-Counter Timechart, Change Timerx_Car on the Go
335
Figure 18-8. Center-Aligned Counter Timechart
336
Figure 18-9. Repetition Timecart for Center-Aligned Counter
337
Figure 18-10. Repetition Timechart for Up-Counter
337
Figure 18-11. Repetition Timechart for Down-Counter
338
Figure 18-12. Input Capture Logic
339
Figure 18-13. Output-Compare under Three Modes
341
Figure 18-14. EAPWM Timechart
341
Figure 18-15. CAPWM Timechart
341
Table 18-2. Complementary Outputs Controlled by Parameters
343
Figure 18-16. Complementary Output with Dead-Time Insertion
345
Figure 18-17. Output Behavior in Response to a Break (the Break High Active)
346
Table 18-3. Counting Direction Versus Encoder Signals
346
Figure 18-18. Example of Counter Operation in Encoder Interface Mode
347
Figure 18-19. Example of Encoder Interface Mode with CI0FE0 Polarity Inverted
347
Figure 18-20. Hall Sensor Is Used to BLDC Motor
347
Figure 18-21. Hall Sensor Timing between Two Timers
349
Figure 18-22. Restart Mode
350
Table 18-4. Slave Mode Example Table
350
Figure 18-23. Pause Mode
351
Figure 18-24. Event Mode
351
Figure 18-25. Single Pulse Mode, Timerx_Chxcv = 0X04, Timerx_Car=0X60
352
Figure 18-26. Timer0 Master/Slave Mode Timer Example
352
Figure 18-27. Triggering TIMER0 with Enable Signal of TIMER2
354
Figure 18-28. Triggering TIMER0 with Update Signal of TIMER2
355
Figure 18-29. Pause TIMER0 with Enable Signal of TIMER2
356
Figure 18-30. Pause TIMER0 with O0CPREF Signal of Timer2
356
Figure 18-31. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
357
Register Definition
359
General Level0 Timer (Timerx, X=1, 2, 3, 4)
386
Overview
386
Characteristics
386
Block Diagram
386
Figure 18-32. General Level 0 Timer Block Diagram
386
Function Overview
388
Figure 18-33. Normal Mode, Internal Clock Divided by 1
388
Figure 18-34. Counter Timing Diagram with Prescaler Division Change from 1 to 2
389
Figure 18-35. Up-Counter Timechart, PSC=0/1
390
Figure 18-36. Up-Counter Timechart, Change Timerx_Car on the Go
391
Figure 18-37. Down-Counter Timechart, PSC=0/1
392
Figure 18-38. Down-Counter Timechart, Change Timerx_Car on the Go
392
Figure 18-39. Center-Aligned Counter Timechart
393
Figure 18-40. Input Capture Logic
395
Figure 18-41. Output-Compare under Three Modes
397
Figure 18-42. EAPWM Timechart
397
Figure 18-43. CAPWM Timechart
397
Table 18-5. Counting Direction Versus Encoder Signals
399
Figure 18-44. Example of Counter Operation in Encoder Interface Mode
400
Figure 18-45. Example of Encoder Interface Mode with CI0FE0 Polarity Inverted
400
Table 18-6. Slave Controller Examples
400
Figure 18-46. Restart Mode
401
Figure 18-47. Pause Mode
401
Figure 18-48. Event Mode
402
Figure 18-49. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
403
Register Definition
404
General Level1 Timer (Timerx, X=8, 11)
426
Overview
426
Characteristics
426
Block Diagram
427
Function Overview
427
Figure 18-50. General Level1 Timer Block Diagram
427
Figure 18-51. Normal Mode, Internal Clock Divided by 1
428
Figure 18-52. Counter Timing Diagram with Prescaler Division Change from 1 to 2
429
Figure 18-53. Up-Counter Timechart, PSC=0/1
430
Figure 18-54. Up-Counter Timechart, Change Timerx_Car on the Go
430
Figure 18-55. Down-Counter Timechart, PSC=0/1
431
Figure 18-56. Down-Counter Timechart, Change Timerx_Car on the Go
432
Figure 18-57. Center-Aligned Counter Timechart
433
Figure 18-58. Input Capture Logic
434
Figure 18-59. Output-Compare under Three Modes
436
Figure 18-60. EAPWM Timechart
436
Figure 18-61. CAPWM Timechart
436
Table 18-7. Slave Controller Examples
438
Figure 18-62. Restart Mode
439
Figure 18-63. Pause Mode
439
Figure 18-64. Event Mode
440
Figure 18-65. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
441
Register Definition
442
General Level2 Timer (Timerx, X=9, 10, 12, 13)
455
Overview
455
Characteristics
455
Block Diagram
455
Figure 18-66. General Level2 Timer Block Diagram
455
Function Overview
456
Figure 18-67. Normal Mode, Internal Clock Divided by 1
457
Figure 18-68. Counter Timing Diagram with Prescaler Division Change from 1 to 2
457
Figure 18-69. Up-Counter Timechart, PSC=0/1
458
Figure 18-70. Up-Counter Timechart, Change Timerx_Car on the Go
459
Figure 18-71. Down-Counter Timechart, PSC=0/1
460
Figure 18-72. Down-Counter Timechart, Change Timerx_Car on the Go
461
Figure 18-73. Center-Aligned Counter Timechart
462
Figure 18-74. Input Capture Logic
463
Figure 18-75. Output-Compare under Three Modes
465
Register Definition
467
Basic Timer (Timerx, X=5, 6)
478
Overview
478
Characteristics
478
Block Diagram
478
Figure 18-76. Basic Timer Block Diagram
478
Function Overview
479
Figure 18-77. Normal Mode, Internal Clock Divided by 1
479
Figure 18-78. Counter Timing Diagram with Prescaler Division Change from 1 to 2
480
Figure 18-79. Up-Counter Timechart, PSC=0/1
481
Figure 18-80. Up-Counter Timechart, Change Timerx_Car on the Go
481
Register Definition
483
Universal Synchronous/Asynchronous Receiver /Transmitter (USART)
488
Overview
488
Characteristics
488
Function Overview
489
Table 19-1. USART Important Pins Description
489
USART Frame Format
490
Figure 19-1. USART Module Block Diagram
490
Figure 19-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
490
Table 19-2. Stop Bits Configuration
490
Baud Rate Generation
491
USART Transmitter
491
USART Receiver
492
Figure 19-3. USART Transmit Procedure
492
Figure 19-4. Oversampling Method of a Receive Frame Bit
493
Use DMA for Data Buffer Access
494
Figure 19-5. Configuration Step When Using DMA for USART Transmission
494
Figure 19-6. Configuration Step When Using DMA for USART Reception
495
Figure 19-7. Hardware Flow Control between Two Usarts
495
Figure 19-8. Hardware Flow Control
496
Multi-Processor Communication
496
Figure 19-9. Break Frame Occurs During Idle State
497
LIN Mode
497
Figure 19-10. Break Frame Occurs During a Frame
498
Figure 19-11. Example of USART in Synchronous Mode
498
Figure 19-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
499
Figure 19-13. Irda SIR ENDEC Module
499
Figure 19-14. Irda Data Modulation
500
Half-Duplex Communication Mode
500
Figure 19-15. ISO7816-3 Frame Format
501
USART Interrupts
502
Figure 19-16. USART Interrupt Mapping Diagram
503
Table 19-3. USART Interrupt Requests
503
Status Register 0 (USART_STAT0)
504
Data Register (USART_DATA)
506
Control Register 0 (USART_CTL0)
507
Control Register 1 (USART_CTL1)
509
Control Register 2 (USART_CTL2)
510
Guard Time and Prescaler Register (USART_GP)
512
Control Register 3 (USART_CTL3)
513
Receiver Timeout Register (USART_RT)
515
Figure 20-1. I2C Module Block Diagram
517
Inter-Integrated Circuit Interface (I2C)
517
Table 20-1. Definition of I2C-Bus Terminology
518
SDA and SCL Lines
518
Figure 20-2. Data Validation
519
Figure 20-3. START and STOP Condition
519
Figure 20-4. Clock Synchronization
520
Figure 20-5. SDA Line Arbitration
520
Figure 20-6. I2C Communication Flow with 7-Bit Address
521
Figure 20-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
521
Figure 20-8. I2C Communication Flow with 10-Bit Address (Master Receive)
521
Figure 20-9. Programming Model for Slave Transmitting
524
Figure 20-10. Programming Model for Slave Receiving
525
Figure 20-11. Programming Model for Master Transmitting
527
Figure 20-12. Programming Model for Master Receiving Using Solution a
529
Figure 20-13. Programming Model for Master Receiving Using Solution B
531
Use DMA for Data Transfer
531
Packet Error Checking
532
Table 20-2. Event Status Flags
534
Table 20-3. I2C Error Flags
534
Status, Errors and Interrupts
534
Register Definition
535
Control Register 1 (I2C_CTL1)
537
Slave Address Register 0 (I2C_SADDR0)
538
Transfer Buffer Register (I2C_DATA)
539
Transfer Status Register 1 (I2C_STAT1)
541
Clock Configure Register (I2C_CKCFG)
542
Rise Time Register (I2C_RT)
543
Serial Peripheral Interface/Inter-IC Sound (SPI/I2S)
544
Figure 21-1. Block Diagram of SPI
545
Table 21-1. SPI Signal Description
545
Table 21-2. Quad-SPI Signal Description
546
Quad-SPI Configuration
546
Figure 21-2. SPI Timing Diagram in Normal Mode
547
Figure 21-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
547
NSS Function
547
Table 21-3. SPI Operation Modes
548
Figure 21-4. a Typical Full-Duplex Connection
549
Figure 21-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
549
Figure 21-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
550
Figure 21-7. a Typical Bidirectional Connection
550
Figure 21-8. Timing Diagram of Quad Write Operation in Quad-SPI Mode
553
Figure 21-9. Timing Diagram of Quad Read Operation in Quad-SPI Mode
554
DMA Function
555
Table 21-4. SPI Interrupt Requests
556
Error Conditions
556
Figure 21-10. Block Diagram of I2S
557
Figure 21-11. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
558
Figure 21-12. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
558
I2S Function Overview
558
Figure 21-13. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
559
Figure 21-14. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
559
Figure 21-15. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
559
Figure 21-16. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
559
Figure 21-17. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
560
Figure 21-18. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
560
Figure 21-19. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
560
Figure 21-20. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
560
Figure 21-21. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
560
Figure 21-22. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
561
Figure 21-23. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
561
Figure 21-24. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
561
Figure 21-25. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
561
Figure 21-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
561
Figure 21-27. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
562
Figure 21-28. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
562
Figure 21-29. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
562
Figure 21-30. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
562
Figure 21-31. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
563
Figure 21-32. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
563
Figure 21-33. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
563
Figure 21-34. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
563
Figure 21-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
563
Figure 21-36. PCM Standard Short Frame Synchronization Mode Timing Diagram
563
Figure 21-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
564
Figure 21-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
564
Figure 21-39. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
564
Figure21-40. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
564
Figure 21-41. PCM Standard Long Frame Synchronization Mode Timing Diagram
564
Figure 21-42. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
565
Figure 21-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
565
Figure 21-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
565
Figure 21-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
565
Figure 21-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
565
Figure 21-47. Block Diagram of I2S Clock Generator
566
Table 21-5. I2S Bitrate Calculation Formulas
566
Table 21-6. Audio Sampling Frequency Calculation Formulas
566
Table 21-7. Direction of I2S Interface Signals for each Operation Mode
567
Operation
567
DMA Function
570
Table 21-8. I2S Interrupt
571
Register Definition
572
Control Register 1 (SPI_CTL1)
574
Status Register (SPI_STAT)
575
Data Register (SPI_DATA)
576
CRC Polynomial Register (SPI_CRCPOLY)
577
TX CRC Register (SPI_TCRC)
578
I2S Clock Prescaler Register (SPI_I2SPSC)
580
Quad-SPI Mode Control Register (SPI_QCTL) of SPI0
581
Figure 22-1. DCI Module Block Diagram
582
Digital Camera Interface(DCI)
582
Figure 22-2. Hardware Synchronization Mode
583
Table 22-1. Pins Used by DCI
583
Signal Description
583
Figure 22-3. Hardware Synchronization Mode: JPEG Format Supporting
584
Embedded Synchronization Mode
584
Table 22-2. Memory View in Byte Padding Mode
585
Window Function
585
Table 22-3. Memory View in Half-Word Padding Mode
586
Table 22-4. Status/Error Flags
586
Interrupts
586
Register Definition
587
Status Register0 (DCI_STAT0)
588
Status Register1 (DCI_STAT1)
589
Interrupt Flag Register (DCI_INTF)
590
Interrupt Flag Clear Register (DCI_INTC)
591
Synchronization Codes Unmask Register (DCI_SCUMSK)
592
Cropping Window Size Register (DCI_CWSZ)
593
TFT-LCD Interface (TLI)
595
Figure 23-1. TLI Module Block Diagram
596
Figure 23-2. Display Timing Diagram
596
Table 23-1. Pins of Display Interface Provided by TLI
596
Signal Description
596
Pixel DMA Function
597
Table 23-2. Supported Pixel Formats
598
Figure 23-3. Block Diagram of Blending
599
Layer Configuration Reload
599
Table 23-3. Status Flags
600
Table 23-4. Error Flags
600
Dithering Function
600
Register Definition
601
Active Size Register (TLI_ASZ)
602
Control Register (TLI_CTL)
603
Reload Layer Register (TLI_RL)
604
Background Color Register (TLI_BGC)
605
Interrupt Flag Register (TLI_INTF)
606
Interrupt Flag Clear Register (TLI_INTC)
607
Current Pixel Position Register (TLI_CPPOS)
608
Layer X Control Register (Tli_Lxctl)
609
Layer X Horizontal Position Parameters Register (Tli_Lxhpos)
610
Layer X Color Key Register (Tli_Lxckey)
611
Layer X Specified Alpha Register (Tli_Lxsa)
612
Layer X Blending Register (Tli_Lxblend)
613
Layer X Frame Base Address Register (Tli_Lxfbaddr)
614
Layer X Frame Total Line Number Register (Tli_Lxftln)
615
Secure Digital Input/Output Interface (SDIO)
617
Figure 24-1 SDIO "No Response" and "No Data" Operations
618
Figure 24-2. SDIO Multiple Blocks Read Operation
619
Figure 24-3. SDIO Multiple Blocks Write Operation
619
Figure 24-4. SDIO Sequential Read Operation
619
Figure 24-5. SDIO Sequential Write Operation
619
Figure 24-6. SDIO Block Diagram
620
SDIO Function Overview
620
Table 24-1. SDIO I/O Definitions
621
AHB Interface
624
Card Function Overview
625
Figure 24-7. Command Token Format
627
Table 24-2. Command Format
627
Commands
627
Table 24-3. Card Command Classes (Cccs)
628
Table 24-4. Basic Commands (Class 0)
630
Table 24-5. Block-Oriented Read Commands (Class 2)
632
Table 24-6. Stream Read Commands (Class 1) and Stream Write Commands (Class 3)
633
Table 24-7. Block-Oriented Write Commands (Class 4)
633
Table 24-8. Erase Commands (Class 5)
634
Table 24-9. Block Oriented Write Protection Commands (Class 6)
635
Table 24-10. Lock Card (Class 7)
635
Table 24-11. Application-Specific Commands (Class 8)
636
Table 24-12. I/O Mode Commands (Class 9)
637
Table 24-13. Switch Function Commands (Class 10)
638
Figure 24-8. Response Token Format
639
Responses
639
Table 24-14. Response R1
640
Table 24-15. Response R2
640
Table 24-16. Response R3
640
Table 24-17. Response R4 for MMC
641
Table 24-18. Response R4 for SD I/O
641
Table 24-19. Response R5 for MMC
641
Table 24-20. Response R5 for SD I/O
642
Table 24-21. Response R6
642
Table 24-22. Response R7
642
Data Packets Format
642
Figure 24-9. 1-Bit Data Bus Width
643
Figure 24-10. 4-Bit Data Bus Width
643
Figure 24-11. 8-Bit Data Bus Width
643
Table 24-23. Card Status
644
Two Status Fields of the Card
644
Table 24-24. SD Status
647
Table 24-25. Performance Move Field
649
Table 24-26. AU_SIZE Field
649
Table 24-27. Maximum AU Size
649
Table 24-28. Erase Size Field
650
Table 24-29. Erase Timeout Field
650
Table 24-30. Erase Offset Field
651
Programming Sequence
651
No Data Commands
653
Single Block or Multiple Block Read
654
Stream Write and Stream Read (MMC Only)
655
Erase
657
Bus Width Selection
658
Table 24-31. Lock Card Data Structure
659
Card Lock/Unlock Operation
659
Specific Operations
661
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GigaDevice Semiconductor GD32F20 Series Hardware Development Manual (32 pages)
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
2
List of Figures
3
List of Tables
4
Introduction
5
Table 1-1. Applicable Products
5
Hardware Design
6
Power Supply
6
Backup Domain
6
VDD /VDDA Domain
7
Power Supply Design
7
Reset and Power Management
8
Clock
11
External High-Speed Crystal Oscillator Clock (HXTAL)
13
External Low-Speed Crystal Oscillator Clock (LXTAL)
15
Clock Output Capability (CKOUT)
16
HXTAL Clock Monitor (CKM)
16
Table 2-1. CKOUT0SEL[3:0] Control Bits
16
Table 2-2. CKOUT1SEL[3:0] Control Bits
16
Startup Configuration
17
Table 2-3. BOOT Mode
17
Typical Peripheral Modules
18
GPIO Circuit
18
ADC Circuit
19
Table 2-4. F ADC
19
USB Circuit
20
Standby Mode Wake-Up Circuit
21
Download and Debug Circuit
22
Table 2-5. JTAG Download Debug Interface Assignment
22
Table 2-6. SWD Download Debug Interface Assignment
23
Reference Schematic Design
25
PCB Layout Design
27
Power Supply Decoupling Capacitors
27
Clock Circuit
27
Reset Circuit
28
USB Circuit
29
Package Description
30
Table 4-1. Package Description
30
Revision History
31
Table 5-1. Revision History
31
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