Hitachi AP1 Data Book page 269

4-bit single-chip microcomputer
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--------------------------------------------------------------HD614P080S
EPROM ADDR ESS
MCU ROM ADDRESS
SOOOO
Soool
SoolF
S0020
SOO7F
sooao
S lFFF
S2oo0
S3FFF
\
0
0
0
blt4
0
0
0
bit9
Vector Address
Zero-Page Subroutine
(64 Words)
Pattern
(4096 Words)
Program
(8192 Words)
I
NOT USED
(Set to "000")
blt3
b112
bltl
bit8
blt7
bit6
bltO
lower 5 bi.t}
soooo
_ JMPl Instruction
bitS
upper 5 bit
(Jump to RESET Roullne)
JMPl Instruction
(Jump to INTo Routine)
SooOF
_ JMPl
Ins~ion
~
Soo10
(Jump to INT t Routine)
I- JMPl "'structlon
(Jump to TIMER-A Routine)
S003F
I-
~J~~~ I:aS~~~~~~B
Routine)
S0040
~
SOFFF
JMPl Instruction
r
(Jump to SERIAL Roullne)
S1OO0
,
S lFFF
Fig. 1 ROM Memory Map
SooO
RAM-mapped Registers
31
SOIF
32~-----------{~020
Memory Registers(MR)
I .\.
47
_____ ____ __ _____ __ ______
S02F
48
S030
Data
(51 2 Digits)
~:; ~------------I :~~~
Not Used
::~ I------------~ !~~~
Stack
(64 Digits)
1023
L -_ _ _ _ _ _ _ _ _ _
- J
S3FF
Interrupt Control Bits
SOOO
SOOl
S002
1-_ _ _ _ _ _ _ --._--\
S003
I-Po_rt_M.,..o,...d_e ...,Re...;;g _ _ ....;(_PM_R_)+: _W--\ S004
~Se~ria:...I~M..:.o:...de:.,:-R..:.e"-g :----.:(~SM,:.;;R..:.)+: -,-W~
SS00005
6
6
Serial Data Reg. lower (SRl) : R/W
Serial Data Reg. Upper (SRU) : R/W
S007
Timer Mode Reg. A
(TMA):
W
S008
9
Timer Mode Reg. 8
(TM8):
W
S009
10 TIMER-B
(TCBl/TlRl) : R/W
SOOA
11
(TCBU/TlRU) : R/W
SOOB
12
SOOC
Not Used
3 1 - - - - - - - - - - - - - ' SOIF
• Two registers are mapped on same address
: Read Only
W
: Write Only
R/W : Read/Write
I
Timer
I
Event Counter Blower (TCBl)
R
Timer load Reg. lower
l
Timer/Event Counter B Upper (TCBU)
R
Timer load Reg. Upper
Fig. 2 RAM Memory Map
(TlRl)
W
(TlRU)
W
SOOOO
Soool
S0002
S0003
S0004
SooOS
S0006
Soo07
S0008
S0009
SOOOA
SOOOB
SooOC
SOOOD
SOooE
SOooF
SOOA
SooB
• RAM MEMORY MAP
The MCU includes 576 digits x 4 bits RAM as the data area
and stack area. In addition to these areas, interrupt control bits
and special registers are also mapped on the RAM memory
space. RAM memory map is illustrated in Fig. 2 and described
in the follOWing paragraph.
267

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