Hitachi AP1 Data Book page 104

HMCS46C,HMCS46CL--------------------------------------------------------
• RESET FUNCTION
The reset is perfonned by setting the RESET pin to "1"
("High" level) and the HMCS46C gets into operation by setting
it to ''0'' ("Low" level); Refer to Figure 22. Moreover, the
HMCS46C has the power-on reset function (ACL; Built-in Reset
Circuit). The Built-in Reset Circuit restricts the rise condition
of the power supply; Refer to Figure 23. When the Built-in
Reset Circuit is used, RESET should be connected to GND.
HMCS46CL doesn't have the power-on reset function.
Internal state of the HMCS46C are specified as follows by
the reset function.
o
Program Counter (PC) is set to Bank 1 31 Page 3F
Address (63 Page 3F Address).
Data I/O Registers R'lO is set to "1" (Jumps to Bank 0 by
execution of LPU instruction after the reset).
o
I/RI, IIRT, I/E and CF are reset to
''0''.
o
IFO, 1Ft, and TF are set to "1".
o
Data I/O Registers (RO to RS) and Discrete I/O Latches
(Do to 015) are all set to "I".
Note that
all
the other logic blocks (the Stack Reg-
isters, the Status F/F, the accumulator, the Carry F/F,
the registers, the Timer/Counter, RAM) are not cleared
by the reset function. The user should initialize these
blocks by software. Because the Status F/F after the
reset is not defined, set the Status F/F to "0" or "1"
before the first execution of the conditional instruc-
tions (LPU, CAL and BR instructions).
(Reset State)
RESET
Vee
• HALT FUNCTION
When the HLT pin is set to ''0'' ("Low" level), the internal
clock stops and all the internal statuses (RAM, the Registers, the
Carry F/F, the Status F/F, the Program Counter, and all the
internal statuses) are held. Because all internal logic operation
stop, power consumption is reduced. There are two input/
output statuses in the Halt State. The user should specify either
"Enable" or "Disable" using a mask option at the time of order-
ingROM.
"Enable"~OutPut
....... The status before the
Halt State is held
Pull up MOS '" ON
Input ........ Independent of the Halt
State or Operating State
(Input Circuit is ON)
Since Pull up MOS is ON, Pull up MOS
current flows with output "0" ("Low"
level) in the Halt State (NMOS; ON).
When an input signal changes, transi-
tion current flows into an input circuit.
Also, current flows into Pull up MOS.
* tRST1 includes the time required from the power ON until the
operation gets into the constant state.
HLT
=
Vee
RESET-GND
O.2V
V e c - - - - - J
tRST2 is applied when the operation is in the constant state.
Figure 22 RESET Timing
4.5V
tOFF
trce
*
tOFF specifies the period when the power supply if OFF in the case that a
short break of the power supply occurs and the power supply ON/OFF is repeated.
Figure 23 Power Supply Timing for Built-in Reset Circuit
102
4.5V