Hitachi AP1 Data Book page 332

HMCS404AC------------------------------------------------------------------------
Table 27. Compare Instruction
I
~
OPERATION MNEMONIC OPERATION CODE FUNCTION STATUS
YCLE
Immediate Not Equal to Memory INEM i 0000 1 0
iJ
i2 i, io i 10M NZ 1/1
Immediate Not Equal to Memory INEMD i,d
010010 i i i i
d~
de d7 ds
d~d. ta~dl ~ i/M NZ
2/2
A Not Equal to Memory ANEM
0000000100
AIM
NZ
1/1
A Not Equal to Memory ANEMD d
~9
Je
~7 ~s ~s~. ~3
J2
~, ~o
AIM NZ
2/2
B Not Equal to Memory
BNEM 0001000100
B1'M
NZ
1/1
Y Not Equal to Immediate YNEI i 000 1 1 1
iJ
i2 i, io Yf-i NZ 1/1
Immediate Less or Equal to Memory ILEM i
o
0 0 0 1 1 iJ i2 i 1 io i;;;;M NB
1/1
Immediate Less or Equal to Memory
ILEMD i,d
~J~~7 ~5 JsJ3~1,-~
i;;;;M NB
2/2
A Less or Equal to Memory ALEM 0000010100 A;;;;M NB 1/1
A Less or Equal to Memory ALEMD d
~9JS ~7~s~5J'~3J2~' ~o
A;;;;M
NB 2/2
B Less or Equal to Memory BLEM 0011000100 B;;;;M NB 1/1
A Less or Equal to Immediate ALEI i 10101 1 iJ i2 il io A;;;;i NB
1/1
Table 28. RAM Bit Manipulation Instruction
Z
OPERATION MNEMONIC OPERATION CODE
FUNCTION STATUS
CYCLE
Set Memory Bit SEM n
00 1 00 0 0 1 n,no 1-M(n)
1/1
Set Memory Bit SEMD n,d
o
1 1 0000 1 n,no
dgdsd7 dsds d.d3d d, do
1-M(n)
2/2
Reset Memory Bit REM n 00 1 000 1 0 n,no O-M(n) 1/1
Reset Memory Bit
REMD n,d
o
1 1 0
9 9
1
9
n
100
chds d7 ds ds d. d~d2 dl do
O-M(n)
2/2
Test Memory Bit TM n 00 1 000 1 1 n,no
M(n)
1/1
Test Memory Bit
TMD n,d
q
1 1 00
q
1 1 n,no
dg ds d7 ds ds d. d3 d2 d, do
M(n)
2/2
Table 29. ROM Address Instruction
I
MNEMONIC
2
OPERATION OPERATION CODE FUNCTION STATUS
CYCL
Branch on Status 1 BR b 1 1 b7b6bsb4b3b2b,bo 1 1/1
Long Branch on Status 1 BRL
u
o
1 0 1 1 1 P3P2P1PO
1
2/2
dgda d7 dsds d.da d2dl do
Long Jump Unconditionally
JMPL u
o
1 0 1 0 1 P3P2P1PO
dgdsd7dsdsd.dad2d, do
2/2
Subroutine Jump on Status 1 CAL a
o
1 1 1 aSa4a3a2a,aO 1
1/2
Long Subroutine Jump on Status 1 CALL
u
~9
Js
~7
Js J5
~4 g:g;g,'g~
1
2/2
Table Branch TBR
P
00 1 0 1 1 P3P2P1PO 1/1
Return from Subroutine RTN 0000010000
1/3
Return from Interrupt
RTNI 0000010001 1-I/E
1/3
Table
30.
Input/Output Instruction
OPERATION MNEMONIC OPERATION CODE
FUNCTION STATUS
WORD
£c:E
Set Discrete I/O Latch SED
o
0 1 1 1 00100 1-D(Y)
1/1
Set Discrete I/O Latch Direct
SEDD m 1 0 1 1 1 0 m3m2m,mO
1-D(m)
1/1
Reset Discrete I/O Latch
RED
o
0 0 1 1 00100
O-D(Y)
1/1
Reset Discrete I/O Latch Direct REDO m
1 0 0 1 1 0 m3m2m,mO O-D(m)
1/1
Test Discrete I/O Latch
TO 001 1 1
o
000 0 D(Y)
1/1
Test Discrete I/O Latch Direct TOO m 1 0 1 0 1 0 m3m2m,mO
D(m)
1/1
Load A from R-Port Register
LAR m 1 0 0 1
o
1 m3m2m,mO R(m)-A
1/1
Load B from R-Port Register LBR m 1
o
0 1
o
0 m3m2m,mO R(m)-B
1/1
Load R-Port Register from A LRA
m 1 0 1 1 0 1 m3m2m,mO A-R(m)
1/1
Load R-Port Register from B
LRB m 1 0 1 1
o
0 m3m2m,mO
B-R(m)
1/1
Pattern Generation P
P
0 1 1 0 1 1 P3P2Pl po
1/2
330