Hitachi AP1 Data Book page 370

HMCS404CL------------------------------------------------------------------------
Table 27. Compare Instruction
OPERATION
I WZRD
MNEMONIC OPERATION CODE FUNCTION STATUS
YCLE
Immediate Not Equal to Memory INEM i
o
0 0 0 1 0 i3 i2 i 1 io i #M NZ 1/1
Immediate Not Equal to Memory INEMD i.d
01
9 9
1 0 i i i i
i 1M
9.HIs.9z
ds ds d.
~3 ~2
d,
~
A Not Equal to Memory ANEM 0000000100
A*M
A Not Equal to Memory ANEMD d
~9
Je
~z ~6 ~& ~4 ~3 Jl"~o
AIM
NZ~2/2
NZ 1/1
~--------~----
NZ 2/2
B Not Equal to Memory BNEM 0001000100 BIM NZ 1/1
Y Not Equal to Immediate YNEI i 0001 1 1 i3 i2;' io Yofi NZ 1/1
Immediate Less or Equal to Memory ILEM i
o
0 0 0 1 1 i3 i2 ;, io i~M NB 1/1
Immediate Less or Equal to Memory ILEMD i.d
~9
Je
~z ~J~ .J~~l~l.~'t~O
i
~M
NB 2/2
A Less or Equal to Memory ALEM 0000010100 A~M NB 1/1
A Less or Equal to Memory ALEMD d
o
1 000 1 0 1 0-0
A~M
dsdBdldsdsd4d ~ _
B Less or Equal to Memory BLEM
0011000100
B~M
A Less or Equal to Immediate ALEI i 10101 1 iJ b il io A~ i
~~
) NB
I
1/1
I
NB 2/2
Table 28. RAM Bit Manipulation Instruction
OPERATION MNEMONIC OPERATION CODE
FUNCTION
~
STATUS
CYCL
Set Memory Bit
SEM n
00 1 0000 1 nIno 1--M(n) 1/1
Set Memory Bit
SEMD n,d
~91s11~S~S~4~312~~~g
1--M(n)
2/2
Reset Memory Bit REM n
00 1 000 1 0 n,no O--M(n)
1/1
Reset Memory Bit REMD n,d
~9dB
dl
~s ~s ~4
J3
~2
a, '
gg O--M(n)
2/2
Test Memory Bit TM n
00 1 000 1 1 n,no M(n)
1/1
Test Memory Bit TMD n,d
~s ~S~I~6~5~4 ~3 ~2 ~~~~
M(n)
2/2
Table 29. ROM Address Instruction
I
MNEMONIC
WZ
OPERATION OPERATION CODE FUNCTION STATUS
CYCL
Branch on Status 1 BR b
1 1 b7babsb4bJb2b,bo
1
1/1
Long Branch on Status 1 BRL u
~B~8~1 ~s ~s ~4 ~:~;~,'~~
1
2/2
Long Jump Unconditionally
JMPL u
o
1 0 1
q
1
~3~2P'IPO
ds dB dl dB ds d4 d3 d2 d, do
2/2
Subroutine Jump on Status 1 CAL a
o
1 1 1 a5a4a3a2a,aO 1
1/2
Long Subroutine Jump on Status 1 CALL u
~9
d s
~l
ds ds
~4 ~:~:~,'~~
1
2/2
Table Branch TBR p
o
0 1 0 1 1 P3P2P1PO 1/1
Return from Subroutine RTN 0000010000
1/3
Return from Interrupt RTNI 0000010001
1--I/E 1/3
Table 30. I nput/Output Instruction
OPERATION MNEMONIC
OPERATION CODE FUNCTION
WORD
STATUS
~E
Set Discrete I/O Latch SED 0 0 1 1 1 00100 1--D(Y)
1/1
Set Discrete I/O Latch Direct SEDD m 1 0 1 1 1 a m3m2m,mO
1--D(m)
1/1
Reset Discrete I/O Latch RED
000 1 1 001
o
0
a--D(Y)
1/1
Reset Discrete I/O Latch Direct REDO m 1 0 0 1 1 0 m3m2m,mO
O--D(m) 1/1
Test Discrete I/O Latch TO
o
0 1 1 1
o
0 0 0 0 D(Y)
1/1
Test Discrete I/O Latch Direct TOO
m 1
o
1 a 1 0 m3m2m,mO D(m)
1/1
Load A from R-Port Register
LAR m 1
o
a 1 0 1 m3m2m,mO R(m)->A
1/1
Load B from R-Port Register LBR
m
1 0 0 1
o
0 m3m2mlmO R(m)--B
1/1
Load R-Port Register from A LRA
m 1 0 1 1 0 1 m3m2m,mO A--R(m)
1/1
Load R-Port Register from B LRB
m 1 0 1 1
o
0 m3m2m,mO B->R(m)
1/1
Pattern Generation P p
a 1 1 a 1 1 P3P2Pl po
1/2
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