Hitachi AP1 Data Book page 99

------------------------------------------------------HMCS46C,HMCS46Cl
• REGISTER
The HMCS46C has eight 4-bit registers and two I-bit registers
available to the programmer. The I-bit registers are the Carry
F/F and the Status F/F. They are explained in the following
paragraphs.
• Status F/F (S)
The Status F /F latches the result of logical or arithmetic
operations (Not Zero, Overflow) and bit test operations. The
Status F/F affects conditional instructions (LPU, BR and CAL
instructions). These instructions are executed only when the
Status F /F is "1". If it is "0", these instructions are skipped and
the Status F/F becomes "1".
• Accumulator (A; A Register) and Carry F/F (C)
The result of the Arithmetic Logic Unit (ALU) operation (4
bits) and the overflow of the ALU are loaded into the accumula-
tor and the Carry F/F. The Carry F/F can be set, reset or tested.
Combination of the accumulator and the Carry F/F can be right
or left rotated. The accumulator is the main register for ALU
operation and the Carry F /F is used to store the overflow gener-
ated by ALU operation when the calculation of two or more
digits (4 bits/digit) is performed.
• 8 Register (8)
The result of ALU operation (4 bits) is loaded into this
register. The B register is used as a sub-accumulator to stack
data temporarily and also used as a counter.
• X Register (X)
The result of ALU operation (4 bits) is loaded into this
register. The X register has exchangeability for the SPX register.
The X register addresses the RAM file.
• SPX Register (SPX)
The SPX register has exchangeability for the X register.
The SPX register is used to stack the X register and expand
the addressing system of RAM in combination with the X
register.
• Y Register (Y)
The result of ALU operation (4 bits) is loaded into this
register. The Y register has exchangeability for the Spy register.
The Y register can calculate itself simultaneously with transfer-
ring data by the bus lines, which is usable for the calculation of
two or more digits (4 bits/digit). The Y register addresses the
RAM digit and I-bit Discrete I/O.
• Spy Register (Spy)
The Spy register has exchangeability for the Y register. The
Spy register
is
used to stack the Y register and expand the
addressing system of RAM and I-bit Discrete I/O in' combina-
tion with the Y register.
The Data I/O Registers R4 and R5, which are not connected
to the LSI pin; can be used for general purpose registers.
• R4 Register (R4)
The contents of the accumulator and the B register are trans-
ferred by LRA and LRB instructions, respectively. The con-
tents of the R4 register are sent to the accumulator and the B
register by LAR and LBR instructions, respectively.
• R5 Register (R5)
The contents of the accumulator and the B register are trans-
ferred by LRA and LRB instructions, respectively. The contents
of the R5 register are sent to the accumulator and the B register,
respectively.
• INPUT/OUTPUT
• 4-bit Data Input/Output Common Channel (R)
The HMCS46C has four 4-bit Data I/O Common Channels
(RO, RI, R2 and R3).
The 4-bit registers (Data I/O Register) are attached to these
channels.
Each channel is directly addressed by the operand p of
input/output instruction.
The data
is
transferred from the accumulator and the B
register to the Data I/O Registers RO to R3 via the bus lines.
Pattern instruction enables the patterns of ROM to be loaded
into the Data I/O Registers R2 and R3.
Input, instruction enables the 4-bit data to be sent to the
accumulator and the B register from RO to R3. Note that, since
the Data I/O Register's output is directly connected to the pin
even during execution of input instruction, the input data is
wired logic of the Data I/O Register's output and the pin input.
Therefore, the Data I/O Register should be set to 15 (all bits
of the Data I/O Register is "1") not to affect the pin input
before execution of input instruction, and Open Drain or With
Pull up MOS should be specified for the I/O configuration of
these pins.
97
The block diagram is shown in Figure 14. The I/O timing is
shown in Figure 15.
• 1-bit Discrete Input/Output Common Terminal (D)
The HMCS46C has 16 I-bit Discrete I/O Common Terminals.
The I-bit Discrete I/O Common Terminal consists of a I-bit
latch and an I/O common pin.
The I-bit Discrete I/O is addressed by the Y register. The
addressed latch can be set or reset by output instruction and
"0" and "1" level can be tested with the addressed pin by input
instruction.
Note that, since the latch output is directly connected to the
pin even during execution of input instruction, the input data
is wired logic of the latch's output and the pin input. Therefore,
the latch should be set to "1" not to affect the pin input before
execution of input instruction and Open Drain or With Pull up
MOS should be specified for the I/O configuration of this pin.
The Do to D3 terminal are also addressed directly by the
operand n of input/output instruction and can be set or reset.
The block diagram is shown in Figure 16 and the I/O timing is
shown in Figure 17.
• I/O Configuration
The I/O configuration of each pin can be specified among
Open Drain, With Pull up MOS and CMOS using a mask option
as shown in Figure 18.