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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - L C D - I I I
• Extension of Display Function
Number of display digits can be increased by externally con-
necting an LCD driver LSI 8044100H to the LCD-III.
The HD44IooH consists of shift registers and latch and
liquid crystal drive circuit. When connected with the LCD-III,
the 8044IooH is used as a circuit for segment. In the LCD-III,
display data for 128 segments is sent to the 32-bit shift register
from RAM constantly. When R42 is set to "0", the RI channel
outputs the 32nd stage output D of the shift register, shift
clock CL2, latch clock CLI and AC signal M. Therefore, up to
96 segment terminals from SEG33 to SEG·i28 can be added by
directly connecting the HD44looH.
• RESET FUNCTION
The LCD·III can be reset by setting the reset terminal to "1"
HLT
=
vee
RESET .. GND
Vee
4.6V
O.2V
(High) and its operation starts when the terminal is set to
"0" (Low). Also an automatic reset function (internal reset
circuit) that operates when power is turned on is provided.
However, note that in the case of internal reset circuit the
rise time of a power supply has a restriction. The LCD-III inter-
nal state is set as follows by the reset function:
The program counter is set to Address 3F of Page 31.
IR/I, IR/T, I/E and CF are reset to "0".
IFO, IFI and TF are preset to "1".
All bits of data I/O register, discrete I/O output latches
(Rl, R2, R3 and Do to DIS) are preset to "1".
Liquid crystal display .. All bits of display mode setting
registers (data I/O registers) R4,
RS and R6 are preset to "1".
RAM data is not retained after reset.
(NOTE) tOFF lpeelfl .. the period during the power lupply II OFF. when
• Ihort bruk occurl or power lupply ON/OFF il r.pelted.
Figure 26 Power Supply Condition Using the Built-in Reset Circuit
m::T .. Vee
Vee - - - - "
tfRST
trRST
tfRST
(NOTE) 1. tRST. Includ .. the time required from the pow.r ON until
the operltlon getllnto the conltlnt nltt.
2. tRST
2
II .pplled wh.n the operltlon II In the conlt.nt It.tt.
Figure 27 Reset Input Condition Using an External Reset Circuit
• HALT FUNCTION
The LCD-III is provided with half function. The halt function
reduces power consumption in the halt state by temporarily
stopping all status including RAM. When halt is released,
operation restarts from the state immediately before the halt.
(Caution at the halt time)
When the LCD·III goes into halt state, segment terminals
(SEG
1
to SEG
32 )
and common terminals (COM I to
COM.) become the same potential and display goes out.
However, in order to reduce power consumption during
halt, disconnect the voltage applied to liquid crystal
power supply V 3. Since there are dividing resistors among
V I, V
2 ,
and Va, current of up to
SOItA
flows if voltage is
applied between VCC and Va in the same way as normal
operation.
167
The user can select one of the following I/O status at the
time of halt based on the "MASK OPTION LIST" when
ordering ROM:
i) All I/O status is kept as the state immediately before
the halt.
ii) All I/O status is held in the high impedance state (both
PMOS and NMOS are off, and pull.up MOS is off).
There are the following two types of halt:
1) External Halt (Halt state generated by using
HIT
terminal)
All operations stop when the
m:T
terminal is set to the
''0''
level (Low). When the
HI:T
terminal is set to the
"1" level (High), operation restarts from the state im·
mediately before the halt.
2) Internal Halt (Halt state generated by programs)
The user can select aVailability of internal halt at the time
of ROM order based on the "MASK OPTION LIST".
When internal halt is selected, timer crystal must be at-
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