Table of Contents
Advertisement
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - L C D - I I I
Do to D
13
are discrete I/O's of common for input and
output,
D14
and
Dl5
require a mask option in 3 types.
When the crystal oscillation for timer is selected and the
latches of
D14
and
D 1s
are not connected to the terminals,
D14
and
Dl5
can
be
used as I-bit general purpose registers
that can
be
set, reset and tested. Furthennore, if there
is
internal halt mode. latch of D
15
is used as a register for
internal halt mode specially.
In such case, since D
15
means internal halt state and DiS
=
"1" means operating state, LSI can be in internal halt state by
resetting
D1s
using an instruction. The pre scaler keeps its
operation in internal halt state. Therefore,
Dl5
may be set by
overflow output pulse from the prescaler to return to operat-
ing state. Refer to HALT FUNCTION for details of internal
halt mode.
Table 3 Mask Option of D
14
/XO and Du/XI Terminals
Mask Option
a
b
c
d
Function of
Function of D
14
/XO
D
14
/XO and DiS/XI
and Du/Xllatch
1
Unselectable crystal oscillation for
short
open
discrete I/O
Output Latch
timer (no internal halt)
(common terminal)
2
with internal
1-bit register
Selectable crystal
halt
open
short
Crystal
-
Circuit
oscillation for
open
short
0
14 ;
'-bit register
3
timer
no internal halt
Connecting
0
15 ;
register for
Terminal
internal halt
(NOTE)
Ulen
C3"I
specify thil mesic option in "The format of I/O channell" at ROM ordar.
Discrete I/O is addressed by Y register, and the set/reset
instruction
is
executed for the addressed latch. "0" and "1"
level can be tested with the addressed terminal and I-bit register
against the I/O common pins and I-bit register. The test
is
performed with the wired logic of the output latch and the pin
SED, RED SEDD, [
REDO Inltruc-
tlon
TO Instruction [
-
o
I st
t'
C Ie
j'
na n rue Ion ye . ,
On SetlRaset
Instruction
Dn(LSI pin)
X
input. Therefore, in the case of the I/O common pins, the
output latch should be in the
high
impedance state when the
test instruction
is
executed. In order to test the pin input, it
is
necessary the state that the output latch should not affect
the pin input.
On Test
~
Instruction
JL
~
On Sampling
Pulle
Figure 9 Timing Chart of Discrete I/O
• Data I/O (R T.minaU
Table 4 Data I/O for the LCD-III
I/O common channel
R 1, R2 (2 channell)
Input channel
RO
C1
channel)
Output channel
R3
C1
channal)
Total
4 channels
(NOTE) In addition to the abollll, R4, R5 and R6 ara providad as
register letting liquid crystal dilplay mode. In thasa registen,
there il no terminal and exists only data I/O register each
which controll liquid crystal dilplay mode. Data il transferred
to R4, R5 and R6
by
LRA or LRB instructlon,l8me as data
transfar to
data
I/O registen of R1, R2 and R3. For dataill of
R4, R5and RS, refer to LIQUID CRYSTAL DISPLAY.
4-bit register (data I/O register) each
is
attached to an I/O
common channel and output channel. No register is attached
to input channel. Addressing to all channels
is
perfonned by
programs (addressed by operands in instructions).
Figure 10 shows the block diagram of each channel.
153
Advertisement
Table of Contents
