Motorola DigitalDNA MPC180E User Manual page 20

Signal Descriptions
Signal Pin
name locations
TA 61
PSDVAL 82
RESET 52
CONFIG 57
ENDIAN 40
IRQ 85
NC 26, 27, 49,
50, 51, 76,
100
DREQ1 83
DREQ2 84
CLK 59
TCK 47
TDI 48
TDO 44
TMS 46
TRSTB 45
2-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 2-1. Pin Descriptions (Continued)
Signal
type
O Transfer Acknowledge: This signal is asserted by the MPC180E when a
successful read or write has occurred.
I Data valid: This active low signal is ignored when CONFIG=0 (MPC860
Mode), but is active in MPC8260 Mode. The assertion of PSDVAL indicates
that a data beat is valid on the data bus.
Miscellaneous pins
I Reset: asynchronous reset signal for initializing the chip to a known state. It
is highly recommended that this signal be connected to a dual
hardware/software reset function. Thus, the system designer can reset the
MPC180E chip with optimal flexibility.
I Configuration: input that indicates whether the interface is to an MPC860 or
MPC8260
1 = 8260 interface
0 = 860 interface
I Endian: active high for big endian mode. Low for little endian mode
(MPC860 only).
1 = big endian
0 = little endian
O Interrupt Request: interrupt line that signifies that one or more EU modules
has asserted its IRQ hardware interrupt.
— No connection to the pin
DMA Hardware Handshake pins
O DMA Request 1: active low signal which indicates that either the input or
output buffer is requesting data transfer by the host or DMA controller.
DREQ1 and DREQ2 are each programmable to refer to the MPC180E chip
input buffer or output buffer. This signal is designed to interoperate with a
PowerQUICC IDMA channel.
O DMA request 2: active low signal which indicates that either the input or
output buffer is requesting data transfer by the host or DMA controller.
DREQ1 and DREQ2 are each programmable to refer to the MPC180E Chip
input buffer or output buffer. This signal is designed to interoperate with a
PowerQUICC IDMA channel.
Clock
I Master clock input
Test
I JTAG test clock
I JTAG test data input
I JTAG test data output
I JTAG test mode select
I JTAG test reset
MPC180E Security Processor User's Manual
Description