Architectural Overview - Motorola DigitalDNA MPC180E User Manual

EEPROM
SDRAM
DIMMs
Figure 1-2. Typical MPC8260 System Example

1.3 Architectural Overview

Figure 1-3 shows a simplified block diagram of MPC180E internal architecture. The
External Bus Interface (EBI) module is designed to interface gluelessly to the
PowerQUICC and PowerQUICC II and to translate the processor core bus timing to a
simple read/write interface for the execution units (EU). The EBI also decodes the
addresses to select the appropriate EU. The EBI contains a 4096 bit input buffer and a 4096
bit output buffer. These FIFOs are used to maximize throughput and reduce the data
management required by the host processor. MPC180E functions are utilized using two
modes: open address mode or FIFO mode.
• Open address mode—Any address in the MPC180E address map is available for use
by the host processor. This mode is used for direct writes to set up the MPC180E
control registers and can be used for data transfers to and from the MPC180E.
• FIFO mode—The MPC180E will accept large data transfers into the input buffer
and return burst data through the output buffer. Up to 4Kb data transfers are possible
through the use of the FIFOs. The MPC180E manages data movement from the
Input FIFO through the execution Units and out to the Output FIFO without host
CPU intervention.
Figure 1-3 shows a simplified block diagram of the MPC180E's internal architecture.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
60x Bus
MPC8260
SDRAM
I/O or Network
Interface
Chapter 1. Overview
Architectural Overview
MPC180E
Local Bus
SDRAM
1-3