Operation - Rabbit 6000 User Manual

3.3 Operation

Pulling the /RESET pin low will initialize everything in the Rabbit 6000 except for the real-time clock reg-
isters, the 32K battery-backed RAM and the onchip-encryption RAM. The reset of the Rabbit 6000 is
delayed until any write cycles in progress are completed; the reset takes effect as soon as no write cycles
are occurring. The reset sequence requires a minimum of 128 cycles of the main clock to complete in
either case.
During reset, the impedance of the /CS1 pin is high and all other memory and I/O control signals are held
high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the
VBATIO pin (which powers /CS1). In this case, a pullup resistor is required on /CS1 to keep the RAM
deselected during powerdown. The RESOUT pin, which is powered by the backup battery, is high during
reset and powerdown as long as VBAT and VBATIO are present, but low at all other times, and can be
used to control an external power switch to disconnect VDDIO from VBATIO when the main power
source is removed.
Table 3-1 lists the condition of the processor after reset takes place. The state of all registers after reset is
provided in the chapter describing the specific peripheral.
CPU Clock,
Peripheral Clock
Clock Doubler,
Clock Dither
Memory Bank 0
Control Register
Memory Advanced
Control Register
CPU Registers:
PC, SP, IIR, EIR,
HTR
Interrupt Priority
(IP Register)
Watchdog Timer
Secondary
Watchdog Timer
Rabbit 6000 User's Manual
Table 3-1. Rabbit 6000 Condition After Reset
Function
digi.com
Operation After Reset
Divide-by-8 mode
Disabled
/CS0, /OE0, write-protected,
4 wait states
8-bit interface
0x0000
0xFF (Priority 3)
Enabled (2 seconds)
Disabled
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