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Rabbit 2000 Reference Manual

Instruction reference manual
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Rabbit 2000 /3000 Microprocessor
Instruction Reference Manual
019–0098 C • 020416
This manual (or an even more up-to-date revision) is available for free download
at the Rabbit website: www.rabbitsemiconductor.com

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  • Page 1 Rabbit 2000 /3000 Microprocessor Instruction Reference Manual 019–0098 C • 020416 This manual (or an even more up-to-date revision) is available for free download at the Rabbit website: www.rabbitsemiconductor.com...
  • Page 2 Rabbit 2000/3000 Microprocessor...

  • Page 3: Table Of Contents

    Table of Contents 1. Alphabetical Listing of Instructions ........1 2.
  • Page 4 Rabbit 2000 Microprocessor...

  • Page 5: Alphabetical Listing Of Instructions

    1. Alphabetical Listing of Instructions ......50 LD A,EIR ......50 LD A,IIR ......14 ........29 ADC A,n DEC IX ......50 LD A,XPC ......14 ........29 ADC A,r DEC IY ......49 LD A,(BC) ......13 ........29 ADC A,(HL) DEC r ......49 LD A,(DE) ......13 .........30 ADC A,(IX+d) DEC ss ......49...
  • Page 6 RR (IX+d) ......106 XOR (HL) ........72 ......87 OR n RR (IY+d) .......106 XOR (IX+d) ........72 ........91 OR r RRC r .......106 XOR (IY+d) .......70 ......90 OR (HL) RRC (HL) ......70 ......90 OR (IX+d) RRC (IX+d) ......70 OR (IY+d) Rabbit 2000/3000 Microprocessor...

  • Page 7: Instructions Listed By Group

    2. Instructions Listed by Group A. Load Immediate Data LD HL,(SP+n) ......54 LD IX,(SP+n) ......55 LD dd,mn .
  • Page 8 ..... . .13 ADC A,(IY+d) RES b,(IY+d) ......77 Rabbit 2000/3000 Microprocessor...
  • Page 9 RES b,r ....... . . 78 SRA r ........101 SET b,(HL) .
  • Page 10 LDP HL,(IX) ......65 LDP HL,(IY) ......65 Rabbit 2000/3000 Microprocessor...

  • Page 11: Document Conventions

    The number of clocks instructions take follows a general patern. There are several Rabbit instructions that do not adhere to this pattern. Some instructions take more clocks and some have been enhanced to take fewer clocks.
  • Page 12 LV flag contains logical check result LV flag set on arithmetic overflow result LV flag is cleared LV flag is affected • • Carry flag is affected Carry flag is not affected Carry flag is cleared Carry flag is set Rabbit 2000/3000 Microprocessor...
  • Page 13 Document Symbols Key Table 5: Symbols Rabbit Z180 Meaning Bit select (000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7) Condition code select (00 = NZ, 01 = Z, 10 = NC, 11 = C) 7-bit (signed) displacement.
  • Page 14 L/V=0 For arithmentic operations, No Overflow L/V=1 For logic operations, Logic One (one or more of the four most signif- icant bits of the result are one) L/V=1 For arithmentic operations, Overflow Rabbit 2000/3000 Microprocessor...

  • Page 15: Processor Registers

    4. Processor Registers Instruction Reference Manual...
  • Page 16 Rabbit 2000/3000 Microprocessor...

  • Page 17: Opcode Descriptions

    5. OpCode Descriptions ADC A,(HL) ADC A,(IX+d) ADC A,(IY+d) Opcode Instruction Clocks Operation ADC A,(HL) 5 (2,1,2) A= A + (HL) + CF DD 8E d ADC A,(IX+d) 9 (2,2,2,1,2) A= A + (IX+d) + CF FD 8E d ADC A,(IY+d) 9 (2,2,2,1,2) A= A + (IY+d) + CF Flags...
  • Page 18 The data in the Accumulator is summed with the Carry Flag, CF, and with the data in register r (any of the registers A, B, C, D, E, H, or L). The result is stored in the Accumulator. Rabbit 2000/3000 Microprocessor...

  • Page 19: Adc Hl,Ss

    ADC HL,ss Opcode Instruction Clocks Operation —— ADC HL,ss 4 (2,2) HL = HL + ss + CF ED 4A ADC HL,BC 4 (2,2) HL = HL + BC + CF ED 5A ADC HL,DE 4 (2,2) HL = HL + DE + CF ED 6A ADC HL,HL 4 (2,2)
  • Page 20 • • • • Description The data in the Accumulator is summed with the data in register r (any of the registers A, B, C, D, E, H, or L). The result is stored in the Accumulator. Rabbit 2000/3000 Microprocessor...

  • Page 21: Add Hl,Ss

    ADD HL,ss Opcode Instruction Clocks Operation —— ADD HL,ss HL = HL + ss ADD HL,BC HL = HL + BC ADD HL,DE HL = HL + DE ADD HL,HL HL = HL + HL ADD HL,SP HL = HL + SP Flags ALTD •...

  • Page 22: Add Ix,Xx

    • • Description The data in the Stack Pointer register is summed with the 7-bit signed displacement d, and then stored in SP. This instruction is implemented for the Rabbit and is not available for the Z180. Rabbit 2000/3000 Microprocessor...

  • Page 23: Altd

    This is an instruction prefix. Causes the instruction immediately following to affect the alternate flags, or use the alternate registers for the destination of the data, or both. For some instructions ALTD causes special alternate register uses, unique to that instruction. This instruction is implemented for the Rabbit and is not available for the Z180...

  • Page 24: And (Hl)

    If the byte in the Accumulator contains the bits 1011 1100 and the byte at memory location HL contains the bits 1101 0101, then the execution of the instruction: AND (HL) would result in the byte in the Accumulator becoming 1001 0100. Rabbit 2000/3000 Microprocessor...

  • Page 25: And Hl,De

    The result is stored in HL. This instruction is implemented for the Rabbit and is not available for the Z180.
  • Page 26 A, B, C, D, E, H, or L). The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes are compared, etc.) and the associated bit in the result byte is set only if both the compared bits are set. The result is stored in the Accumulator. Rabbit 2000/3000 Microprocessor...

  • Page 27: Bit B,(Hl)

    BIT b,(HL) BIT b,(IX+d) BIT b,(IY+d) Opcode Instruction Clocks Operation —— BIT b,(HL) 7 (2,2,1,2) (HL) & bit CB 46 BIT 0,(HL) 7 (2,2,1,2) (HL) & bit 0 CB 4E BIT 1,(HL) 7 (2,2,1,2) (HL) & bit 1 CB 56 BIT 2,(HL) 7 (2,2,1,2) (HL) &...
  • Page 28 ALTD • • • • Description If the data in word register HL does not equal zero, then it is set to 1. This instruction is implemented for the Rabbit and is not available for the Z180. Rabbit 2000/3000 Microprocessor...
  • Page 29 • Description If the data in index register IX or IY does not equal zero, then that register is set to 1. These instructions are implemented for the Rabbit and are not available for the Z180. CALL mn Opcode Instruction...

  • Page 30: Cp (Ix+D)

    Sign Flag and the Carry Flag are set. If they are equal, the Zero Flag is set. If the data is greater than the data in the Accumulator, then the Sign, Carry, and Zero Flags are reset. This operation does not affect the data in the Accumulator. Rabbit 2000/3000 Microprocessor...
  • Page 31 CP n Opcode Instruction Clocks Operation FE n CP n 4 (2,2) A - n Flags ALTD • • • • Description Compares the data in the Accumulator with an 8-bit constant n. This compare is accomplished by subtracting n from the Accumulator. If the value of the data in the Accumulator is less than the value of n, then the Sign Flag and the Carry Flag are set.

  • Page 32: Dec (Hl)

    Decrements the byte whose address is: • in word register HL, or • the data in index register IX plus a displacement value d, or • the data in index register IY plus a displacement value d. Rabbit 2000/3000 Microprocessor...
  • Page 33 DEC IX DEC IY Opcode Instruction Clocks Operation DD 2B DEC IX 4 (2,2) IX = IX - 1 FD 2B DEC IY 4(2,2) IY = IY - 1 Flags ALTD Description Decrements the data in index register IX or IY. DEC r Opcode Instruction...
  • Page 34 B does not equal 0, it adds the 8-bit signed constant e to the Program Counter. Two is subtracted from the value e so the instruction jumps from the current instruction and not the following instruction. Rabbit 2000/3000 Microprocessor...

  • Page 35: Ex (Sp),Hl

    EX (SP),HL Opcode Instruction Clocks Operation H <−> (SP+1); L <−> (SP) ED 54 EX (SP),HL 15 (2,2,1,2,2,3,3) Flags ALTD • Description Exchanges the byte in the register H with the data whose address is the data in the Stack Pointer register plus 1;...

  • Page 36: Ex Af,Af

    EX DE,HL exchanges the data in word register DE with the data in word register HL. If the ALTD instruction is present then the data in DE is exchanged with the data in the alternate word register HL'. This instruction is implemented for the Rabbit and is not available for the Z180. •...

  • Page 37: Inc (Hl)

    Opcode Instruction Clocks Operation BC <−> BC'; DE <−> DE'; HL <−> HL' Flags ALTD Description Exchanges the data in word registers BC, DE, and HL, with the data in their respective alternate word regis- ters BC', DE', and HL'. INC (HL) INC (IX+d) INC (IY+d)
  • Page 38 H = H + 1 INC L L = L + 1 Flags ALTD • • • • Description Increments the data in the register r (any of the registers A, B, C, D, E, H, or L). Rabbit 2000/3000 Microprocessor...
  • Page 39 INC ss Opcode Instruction Clocks Operation —— INC ss ss = ss + 1 INC BC BC = BC + 1 INC DE DE = DE + 1 INC HL HL = HL + 1 INC SP SP = SP + 1 Flags ALTD •...
  • Page 40 I/O operations and fifteen wait states are added for I/O accesses. WARNING: If an I/O prefixed instruction is immediately followed by one of these 12 special one byte memory access instructions, a bug in the Rabbit 2000 causes I/O access to occur instead of memory access: ADC A,(HL)

  • Page 41: Ipset

    The Interrupt Priority Register, IP is an 8-bit register that forms a stack of the current priority and the other previous 3 priorities. IPSET 0 forms the lowest priority; IPSET 3 forms the highest priority. These instruc- tions are privileged. They are implemented for the Rabbit and are not available for the Z180. •...

  • Page 42: Ipres

    The IPRES instruction rotates the contents of the Interrupt Priority Register 2-bits to the right, replacing the current priority with the previous priority. It is impossible to interrupt during the execution of this instruction. This instruction is privileged. It is implemented for the Rabbit and is not available for the Z180. Example...
  • Page 43 JP (HL) JP (IX) JP (IY) JP mn Opcode Instruction Clocks Operation JP (HL) 4 (2,2) PC = HL DD E9 JP (IX) 6 (2,2,2) PC = IX FD E9 JP (IY) 6 (2,2,2) PC = IY C3 n m JP mn 7 (2,2,2,1) PC = mn...
  • Page 44 The condition f is one of the following: NZ, zero flag not set; Z, zero flag set; NC, carry flag not set; C, carry flag set; LZ, Logical/Overflow flag is not set; LO, Logical/Overflow flag is set; P, sign flag not set; M, sign flag set. This instruction recognizes labels when used in the Dynamic C assembler. Rabbit 2000/3000 Microprocessor...
  • Page 45 JR cc,e Opcode Instruction Clocks Operation —— JR cc,e 5 (2,2,1) if {cc} PC = PC + e 20 e-2 JR NZ,e 5 (2,2,1) if {NZ} PC = PC + e 28 e-2 JR Z,e 5 (2,2,1) if {Z} PC = PC + e 30 e-2 JR NC,e 5 (2,2,1)

  • Page 46: Lcall X,Mn

    The value mn must be in the range E000–FFFF. This instruction is implemented for the Rabbit and is not available for the Z180. Alternate Forms The Dynamic C assembler recognizes several other forms of this instruction.

  • Page 47: Ld (Bc),A

    LD (BC),A LD (DE),A LD (HL),n LD (HL),r Opcode Instruction Clocks Operation LD (BC),A 7 (2,2,3) (BC) = A LD (DE),A 7 (2,2,3) (DE) = A 36 n LD (HL),n 7 (2,2,3) (HL) = n —— LD (HL),r 6 (2,1,3) (HL) = r LD (HL),A 6 (2,1,3)

  • Page 48: Ld (Hl+D),Hl

    HL and a displacement value d. Then, loads the data in register H into the memory location whose address is the sum of the data in word register HL and a displacement value d plus 1. This instruction is implemented for the Rabbit and is not available for the Z180. Rabbit 2000/3000 Microprocessor...

  • Page 49: Ld (Ix+D),N

    IX and a displacement value d. Then, loads the data in register H into the memory location whose address is the sum of the data in index register IX and a dis- placement value d plus 1. This instruction is implemented for the Rabbit and is not available for the Z180.

  • Page 50: Ld (Iy+D),N

    IY and a displacement value d. Then, loads the data in register H into the memory location whose address is the sum of the data in index register IY and a dis- placement value d plus 1. This instruction is implemented for the Rabbit and is not available for the Z180.

  • Page 51: Ld (Mn),A

    LD (mn),A LD (mn),HL LD (mn),IX LD (mn),IY LD (mn),ss Opcode Instruction Clocks Operation 32 n m LD (mn),A (mn) = A 22 n m LD (mn),HL (mn) = L; (mn + 1) = H DD 22 n m LD (mn),IX (mn) = IX ;...

  • Page 52: Ld (Sp+N),Hl

    Flags ALTD Description These instructions are implemented for the Rabbit and are not available for the Z180. • LD (SP+n),HL: Loads the data in the register L into the memory location whose address is the sum of the data in the Stack Pointer, SP, and the displacement n. Then loads the data in the register H into the memory location whose address is the sum of the data in SP, the displacement n, and 1.

  • Page 53: Ld A,(Mn)

    LD A,(BC) LD A,(DE) LD A,(mn) Opcode Instruction Clocks Operation LD A,(BC) 6 (2,2,2) A = (BC) LD A,(DE) 6 (2,2,2) A = (DE) 3A n m LD A,(mn) 9 (2,2,2,1,2) A = (mn) Flags ALTD • • Description Loads the Accumulator with the data whose address in memory is: •...

  • Page 54: Ld A,Iir

    A = XPC Flags ALTD • Description Loads the Accumulator with the data in the Extension of the Program Counter, XPC. This instruction is priv- ileged. It is implemented for the Rabbit and is not available for the Z180. Rabbit 2000/3000 Microprocessor...

  • Page 55: Ld Dd,(Mn)

    Loads the alternate register pair dd' (any of the registers BC', DE', or HL') with the data in the register pair BC or the register pair DE. These instructions are implemented for the Rabbit and are not available for the Z180.

  • Page 56: Ld Dd,Mn

    IIR is used to specify the Most Significant Byte (MSB) of the Internal Peripheral Interrupt address. The value loaded in the IIR is concatenated with the appropriate Internal Peripheral address to form the 16-bit ISR starting address for that peripheral. Rabbit 2000/3000 Microprocessor...

  • Page 57: Ld Hl,(Mn)

    LD HL,(mn) LD HL,(HL+d) LD HL,(IX+d) LD HL,(IY+d) Opcode Instruction Clocks Operation 2A mn LD HL,(mn) 11 (2,2,2,1,2,2) L = (mn); H = (mn + 1) DD E4 d LD HL,(HL+d) 11 (2,2,2,1,2,2) L = (HL + d); H = (HL + d + 1) E4 d LD HL,(IX+d) 9 (2,2,1,2,2)

  • Page 58: Ld Hl,(Sp+N)

    Loads the register L with the data whose address is the data in index register SP plus a displacement d. Then loads the register H with the data whose address is the data in index register SP plus a displacement d plus 1. This instruction is implemented for the Rabbit and is not available for the Z180. LD HL,IX...

  • Page 59: Ld Ix,(Mn)

    Then loads the high order byte of IX with the data whose address is the data in the Stack Pointer register plus a displacement n plus 1. This instruction is implemented for the Rabbit and is not available for the Z180.

  • Page 60: Ld Ix,Mn

    • LD IX,HL: Loads the index register IX with the data in word register HL. This instruction is implemented for the Rabbit and is not available for the Z180 • LD IX,mn: Loads the index register IX with the 16-bit constant mn.

  • Page 61: Ld Iy,(Sp+N)

    SP plus a displacement n. Then loads the high order byte of IY with the data whose address is the data in the Stack Pointer register plus a displacement n plus 1. This instruction is implemented for the Rabbit and is...

  • Page 62: Ld R,(Hl)

    • the data in word register HL, or • the sum of the data in index register IX and a displacement d, or • the sum of the data in index register IY and a displacement d. Rabbit 2000/3000 Microprocessor...
  • Page 63 LD r,n Opcode Instruction Clocks Operation —— LD r,n 4 (2,2) r = n 3E n LD A,n 4 (2,2) A = n 06 n LD B,n 4 (2,2) B = n 0E n LD C,n 4 (2,2) C = n 16 n LD D,n 4 (2,2)
  • Page 64 Loads the one-byte register r (any of the registers A, B, C, D, E, H, or L) with the data in another one-byte register g (any of the registers A, B, C, D, E, H, or L). Rabbit 2000/3000 Microprocessor...

  • Page 65: Ld Sp,Hl

    XPC = A Flags ALTD Description Loads the Extension of the Program Counter, XPC, with the data in the Accumulator. This instruction is priv- ileged. It is implemented for the Rabbit and is not available for the Z180. Instruction Reference Manual...

  • Page 66: Lddr

    LDD or LDI. Return from the inter- rupt is to the first byte of the instruction which is the I/O prefix byte if there is one Rabbit 2000/3000 Microprocessor...

  • Page 67: Ldp (Hl),Hl

    (bits 19 through 16) are defined as the four least significant bits of the Accumulator (bits 3 though 0). The LDP instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space. These instructions are implemented for the Rabbit and are not available for the Z180. •...

  • Page 68: Ldp (Mn),Hl

    (bits 19 through 16) are defined as the four least significant bits of the Accumulator (bits 3 though 0). The LDP instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space. These instructions are implemented for the Rabbit and are not available for the Z180. •...

  • Page 69: Ldp Hl,(Hl)

    (bits 19 through 16) are defined as the four least significant bits of the Accumulator (bits 3 though 0). The LDP instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space. These instructions are implemented for the Rabbit and are not available for the Z180. •...

  • Page 70: Ldp Hl,(Mn)

    (bits 19 through 16) are defined as the four least significant bits of the Accumulator (bits 3 though 0). The LDP instructions bypass the MMU’s address translation unit for direct access to the 20-bit memory address space. These instructions are implemented for the Rabbit and are not available for the Z180. •...

  • Page 71: Ljp X,Mn

    SP plus 2. Finally it adds three to the value in the SP and stores the result in the SP This instruction is implemented for the Rabbit and is not available for the Z180.
  • Page 72 If there is a carry from this stage of the 2’s complement operation, it is passed to the next stage. This instruction is implemented for the Rabbit and is not available for the Z180. Examples: LD BC, 0FFFFh ;BC gets -1...
  • Page 73 Opcode Instruction Clocks Operation ED 44 4 (2,2) A = 0 - A Flags ALTD • • • • • Description Subtracts the value of the data in the Accumulator from zero and stores the result in the Accumulator. Opcode Instruction Clocks Operation...

  • Page 74: Or (Iy+D)

    Accumulator. Example If the byte in the Accumulator is 0100 1100 and the byte in the memory location pointed to by HL is 1110 0101, the operation: OR (HL) would result in the Accumulator containing 1110 1101. Rabbit 2000/3000 Microprocessor...

  • Page 75: Or Hl,De

    The result is stored in HL. This instruction was implemented for the Rabbit and is not available for the Z180. OR IX,DE...
  • Page 76 The relative bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes are compared, etc.) and the associated bit in the result byte is set if either of the compared bits is set. The result is stored in the Accumulator. Rabbit 2000/3000 Microprocessor...
  • Page 77 POP IP: Loads the Interrupt Priority Register, IP, with the data at the memory location in the Stack Pointer, SP, and then increments the data in SP. This privileged instruction was imple- mented for the Rabbit and is not available for the Z180. •...
  • Page 78 Stack Pointer, SP, then loads the high order byte of zz with the data at the mem- ory address immediately following the one held in SP. SP is then incremented twice. Rabbit 2000/3000 Microprocessor...
  • Page 79 PUSH IP: Loads the location in memory whose address is 1 less that the data held in the Stack Pointer, SP, with the data in the Interrupt Priority Register IP. Then decrements SP. This instruc- tion was implemented for the Rabbit and is not available for the Z180. •...
  • Page 80 (any of the word register AF, BC, DE, or HL), and loads the memory loca- tion with the address two less than the data in SP with the low order byte of the data in zz. Then SP is decre- mented twice. Rabbit 2000/3000 Microprocessor...

  • Page 81: Res B,(Hl)

    RES b,(HL) RES b,(IX+d) RES b,(IY+d) Opcode Instruction Clocks Operation —— RES b,(HL) (HL) = (HL) & ~bit b CB 86 RES bit 0,(HL) (HL) = (HL) & ~bit 0 CB 8E RES bit 1,(HL) (HL) = (HL) & ~bit 1 CB 96 RES bit 2,(HL) (HL) = (HL) &...
  • Page 82 Resets bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the data whose address is held in the register r (any of the register A, B, C, D, E, H, or L). The bit is reset by performing a logical AND between the selected bit and its complement. Rabbit 2000/3000 Microprocessor...
  • Page 83 Opcode Instruction Clocks Operation 8 (2,1,2,2,1) = (SP); PC = (SP + 1); (low) (high) SP = SP + 2 Flags ALTD Description RET transfers execution from a subroutine to the program that called it. First it loads the low order byte of the Program Counter, PC, with the data at the memory address in the Stack Pointer, SP, then loads the high order byte of PC with the data at the memory address immediately following the one held in SP.
  • Page 84 • zero flag set • carry flag not set • carry flag set • LZ/NV Logic Zero/Overflow flag is not set • LO/V Logic Zero/Overflow flag is set • sign flag not set • sign flag set. Rabbit 2000/3000 Microprocessor...

  • Page 85: Reti

    PC with the data whose address is two higher than the data in the SP. The data in the SP is then incremented three times. This privileged instruction was implemented for the Rabbit and is not available for the Z180.

  • Page 86: Rl (Ix+D)

    If the HL contains 0x4545, the byte in the memory location 0x4545 is 0110 1010, and the CF is set, then after the execution of the operation RL (HL) The byte in memory location 0x4545 will contain 1101 0101 and the CF will be reset. Rabbit 2000/3000 Microprocessor...
  • Page 87 (bit 0 moves to bit 1, etc.) while the CF moves to bit 0 and bit 15 moves to the CF. See Figure 1 on page 82. This instruction was implemented for the Rabbit and is not available for the Z180.
  • Page 88 Rotates to the left with the Carry Flag, CF, the contents of the Accumulator. Each bit in the register moves to the next highest-order bit position (bit 0 moves to bit 1, etc.) while the CF moves to bit 0 and bit 7 moves to the CF. See Figure 1 on page 82. Rabbit 2000/3000 Microprocessor...

  • Page 89: Rlc (Hl)

    RLC (HL) RLC (IX+d) RLC (IY+d) Opcode Instruction Operation CB 06 RLC (HL) (HL) = {(HL)[6,0],(HL)[7]}; CF = (HL)[7] DD CB d 06 RLC (IX+d) (IX + d) = {(IX + d)[6,0],(IX + d)[7]}; 13** CF = (IX+d)[7] FD CB d 06 RLC (IY+d) (IY + d) = {(IY + d)[6,0],(IY + d)[7]};...

  • Page 90: Rlca

    Rotates to the left the data in the Accumulator. Each bit in the register moves to the next highest-order bit position (bit 0 moves to bit 1, etc.) while bit 7 moves to both bit 0 and the CF. See Figure 2 on page 85. Rabbit 2000/3000 Microprocessor...

  • Page 91: Rr (Ix+D)

    RR (HL) RR (IX+d) RR (IY+d) Opcode Instruction Clocks Operation CB 1E RR (HL) 10 (2,2,1,2,3) {(HL),CF} = {CF,(HL)} DD CB d 1E RR (IX+d) 13 (2,2,2,2,2,3) {(IX+d),CF} = {CF,(IX+d)} FD CB d 1E RR (IY+d) 13 (2,2,2,2,2,3) {(IY+d),CF} = {CF,(IY+d)} Flags ALTD •...
  • Page 92 Rotates to the right with the Carry Flag, CF, the data in word register DE or HL. Bit 0 moves to the CF, bits 1 through 15 move to the next lowest-order bit position, and the CF moves to bit 15. See Figure 3 on page 87. These instructions were implemented for the Rabbit and are not available for the Z180. RR IX...
  • Page 93 RR r Opcode Instruction Clocks Operation —— RR r 4 (2,2) {r,CF} = {CF,r} CB 1F RR A 4 (2,2) {A,CF} = {CF,A} CB 18 RR B 4 (2,2) {B,CF} = {CF,B} CB 19 RR C 4 (2,2) {C,CF} = {CF,C} CB 1A RR D 4 (2,2)

  • Page 94: Rrc (Hl)

    Each bit in the register moves to the next lowest-order bit position (bit 7 moves to bit 6, etc.) while bit 0 moves to both bit 7 and the CF. See Figure 4 below. Figure 4: The bit logic of the RRC instruction. Rabbit 2000/3000 Microprocessor...

  • Page 95: Rrca

    RRC r Opcode Instruction Clocks Operation —— RRC r 4 (2,2) r = {r[0],r[7,1]}; CF = r[0] CB 0F RRC A 4 (2,2) A = {A[0],A[7,1]}; CF = A[0] CB 08 RRC B 4 (2,2) B = {B[0],B[7,1]}; CF = B[0] CB 09 RRC C 4 (2,2)
  • Page 96 SP. The value in the SP is then decre- mented twice. The PC is reset by loading it with the address to reset to v (any of the addresses 0020, 0030, 0040, 0050, or 0070). Rabbit 2000/3000 Microprocessor...

  • Page 97: Sbc (Ix+D)

    SBC A,(HL) SBC (IX+d) SBC (IY+d) Opcode Instruction Clocks Operation SBC A,(HL) 5 (2,1,2) A = A - (HL) - CF DD 9E d SBC (IX+d) 9 (2,2,2,1,2) A = A - (IX + d) - CF FD 9E d SBC (IY+d) 9 (2,2,2,1,2) A = A - (IY + d) - CF...
  • Page 98 These operations output an inverted carry: • The Carry Flag is set if the Accumulator is less than the data being subtracted from it. • The Carry Flag is cleared if the Accumulator is greater than the data being subtracted from it. Rabbit 2000/3000 Microprocessor...

  • Page 99: Sbc Hl,Ss

    SBC HL,ss Opcode Instruction Clocks Operation —— SBC HL,ss 4 (2,2) HL = HL - ss - CF ED 42 SBC HL,BC 4 (2,2) HL = HL - BC - CF ED 52 SBC HL,DE 4 (2,2) HL = HL - DE - CF ED 62 SBC HL,HL 4 (2,2)

  • Page 100: Set B,(Hl)

    • the data in word register HL, or • the sum of the data in index register IX and a displacement d, or • the sum of the data in index register IY and a displacement d. Rabbit 2000/3000 Microprocessor...
  • Page 101 SET b,r Opcode Instruction Clocks Operation SET b,r 4 (2,2) r = r | bit CB (0) CB (1) CB (2) CB (3) CB (4) CB (5) CB (6) CB (7) Flags ALTD • Description Sets bit b (any of the bits 0, 1, 2, 3, 4, 5, 6, or 7) of the data in register r (any of the registers A, B, C, D, E, H, or L).

  • Page 102: Sla (Hl)

    Bits 0 through 6 are each shifted to the next highest-order bit position (bit 0 moves to bit 1, etc.). Bit 7 is shifted to the Carry Flag, CF. Bit 0 is reset. See Figure 5 below. Figure 5: The bit logic of the SLA instruction. Rabbit 2000/3000 Microprocessor...
  • Page 103 SLA r Opcode Instruction Clocks Operation —— SLA r 4 (2,2) r = {r[6,0],0}; CF = r[7] CB 27 SLA A 4 (2,2) A = {A[6,0],0}; CF = A[7] CB 20 SLA B 4 (2,2) B = {B[6,0],0}; CF = B[7] CB 21 SLA C 4 (2,2)

  • Page 104: Sra (Hl)

    Bits 7 through 1 are shifted to the next lowest-order bit position (bit 7 is shifted to bit 6, etc.). Bit 7 is also cop- ied to itself. Bit 0 is shifted to the Carry Flag, CF. See Figure 6 below. Figure 6: The bit logic of the SRA instruction. Rabbit 2000/3000 Microprocessor...
  • Page 105 SRA r Opcode Instruction Clocks Operation —— SRA r 4 (2,2) r = {r[7],r[7,1]}; CF = r[0] CB 2F SRA A 4 (2,2) A = {A[7],A[7,1]}; CF = A[0] CB 28 SRA B 4 (2,2) B = {B[7],B[7,1]}; CF = B[0] CB 29 SRA C 4 (2,2)

  • Page 106: Srl (Hl)

    Each bit is shifted to the next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shift to the Carry Flag, CF. Bit 7 is reset. See Figure 7 below. Figure 7: The bit logic of the SRL instruction. Rabbit 2000/3000 Microprocessor...
  • Page 107 SRL r Opcode Instruction Clocks Operation —— SRL r 4 (2,2) r = {0,r[7,1]}; CF = r[0] CB 3F SRL A 4 (2,2) A = {0,A[7,1]}; CF = A[0] CB 38 SRL B 4 (2,2) B = {0,B[7,1]}; CF = B[0] CB 39 SRL C 4 (2,2)

  • Page 108: Sub (Hl)

    D6 n SUB n 4 (2,2) A = A - n Flags ALTD • • • • • Description Subtracts from the data in the Accumulator the 8-bit constant n. The result is stored in the Accumulator. Rabbit 2000/3000 Microprocessor...
  • Page 109 SUB r Opcode Instruction Clocks Operation —— SUB r A = A - r SUB A A = A - A SUB B A = A - B SUB C A = A - C SUB D A = A - D SUB E A = A - E SUB H...

  • Page 110: Xor (Hl)

    If the HL contains 0x4000 and the memory location 0x4000 contains the byte 1001 0101 and the Accumula- tor contains the byte 0101 0011 then the execution of the instruction XOR (HL) would result in the byte in the Accumulator becoming 1100 0110. Rabbit 2000/3000 Microprocessor...
  • Page 111 XOR n Opcode Instruction Clocks Operation EE n XOR n 4 (2,2) A = [A & ~n] | [~A & n] Flags ALTD • • • • Description Performs an exclusive OR operation between the byte in the Accumulator and the 8-bit constant n. The corre- sponding bits of each byte are compared (i.e., the bit 1 of both bytes are compared, the bit 2 of both bytes are compared, etc.) and the associated bit in the result byte is set if and only if one of the two compared bits is set.
  • Page 112 Rabbit 2000/3000 Microprocessor...

  • Page 113: Quick Reference Table

    : An “N” in this column indicates that the instruction has been added to the Z180 instruction set by the Rabbit 2000/3000. An “M” indicates that this instruction is from the Z180, but has been modified. A “P” indicates a privileged instruction.
  • Page 114 I /O external prefix 11010011 I /O internal prefix IPSET 0 11101101 01000110 4 (2,2) IP = {IP[5:0], 00} IPSET 1 11101101 01010110 4 (2,2) IP = {IP[5:0], 01} IPSET 2 11101101 01001110 4 (2,2) IP = {IP[5:0], 10} Rabbit 2000 Microprocessor...
  • Page 115 Opcode Opcode Opcode Opcode Instruction Clock cycles S Z LV C Operation N/M/P byte 1 byte 2 byte 3 byte 4 IPSET 3 11101101 01011110 4 (2,2) IP = {IP[5:0], 11} IPRES 11101101 01011101 4 (2,2) IP = {IP[1:0], IP[7:2]} JP (HL) 11101001 4 (2,2)
  • Page 116 11000111 ----n--- ----m--- ---x---- 10 (2,2,2,2,2) XPC = x; PC = mn PCL = (SP); PCH = (SP+1); XPC = LRET 11101101 01000101 13 (2,2,1,2,2,2,2) (SP+2); SP = SP+3 11110111 12 (2,10) HL:BC = BC * DE Rabbit 2000 Microprocessor...
  • Page 117 Opcode Opcode Opcode Opcode Instruction Clock cycles S Z LV C Operation N/M/P byte 1 byte 2 byte 3 byte 4 11101101 01000100 4 (2,2) A = 0 - A 00000000 No operation OR (HL) 10110110 5 (2,1,2) A = A | (HL) OR (IX+d) 11011101 10110110...
  • Page 118 9 (2,2,2,1,2) A = [A & ~(IY+d)] | [~A & (IY+d)] XOR n 11101110 ----n--- 4 (2,2) A = [A & ~n] | [~A & n] XOR r 10101-r- A = [A & ~r] | [~A & r] Rabbit 2000 Microprocessor...
  • Page 119 Z80 and Z180 are trademarks of Zilog, Inc. Notice to Users Rabbit Semiconductor products are not authorized for use as crit- ical components in life-support devices or systems unless a spe- cific written agreement regarding such intended use is entered into between the customer and Rabbit Semiconductor prior to use.
  • Page 120 Rabbit 2000/3000 Microprocessor...

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