Page 1 ® Rabbit 2000 Microprocessor User’s Manual 019–0069 • 041018–M...
Page 2 Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Rabbit 2000 are registered trademarks of Rabbit Semiconductor. Dynamic C is a registered trademark of Z-World, Inc. Rabbit Semiconductor 2932 Spafford Street...
Page 3: Table Of Contents
1.1 Features and Specifications ........................1 1.2 Summary of Rabbit Advantages ......................5 Chapter 2. Rabbit Design Features 2.1 The Rabbit 8-bit Processor vs. 16-bit and 32-bit Processors ..............8 2.2 Overview of On-Chip Peripherals ......................8 2.2.1 Serial Ports ...........................8 2.2.2 System Clock ..........................8 2.2.3 Time/Date Oscillator ........................9...
Page 4 4.2 Open-Drain Outputs Used for Key Scan.................... 44 4.3 Cold Boot ............................45 4.4 The Slave Port ............................ 46 4.4.1 Slave Rabbit As A Protocol UART ................... 47 Chapter 5. Pin Assignments and Functions 5.1 Package Schematic and Pinout......................49 5.2 Package Mechanical Dimensions.......................
Page 5 14.2 Clock Spectrum Spreader Module ....................150 Chapter 15. AC Timing Specifications 15.1 Memory Access and I/O Read/Write Times...................154 15.2 Current Consumption........................162 Chapter 16. Rabbit BIOS and Virtual Driver 16.1 The BIOS ............................165 16.1.1 BIOS Services ........................165 16.1.2 BIOS Assumptions .........................166 16.2 Virtual Driver..........................166...
Page 6 18.17 Control Instructions - Jumps and Calls ..................185 18.18 Miscellaneous Instructions......................185 18.19 Privileged Instructions........................186 Chapter 19. Differences Rabbit vs. Z80/Z180 Instructions Chapter 20. Instructions in Alphabetical Order With Binary Encoding Appendix A. A.1 The Rabbit Programming Port ......................197 A.2 Use of the Programming Port as a Diagnostic/Setup Port...............
Page 7: Chapter 1. Introduction
C-language development system (Dynamic C). Z-World is providing the soft- ware development tools for the Rabbit. The Rabbit 2000 is easy to use. Hardware and software interfaces are as uncluttered and are as foolproof as possible. The Rabbit 2000 has outstanding computation speed for a microprocessor with an 8-bit bus.
Page 8 • A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of communication.
Page 9 • The built-in main clock oscillator uses an external crystal or more usually a ceramic resonator. Typical resonator frequencies are in the range of 1.8 MHz to 29.5 MHz. Since precision timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator with ½...
Page 10 Figure 1-1 shows a block diagram of the Rabbit. D0–D7 /CS0, /CS1, /CS2 A0–A19 /OE0, /OE1 /WE0, /WE1 PA0–PA7 XTALB1 PB0–PB7 XTALB2 PC0–PC7 PD0–PD7 PE0–PE7 XTALA1 XTALA2 TXA, RXA, CLKA, ATXA, ARXA TXB, RXB, CLKB, ATXB, ARXB TXC, RXC I0–I7 TXD, RXD SD0–SD7,...
Page 11: Summary Of Rabbit Advantages
32 kHz. • The Rabbit may be used to create an intelligent peripheral or a slave processor. For example, protocol stacks can be off loaded to a Rabbit slave. The master can be any processor.
Page 12 Rabbit 2000 Microprocessor...
Page 13: Chapter 2. Rabbit Design Features
ESIGN EATURES The Rabbit is an evolutionary design. The instruction set and the register layout is that of the Z80 and Z180. The instruction set has been augmented by a substantial number of new instructions. Some obsolete or redundant Z180 instructions have been dropped to make available efficient 1-byte opcodes for important new instructions.
Page 14: The Rabbit 8-Bit Processor Vs. 16-Bit And 32-Bit Processors
The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a com- pact instruction set, its performance is as good as many 16-bit processors. Thus the Rabbit can handle many 16-bit operations.
Page 15: Time/Date Oscillator
Table 2-1 provides estimates of the operating power for selected clock speeds. Table 2-1. Operating Power Estimates at Selected Clock Speeds Current Current Clock Speed Voltage Power Clock Speed Voltage Power (MHz) (mW) (MHz) (mW) (mA) (mA) 25.0 12.5 12.5 0.032 0.054 0.135...
Page 16: Slave Port
2.2.5 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor, which could be another Rabbit. The port is shared with parallel port A and is a bidirectional data port. The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port.
Page 17 Timer B is convenient for creating an event at a precise time in the future under program control. Figure 2-3 illustrates the Rabbit timers. perclk/2 Timer A System...
Page 18: Design Standards
10-pin connector with two rows of pins on 2 mm centers. The port is connected to Rabbit serial port A, to the startup mode pins on the Rabbit, to the Rabbit reset pin, and to a programmable output pin that is used to signal the PC that attention is needed.
Page 19: Processor Registers
EATURES 3.1 Processor Registers The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are new. The EIR register is the same as the Z80 I register, and is used to point to a table of interrupt vectors for the exter- nally generated interrupts.
Page 20 The registers IX, IY and HL can also serve as index registers. They point to memory addresses from which data bits are fetched or stored. Although the Rabbit can address a megabyte or more of memory, the index registers can only directly address 64K of mem- ory (except for certain extended addressing LDP instructions).
Page 21: Memory Mapping
C programs. The Rabbit memory-mapping unit is similar to, but more powerful than, the Z180 mem- ory-mapping unit. Figure 3-2 illustrates the relationship among the major components related to addressing memory.
Page 22 The root segment is mapped to the base of flash memory and contains the star- tup code as well as other code that may happen to be stored there. The data segment usage varies depending on the overall strategy for setting up memory. It may be an extension of Rabbit 2000 Microprocessor...
Page 23 the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or the data segment. Special instructions support executing code that is visible in the XPC segment.
Page 24: Extended Code Space
16-bit variables. The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16- bit address. The Rabbit paging scheme uses the concept of a sliding page, which is 8K long.
Page 25: Extending Data Memory
than the XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the root using short jumps and calls. However, a long call must be used when code in the XPC segment is called. Functions located in the root have an efficiency advantage because a long call and a long return require 32 clocks to execute, but a short call and a short return require only 20 clocks to execute.
Page 26 This requires copying the root code to RAM at startup time. Copying root code to RAM is not necessarily that burdensome since the amount of RAM required can be quite small, say 12K for example. Rabbit 2000 Microprocessor...
Page 27: Practical Memory Considerations
128 K of RAM, but smaller or larger memories may be used. Although the Rabbit can support code size approaching a megabyte, it is anticipated that the great majority of applications will use less then 250K of code, equivalent to approxi- mately 10,000–20,000 C statements.
Page 28: Instruction Set Outline
Many instructions in the Z180 require a substantial number of additional clocks. The Rabbit usually requires two clocks for each byte of the op code and for each data byte read. Three clocks are needed for each data byte written. One additional clock is required if a memory address needs to be computed or an index register is used for addressing.
Page 29: Load Immediate Data To A Register
I/O space. There are two I/O spaces, internal peripherals and external I/O devices. Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit (see Chapter 19, “Differences Rabbit vs. Z80/Z180 Instructions”). Most of the deleted instructions are obsolete or are little-used instructions that can be emulated by several Rabbit instructions.
Page 30: Load Or Store Data Using An Index Register
; store HL at address pointed to ; by IX plus -128 to +127 offset LD HL,(IX+d) LD HL',(IX+d) LD (IY+d),HL ; store HL at address pointed to ; by IY plus -128 to +127 offset LD HL,(IY+d) LD HL',(IY+d) Rabbit 2000 Microprocessor...
Page 31: Register To Register Move
The alternate 8-bit registers can be a destination, for example: LD a',c LD d',b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of the required prefix byte. Instructions such as are not allowed.
Page 32: Push And Pop Instructions
16-bit operations. The Z180/Z80 has a weak set of 16-bit operations, and as a practical matter the programmer has to resort to combinations of 8-bit operations in order to perform many 16-bit operations. The Rabbit has many new op codes for 16-bit operations, removing some of this weakness.
Page 33 instruction is a special instruction designed to help test the HL register. BOOL BOOL sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed. The flags are set according to the result. can also operate on IX and IY.
Page 34 If the number is unsigned or is to be treated as unsigned for a logical right shift, then an unsigned by unsigned multiply must be per- formed. The problem can be simplified by excluding the case where the multiplier is 2^^15. Rabbit 2000 Microprocessor...
Page 35: Input/Output Instructions
In certain conditions where an I/O operation is followed by a special one-byte instruction, a bug in the original Rabbit 2000 chip causes an I/O access to take place instead of a mem- ory access operation. The problem was corrected in revisions A–C of the Rabbit 2000.
Page 36 I/O instruction and a follow- ing instruction from the above list. Rabbit users are unlikely to encounter this problem because the sequence of instructions that exhibit the bug is never generated by the Dynamic C compiler or in any of the stan- dard libraries.
Page 37: How To Do It In Assembly Language-Tips And Tricks
3.4 How to Do It in Assembly Language—Tips and Tricks 3.4.1 Zero HL in 4 Clocks BOOL HL ; 2 clocks, clears carry, HL is 1 or 0 RR HL ; 2 clocks, 4 total - get rid of possible 1 This sequence requires four clocks compared to six clocks for LD HL,0 3.4.2 Exchanges Not Directly Implemented...
Page 38: Comparisons Of Integers
: compute HL==DE OR a ; clear carry SBC HL,DE ; zero is equal BOOL HL ; force to zero, 1 DEC HL ; invert logic BOOL HL ; 12 clocks total -logical not, 1 for inputs equal Rabbit 2000 Microprocessor...
Page 39 Some simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a reverse sense from . In the following examples, the pseudo-code in the form does not indicate a load of with the LD DE,(65535-B) address pointed to by...
Page 40: Atomic Moves From Memory To I/O Space
DE. The decrementing of HL and DE is a side effect. If the repeating instructions are used, interrupts can take place between successive itera- LDIR LDDR tions. Word stores to I/O space can be used to set two I/O registers at adjacent addresses with a single noninterruptable instruction. Rabbit 2000 Microprocessor...
Page 41: Interrupt Structure
3.5 Interrupt Structure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con- trol is transferred to the address of the interrupt service routine. The address of the inter- rupt service routine has two parts: the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt, as shown in Table 7-10.
Page 42 20 µs. The intention in the Rabbit is that most interrupting devices will use priority 1 level inter- rupts. Devices that need extremely fast response to interrupts will use priority level 2 or 3 interrupts.
Page 43: Multiple External Interrupting Devices
3.5.2 Multiple External Interrupting Devices The Rabbit has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge sensitive, meaning that it requests an interrupt only when a rising or falling edge, whichever is specified in the setup registers, takes place.
Page 44: Critical Sections
No interrupt can be allowed between the test of the bit and the setting of the bit as this might allow two different program to both think they own the resource. Rabbit 2000 Microprocessor...
Page 45: Computed Long Calls And Jumps
3.5.6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made. This would be done by the following sequence. LD xpc,a JP (HL) In this case, A has the new XPC, and HL has the new PC. This code should normally be executed in the root segment so as not to pull the memory out from under the JP (HL) instruction.
Page 46 Rabbit 2000 Microprocessor...
Page 47: Chapter 4. Rabbit Capabilities
4. R ABBIT APABILITIES This section describes the various capabilities of the Rabbit that may not be obvious from the technical description. 4.1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control. The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock.
Page 48 1 µs. If multiple pulses need to be measured simultaneously, then the precision will be reduced, but this reduction can be minimized by careful programming. Rabbit 2000 Microprocessor...
Page 49: Pulse Width Modulation To Reduce Relay Power
4.1.1 Pulse Width Modulation to Reduce Relay Power Typically relays need far less current to hold them closed than is needed to initially close them. For example, if the driver is switched to a 75% duty cycle using pulse width modu- lation after the initial period when the relay armature is picked, the holding current will be approximately 75% of the full duty-cycle current and the power consumption will be about 56% as great.
Page 50: Open-Drain Outputs Used For Key Scan
The advantage of using open-drain outputs is that if two keys in the same col- umn are depressed, there will not be a fight between a driver driving the line high and another driver driving it low. o.d. o.d. Figure 4-2. Using Open-Drain Outputs for Key Scan Rabbit 2000 Microprocessor...
Page 51: Cold Boot
Rabbit-based microprocessor board. • If the Rabbit is used as a slave processor, the master processor can cold boot it over via the slave port. This means the slave can operate without any nonvolatile memory. Only RAM is required.
Page 52: The Slave Port
The master can cold boot and download a program to the slave. The master does not have to be a Rabbit processor, but can be any type of pro- cessor capable of reading and writing standard registers.
Page 53: Slave Rabbit As A Protocol Uart
4.4.1 Slave Rabbit As A Protocol UART A prime application for the Rabbit used as a slave is to create a 4-port UART that can also handle the details of a communication protocol. The master sends and receives messages over the slave port.
Page 54 Rabbit 2000 Microprocessor...
Page 55: Chapter 5. Pin Assignments And Functions
5. P SSIGNMENTS AND UNCTIONS 5.1 Package Schematic and Pinout /WE1 /CS2 /OE1 /CS1 /OE0 /CS0 /WE0 PC0, TXD /SCS, I7, PE7 PC1, RXD I6, PE6 PC2, TXC INT1B, I5, PE5 PC3, RXC INT0B, I4, PE4 PC4, TXB I3, PE3 PC5, RXB I2, PE2 PC6, TXA...
Page 56: Package Mechanical Dimensions
Figure 5-3 shows the PC board land pattern for the Rabbit 100-pin PQFP. This land pat- tern is RLP 711A, the registered land pattern for the Rabbit 2000 chip as developed by the Surface Mount Land Patterns Committee and specified in IPC-SM-782A, Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999.
Page 57 TOLERANCE AND SOLDER JOINT ANALYSIS X: 0.44 mm Heel Fillet Toe Fillet Side Fillet Figure 5-3. PC Board Land Pattern for Rabbit 100-pin PQFP User’s Manual...
Page 58: Rabbit Pin Descriptions
5.3 Rabbit Pin Descriptions Table 5-1 lists all the pins on the device, along with their direction, function, and pin num- ber on the package. Table 5-1. Rabbit Pin Descriptions Pin Group Pin Name Direction Function Pin Numbers Peripheral clock output. This signal is...
Page 59 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Pin Numbers Startup mode select (SMODE1 = pin 35, SMODE0 = pin 36) to determine bootstrap procedure. (SMODE1 = 0, SMODE0 = 0) start executing at address zero.
Page 60 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Pin Numbers I/O read strobe. Driven low on an external I/O read bus cycle. May be used to drive I/O Read glue logic concerned with I/O expansion, /IORD...
Page 61 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Pin Numbers I/O Port D. Each bit may be individually selected to be an input or output. Each output may be selected to be high-low drive or open drain. Outputs are buffered...
Page 62 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Pin Numbers VBAT +3.0 V (battery backup), +3.3 V or +5.0 V 42 +3.3 V or +5.0 V 3, 28, 53, 78, 92 Power 2, 27, 39, 52,...
Page 63 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Pin Numbers I/O strobes. Each strobe uses 1/8th of the I/O space or 8K addresses. Each strobe can /I0,/I1, be programmed as: chip select, read, write, /I2, /I3, combined read or write.
Page 64: Bus Timing
The user should not attempt a design that uses the chip select or a memory address as a clock or state changing signal without taking this into con- sideration. Rabbit 2000 Microprocessor...
Page 65: Description Of Pins With Alternate Functions
5.5 Description of Pins with Alternate Functions Table 5-2. Pins With Alternate Functions Pin Name Output Function Input Function Other Function 1. Low on first op code fetch. Programmable output STATUS (38) 2. Low on interrupt port high/low acknowledge (SMODE0, SMODE1) 1-bit input after boot SMODE1 (35) Startup boot mode...
Page 66 PD2 (48) PD1 (49) PD0 (50) /I7—programmable I/O PE7 (21) /SCS (slave chip select). strobe. PE6 (22) PE5 (23) INT1 (input) PE4 (24) INT0 (input) PE3 (25) PE2 (27) PE1 (29) INT1 (input) PE0 (30) INT0 (input) Rabbit 2000 Microprocessor...
Page 67: Dc Characteristics
NOTE: Stresses beyond those listed in Table 5-3 may cause permanent damage. The rat- ings are stress ratings only, and functional operation of the Rabbit 2000 chip at these or any other conditions beyond those indicated in this section is not implied.
Page 68: Volts
5.6.1 5.0 Volts Table 5-4 outlines the DC characteristics for the Rabbit at 5.0 V over the recommended operating temperature range from T = –40°C to +85°C, V = 4.5 V to 5.5 V. Table 5-4. 5.0 Volt DC Characteristics...
Page 69: Volts
5.6.2 3.3 Volts Table 5-5 outlines the DC characteristics for the Rabbit at 3.3 V over the recommended operating temperature range from T = –40°C to +85°C, V = 2.7 V to 3.6 V. Table 5-5. 3.3 Volt DC Characteristics...
Page 70: I/O Buffer Sourcing And Sinking Limit
5.7 I/O Buffer Sourcing and Sinking Limit Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 8 mA of current per pin at full AC switching speed. Full AC switching assumes 22.11 MHz CPU clock and capacitive loading on address and data lines of less than 100 pF per pin. Address pin A0 and Data pin D0 are rated at 16 mA each.
Page 71: Chapter 6. Rabbit Internal I/O Registers
6.1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6-1. Addi- tional I/O registers were added in the Rabbit 2000 revisions as listed in the table. Refer to Section B.2.1 for more information.
Page 72 Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset 0xx00000 Rabbit 2000 Global Revision Register (Rev A–C) 0xx00001 Rabbit 2000A Global Revision Register (Rev A–C) GREV 0x2F 0xx00010 Rabbit 2000B Global Revision Register (Rev A–C) 0xx00011 Rabbit 2000C Global Revision Register (Rev A–C)
Page 73 Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Port D Data Direction Register PDDDR 0x67 00000000 Port D Bit 0 Register PDB0R 0x68 xxxxxxxx Port D Bit 1 Register PDB1R 0x69 xxxxxxxx Port D Bit 2 Register...
Page 74 Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Serial Port A Status Register SASR 0xC3 0xx00000 Serial Port A Control Register SACR 0xC4 xx000000 Serial Port B Data Register SBDR 0xD0 xxxxxxxx Serial Port B Address Register...
Page 75 Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Timer B Control/Status Register TBCSR 0xB0 xxxxx000 Timer B Control Register TBCR 0xB1 xxxx0000 Timer B MSB 1 Register TBM1R 0xB2 xxxxxxxx Timer B LSB 1 Register...
Page 76 Rabbit 2000 Microprocessor...
Page 77: Chapter 7. Miscellaneous I/O Functions
(GREV) is reserved for revision identification. The CPU identification (GCPU) of all revisions of the Rabbit 2000 microprocessor is the same. Rabbit 2000 revi- sions are differentiated by the value in the GREV register. Refer to Section B.2.2 for more information.
Page 78: Rabbit Oscillators And Clocks
7.2 Rabbit Oscillators and Clocks There are two crystal oscillators built into the Rabbit. The main oscillator accepts crystals up to a frequency of 29.4912 MHz (first overtone crystals only). The clock oscillator requires a 32.768 kHz crystal, which is powered by VBAT, and can be battery-backed.
Page 79 Table 7-1. Global Control/Status Register (I/O adr = 0x00) Bit(s) Value Description No reset or watchdog timer timeout since the last read. The watchdog timer timed out. These bits are cleared by a read of this (read only) register. This bit combination is not possible. Reset occurred.
Page 80: Clock Doubler
Table 7-3 lists the recommended values or “settings” for the Global Clock Double Register for various oscillator frequencies. Table 7-3. Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value Frequency Range ≤11.0592 MHz 11.0592–12.9024 MHz 12.9024–14.7576 MHz 14.7576–16.5888 MHz 16.5888–20.2752 MHz 20.2752–23.9616 MHz 23.9616–31.3344 MHz >31.3344 MHz Rabbit 2000 Microprocessor...
Page 81 When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2. Oscillator Oscillator delayed and inverted Doubled clock Delay Time 0.48P 0.52P 0.48P 0.52P Address, /CS Example Write Data out...
Page 82: Controlling Power Consumption
It is anticipated that these measures would reduce current consumption to as low as 25 µA plus some leakage that would be significant at high operating temperatures. Rabbit 2000 Microprocessor...
Page 83: Output Pins Clk, Status, /Wdtout, /Bufen
7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN Certain output pins can have alternate assignments as specified in Table 7-4. Table 7-4. Global Output Control Register (GOCR = 0x0E) Bit(s) Value Description CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. CLK pin is low.
Page 84: Time/Date Clock (Real-Time Clock)
RAM. Table 7-5. Real-Time Clock Read Registers Real-Time Clock x Holding Register (RTC0R) R/W (Address = 00000010) (RTC1R) (Address = 00000011) (RTC2R) (Address = 00000100) (RTC3R) (Address = 00000101) (RTC4R) (Address = 00000110) (RTC5R) (Address = 00000111) Rabbit 2000 Microprocessor...
Page 85 Table 7-6. Real-Time Clock RTCxR Data Registers Bit(s) Value Description Read The current value of the 48-bit RTC holding register is returned. Writing to the RTC0R transfers the current count of the RTC to six holding Write registers while the RTC continues counting. Table 7-7.
Page 86: Watchdog Timer
If any have counted down to zero, the interrupt routine disables interrupts, and then enters an endless loop waiting for the reset. Hits of the virtual watchdogs are placed in the user’s program at “must exercise” locations. Rabbit 2000 Microprocessor...
Page 87 Table 7-9. Watchdog Timer Test Register (WDTTR adr = 0x09) Bit(s) Value Description Clock the least significant byte of the WDT timer from the peripheral 0x51 clock. (Intended for chip test and code 0x54 below only.) Clock the most significant byte of the WDT timer from the peripheral 0x52 clock.
Page 88: System Reset
Table 7-10 describes the state of the I/O pins after an external reset is recognized by the Rabbit CPU. Note that the /RESET signal must be held low for three clocks for the proces- sor to begin the reset sequence. There is no facility to tri-state output lines such as the address lines and the memory and I/O control lines.
Page 89 Table 7-10. Rabbit 2000 Reset Sequence and State of I/O Pins /RESET Low † Pin Name Direction Post-Reset Recognized by CPU /RESET Input Low or High High Output High Operational XTALA1 Input Not Affected Not Affected XTALA2 Output Not Affected...
Page 90: Rabbit Interrupt Structure
7.9 Rabbit Interrupt Structure An interrupt causes a call to be executed, pushing the PC on the stack and starting to exe- cute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively.
Page 91 The interrupts differ from most Z80 or Z180 interrupts in that the 256-byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16-bit pointer to the routine. The interrupt vectors are spaced 16 bytes apart so that the entire code will fit in the table for very small interrupt routines.
Page 92: External Interrupts
A–C of the Rabbit 2000. (Refer to Appendix B for further information to determine which version of the Rabbit 2000 chip you are using.) If you are working with an original Rabbit 2000 chip, see Technical Note 301, Rabbit 2000 Microprocessor Interrupt Problem.
Page 93: Interrupt Vectors: Int0 - Eir,0X00/Int1 - Eir,0X08
7.9.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 When it is desired to expand the number of interrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou- tines. Each additional interrupting device will have to signal the processor that it is requesting an interrupt.
Page 94: Bootstrap Operation
Parallel Ports B and E are used for the Slave Port control signals. Only Slave Port Data Register 0 is used for bootstrap operation, and any writes to the other data registers will be ignored by the processor, and can actually interfere with the bootstrap operation by mask- ing the Write Empty signal. Rabbit 2000 Microprocessor...
Page 95 Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock. Note that the serial clock must be externally supplied for boot- strap operation.
Page 96 Rabbit 2000 Microprocessor...
Page 97: Chapter 8. Memory Mapping And Interface
See Section 3.2, “Memory Mapping,” for a discussion of the Rabbit memory mapping. Figure 8-1 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interface unit accepts the 20-bit addresses and generates control signals applied directly to the memory chips.
Page 98 STACKSEG = 0x11 Locates stack segment in physical memory. DATASEG = 0x12 Locates data segment in physical memory. Table 8-2. Segment Size Register Bits 7..4 Bits 3..0 SEGSIZE = 0x13 Boundary address stack segment. Boundary address data segment. Rabbit 2000 Microprocessor...
Page 99: Memory Interface Unit
Rabbit. There are three separate chip select output lines (/CS0, /CS1, and /CS2) that can be used to select one of three different memory chips. A field in the control register determines which chip select is selected for memory accesses to the quadrant.
Page 100: Memory Control Unit Registers
256K byte pages, only one of which is available at a time. In revisions A–C of the Rabbit 2000 chip, the reset state of the MB0CR register is set to inhibit /WE0. See Section B.2.6 for more information.
Page 101: Mmu Instruction/Data Register
Refer to Section B.2.5 for more information on using I and D space on the Rabbit 2000 chip. More information on separate I and D implementa- tion will be available in the Rabbit 2000 Designer’s Handbook, and is currently available in the Rabbit 3000 Designers Handbook.
Page 102: Allocation Of Extended Code And Data
52K in the 64K D space and continues. The 52K space must be shared with the root code and data, and is allocated upward from zero. Dynamic C also supports extended data constants. These are mixed in with the extended code in flash. Rabbit 2000 Microprocessor...
Page 103: How Compiler Compiles To Memory
8.5 How Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory. In any but the smallest programs, most of the code is compiled to extended memory. This code executes in the 8K window from E000 to FFFF.
Page 104 FFFF E000 FFFF E000 4K pages Memory View in 8K window each segment Figure 8-4. Compilation of Code Segments in Extended Memory Rabbit 2000 Microprocessor...
Page 105: Chapter 9. Parallel Ports
ARALLEL ORTS The Rabbit has five 8-bit parallel ports designated A, B, C, D and E. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below.
Page 106: Parallel Port A
When the port is read, the value read reflects the voltages on the pins, "1" for high and "0" for low. This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage. Rabbit 2000 Microprocessor...
Page 107: Parallel Port B
9.2 Parallel Port B Parallel Port B, shown in Table 9-4, has six inputs and two outputs when used exclusively as a parallel port. Table 9-3. Parallel Port B Registers Register Name Mnemonic I/O address Reset Port B Data Register PBDR 0x40 00xxxxxx...
Page 108: Parallel Port C
On reset the active (even-numbered) function register bits and data register bits are zeroed. This causes the port to output zeros on the four output bits. Rabbit 2000 Microprocessor...
Page 109: Parallel Port D
9.4 Parallel Port D Parallel port D, shown in Figure 9-1, has eight pins that can programmed individually to be inputs and outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses.
Page 110 5 are reset to zero. ARXA ATXA ARXB ATXB Inputs I/O Data perclk/2 Driver—optional open drain Timer A1 Timer B1 Timer B2 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-1. Parallel Port D Block Diagram Rabbit 2000 Microprocessor...
Page 111 Table 9-8. Parallel Port D Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDDR (R/W) adr = 0x060 out = out = out = out = out = out = out = out = PDDCR (W) open...
Page 112: Parallel Port E
The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses. /scs INT1 INT0 Inputs I/O Data perclk/2 Timer A1 Timer B1 Timer B2 INT1 INT0 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-2. Parallel Port E Block Diagram Rabbit 2000 Microprocessor...
Page 113 Table 9-10. Parallel Port E Registers Register Name Mnemonic I/O address Reset Port E Data Register PEDR 0x70 xxxxxxxx Port E Control Register PECR 0x74 xx00xx00 Port E Function Register PEFR 0x75 00000000 Port E Data Direction Register PEDDR 0x77 00000000 Port E Bit 0 Register PEB0R...
Page 114 Bits 1, 0 00—clock upper nibble on pclk/2 00—clock lower nibble on pclk/2 01—clock on timer A1 01—clock on timer A1 10—clock on timer B1 10—clock on timer B1 11—clock on timer B2 11—clock on timer B2 Rabbit 2000 Microprocessor...
Page 115: Chapter 10. I/O Bank Control Registers
10. I/O B ONTROL EGISTERS The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I/O bus cycle.
Page 116 NOTE: Refer to Section 3.3.8 for a fix to a bug that manifests itself if an I/O instruction (prefix IOI or IOE) is followed by one of 12 single-byte op codes that use HL as an index register. Rabbit 2000 Microprocessor...
Page 117: Chapter 11. Timers
11. T IMERS There are two timers—Timer A and Timer B. Timer A is intended mainly for generating the baud clock for the serial ports, a periodic clock for clocking parallel ports D and E, or for generating periodic interrupts. Timer B can be used for the same functions, but it can- not generate the baud clock.
Page 118: Timer A
Each of the five countdown registers in timer A can cause an interrupt. There is one inter- rupt vector for timer A and a common interrupt priority. A common status register (TACSR) has a bit for each timer that indicates if the output pulse for that timer has taken Rabbit 2000 Microprocessor...
Page 119: Timer A I/O Registers
place since the last read of the status register. When the status register is read, these bits are cleared. No bit will be lost. Either it will be read by the status register read or it will be set after the status register read is complete. If a bit is on and the corresponding interrupt is enabled, an interrupt will occur when priorities allow.
Page 120: Practical Use Of Timer A
(maxi- mum 256 clocks). Then both timers’ reload registers can be set to new values before or after both are clocked. Rabbit 2000 Microprocessor...
Page 121: Timer B
11.2 Timer B Figure 11-1 shows a block diagram of Timer B. The main clock for Timer B is /2. Bit 0 of the TBCSR register controls the main clock PCLK for Timer B. The Timer B counter can be driven directly by /16 [( /2)/8], PCLK...
Page 122 The MSB x registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-7. Table 11-7. Timer B MSB x Register (TBM1R/TBM2R = 0x0B2/0x0B4) Bits 7:6 Bits 5:0 Two most significant bits of timer Not used. match preload register. Rabbit 2000 Microprocessor...
Page 123: Using Timer B
11.2.1 Using Timer B Normally the prescaler is set to divide /2 by a number that provides a counting rate PCLK appropriate to the problem. For example, if the clock is 22.1184 MHz, then /2 is PCLK 11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of the 10-bit clock in 92.6 µs.
Page 124 This restriction limits the minimum pulse width to about 5 µs, depending on the clock speed and interrupt priorities. Rabbit 2000 Microprocessor...
Page 125: Chapter 12. Rabbit Serial Ports
See Section B.2.3 for more information. The Rabbit has four on-chip serial ports designated A, B, C, and D. All the ports can perform asynchronous serial communications at high baud rates. Ports A and B have the additional capabilities of being able to operate as clocked ports and of being switchable to alternate I/O pins.
Page 126: Serial Port Register Layout
One choice is the peripheral clock divided by 2—with that choice and a well-chosen crys- tal frequency for the main oscillator, the most commonly used baud rates can be obtained down to approximately 2400 bps at the highest Rabbit clock frequencies (see Section A.4 in Appendix A).
Page 127 Control Register (write only) 11xx0100 SxCR * Extra stop bit is supported in revisions A–C of the Rabbit 2000 chip via this register. Table 12-2 describes the serial port status registers. Table 12-2. Serial Port Status Registers (adr = 11xx0011, xx = A,B,C,D)
Page 128 Port C,” and Section 9.4, “Parallel Port D,” for more details). Bits 3,2—This sets the mode of operation. Modes 10 and 11 apply only to Ports A and B. Bits 1,0—These bits enable interrupts and set the interrupt priority. Rabbit 2000 Microprocessor...
Page 129: Serial Port Interrupt
12.2 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts. There is a sepa- rate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3.
Page 130: Transmit Serial Data Timing
On receive, the scan for the next start bit starts immediately after the stop bit is detected. The stop bit is normally detected at a sample clock that nominally occurs in the center of the stop bit. If there is a 9th (8th) address bit, the stop bit follows that bit. Rabbit 2000 Microprocessor...
Page 131: Clocked Serial Ports
12.5 Clocked Serial Ports See Section B.2.3 for more information for more information about a new feature added to revisions A–C to better support full-duplex communication. Ports A and B can operate in clocked mode. The data line and clock line are driven as shown in Figure 12-4.
Page 132 To transmit each byte in external clock mode, the user must load the data register and then store the send code. When the shift register is idle and the receiver provides a clock burst, the data bits are transferred to the shift register and are shifted out. Once the transfer is Rabbit 2000 Microprocessor...
Page 133 made to the shift register, a new byte can be loaded into the transmit register and a new send code can be stored. To receive a byte in external clock mode, the user must set the receive code for the first byte and then store the receive code for the next byte after each byte is removed from the data register.
Page 134: Clocked Serial Timing
Figure 12-5. Full-Duplex Clocked Serial Timing Diagram with Internal Clock 12.6.2 Clocked Serial Timing with External Clock In a system where the Rabbit serial clock is generated by an external device, the clock sig- nal has to be synchronized with the internal peripheral clock (...
Page 135: Serial Port Software Suggestions
(Ext.) Valid Figure 12-7. Synchronous Serial Data Receive Timing with External Clock When clocking the Rabbit externally, the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit . If...
Page 136 All increments are done in a circular fashion, most easily accomplished by making the buffer a power of two in length, then anding a mask after the increment. The actual memory address is the pointer plus a buffer base address. Rabbit 2000 Microprocessor...
Page 137: Controlling An Rs-485 Driver And Receiver
12.7.1 Controlling an RS-485 Driver and Receiver RS-485 uses a half-duplex method of communication. One station enables its driver and sends a message. After the message is complete, the station disables the driver and listens to the line for a reply. The driver must be enabled before the start bit is sent and not dis- abled until the stop bit has been sent.
Page 138: Extra Stop Bits, Sending Parity, 9Th Bit Communication Schemes
Certain systems, such as some 8051-based multidrop communications systems, use a 9th data bit to mark the start of a message frame. The Rabbit 2000 can receive parity or message formats that contain a 9th bit without problem. Transmitting messages with par- ity or messages that always contain a 9th bit is also possible.
Page 139 9-bit (8-bit) character. Sending a 9th bit or an extra stop bit is easier with revisions A–C of the Rabbit 2000 chip, which have a long stop register as described in Section B.2.3. It was more difficult to transmit an extra stop bit or a parity bit of value "1"...
Page 140: Supporting 9Th Bit Communication Protocols
Some microprocessor serial ports have a “wake up” mode of operation. In this mode, char- acters without the 9th bit set to "1" are ignored, and no interrupt is generated. When the start of a frame is detected, an interrupt takes place on that byte. If the byte contains the Rabbit 2000 Microprocessor...
Page 141: Rabbit-Only Master/Slave Protocol
9th bit only by using special drivers. 12.7.7 Rabbit-Only Master/Slave Protocol If only Rabbit microprocessors are connected, the 9th bit low can be set on the address byte, and the remaining bytes can be transmitted in the normal 8-bit mode. This is more efficient than other 9th bit protocols because only the first byte requires 11 baud times;...
Page 142 Rabbit 2000 Microprocessor...
Page 143: Chapter 13. Rabbit Slave Port
The slave port is a part of the slave Rabbit, but logically it is an independent device that is used to communicate between the two processors. Figure 13-1 shows a diagram of the slave port.
Page 144 The flag for that register is thus set to a "1" when the reg- ister is written to, and the flag is set to a "0" when the register is read. Rabbit 2000 Microprocessor...
Page 145 The registers appear to be internal I/O registers to the slave. To the master, at least for a Rabbit master, the registers appear to be external I/O registers. The figure below shows the sequence of events when the master reads/writes the slave port registers.
Page 146 Either side that is interrupted can clear the signal that is causing an interrupt request by writ- ing to the slave port status register. The data bits are ignored, but the flip-flop that is the source of the interrupt request is cleared. Figure 13-3 shows a logical schematic of this func- tionality. Rabbit 2000 Microprocessor...
Page 147 There is no requirement that the master and slave share a clock, but doing so makes it unnecessary to connect a crystal to the slaves. Each Rabbit in Figure 13-4 has to have RAM memory. The master must also have flash memory. However, the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program.
Page 148 • /SCS—Input. Slave chip select. The slave ignores read or write requests unless the chip select is low. If a Rabbit is used as a master, this line can be connected to one of the master’s programmable chip select lines /I0–/I7.
Page 149: Hardware Design Of Slave Port Interconnection
Figure 13-4 shows a typical circuit diagram for connecting two slave Rabbits to a master Rabbit. The designer has the option of cold-booting the slave and downloading the pro- gram to RAM on each cold start. Another option is to configure the slave with both RAM and flash memory.
Page 150 If bit 3 is "0," then bit 2 controls whether parallel port A is an input (bit 2 = 0) or an output (bit 2 = 1). Bits 1,0—This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled by (0,0). Rabbit 2000 Microprocessor...
Page 151: Applications And Communications Protocols For Slaves
Some possible applications are listed below. Keep in mind that the Rabbit can also be operated as a slave processor via a serial port and some of the protocols will work well via a serial communications connection. If a serial connection is used, the protocol becomes more complicated if errors in transmission need to be taken into account.
Page 152: Master-Slave Messaging Protocol
A typical slave system consists of a Rabbit microprocessor and a RAM memory con- nected to it. The clock can be provided either by connecting a crystal, or crystals to the slave or by providing an external clock, which could be the master’s clock.
Page 153 As a simple example, suppose that the slave is to be used as a four-port UART. It has the capability to send or receive characters on any of its four serial ports. Leaving aside the question of setup for parameters, such as the baud rate, we could define a protocol as fol- lows.
Page 154 Rabbit 2000 Microprocessor...
Page 155: Chapter 14. Rabbit 2000 Clocks
ABBIT LOCKS The Rabbit 2000 has two built-in oscillators. The 32.768 kHz clock oscillator is needed for the battery-backable clock, the watchdog timer, and the cold-boot function. The main oscillator provides the run-time clock for the microprocessor. Figure 14-1 shows these oscillator circuits.
Page 156: Low-Power Design
The Rabbit 2000 does not have a "standby" mode that some microprocessors have. Instead, the Rabbit has the ability to switch its clock to the 32.768 kHz oscillator. This is called the sleepy mode. When this is done, the power consumption is decreased dramatically. The current consumption is often reduced to the region of 100 µA at this clock speed.
Page 157: Chapter 15. Ac Timing Specifications
IMING PECIFICATIONS The Rabbit 2000 processor may be operated at voltages between 2.5 V and 5.5 V, and at temperatures from –40°C to +85°C with use possible use over the range -55°C to +120°C. Most users will operate the Rabbit at either 5.0 V or 3.3 V. The most computation per watt is obtained at approximately 3.3 V.
Page 158 The graphs in Figure 15-1 and Figure 15-2 illustrate the maximum clock speed at which no failure is detected for a typical Rabbit 2000 as the voltage and temperature are varied. The official design specifications specify a lower maximum frequency to allow for pro- cess variation.
Page 159 5.0 V 3.3 V Temperature (°C) Figure 15-1. Rabbit 2000 Typical Maximum Operating Frequency versus Temperature at 5 V and 3.3 V 50.00 45.00 40.00 35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 Voltage (V) Figure 15-2. Rabbit 2000 Typical Maximum Operating Frequency versus Voltage at 25°C...
Page 160: Memory Access And I/O Read/Write Times
Higher temperatures reduce the maximum operating speed by approximately 1% for each 5°C. In addition, higher operating speeds increase the die temperature because of the heat generated and therefore slightly compound the adverse effects of higher temperature. Rabbit 2000 Microprocessor...
Page 161 Table 15-2. Memory Access Time Requirements (V±5%, T -40°C to +70°C) Memory Memory Maximum PC- Clock Access Time Period Wait Access Time Compatible Speed @5 V 20 pF States @5 V 70 pF Load Baud Rate (ns) (MHz) Load (ns) (bps) (ns) 29.4912...
Page 162 Figure 15-3, Figure 15-4, and Figure 15-5 illustrate the memory and I/O read and write cycles. The Rabbit operates at 2 clocks per bus cycle plus any wait states that might be specified. The following memory read time delays were measured.
Page 163 Memory Read (no wait states) valid valid valid Memory Write (no extra wait states) valid valid valid Figure 15-3. Memory Read and Write Cycles Notice that the data times are different, depending on whether data are being read or writ- ten.
Page 164 17 ns DHZV Data valid to high Z relative to clock (T — 11 ns — 17 ns DVHZ The measurements were taken at the 50% points under the same conditions that the I/O read delays were measured. Rabbit 2000 Microprocessor...
Page 165 I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified. External I/O Read (no extra wait states) valid valid valid External I/O Write (no extra wait states) valid valid valid Figure 15-4. I/O Read and Write Cycles No Extra Wait States User’s Manual...
Page 166 Figure 15-5 shows the effect of adding an extra wait state to the memory read/write cycles. The effects are similar for the I/O bus read/write cycles. Memory Read (one wait state) valid valid valid Memory Write (one wait state) valid valid valid Figure 15-5. Memory Read and Write with Wait States Rabbit 2000 Microprocessor...
Page 167 Table 15-7 provides typical memory and external I/O parameters measured at 3.3 V. Table 15-7. Memory and External I/O Read/Write Parameters at 3.3 V Parameter Description Value Time from CPU clock rising Max. 10 ns @ 20 pF edge to address valid 19 ns @ 70 pF Data read setup time Min.
Page 168: Current Consumption
0.032 (sleepy mode) 0.113 0.032 (sleepy mode) 0.072 The current consumed by memory and other devices included in the system, including pullup resistors, outputs driving a load, and floating inputs, must be added to the figures in Table 15-8. Rabbit 2000 Microprocessor...
Page 169 The 32.768 kHz clock oscillator and the associated real-time clock consume approxi- mately 23 µA at 3 V. (At 2.25 V, when backed by a battery, the current consumption is approximately 11 µA.) The (typical) current consumed when the main power is off, and only the 32.768 kHz oscillator and clock are powered, is given by the formula current (µA) = 5.44*(V - 0.86) where V is the operating voltage.
Page 170 Rabbit 2000 Microprocessor...
Page 171: Chapter 16. Rabbit Bios And Virtual Driver
IRTUAL RIVER When a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is auto- matically incorporated into the program. Virtual Driver is the name given to some initial- ization routines and a group of services performed by the periodic interrupt. The Rabbit BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is compiled to the target along with the application program.
Page 172: Bios Assumptions
Processors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is expected to be connected to /CS0, /WE0, and /OE0. (See the Rabbit 2000 Designer’s Handbook Memory Planning chapter if you want to design a board with RAM only.) The crystal frequency is expected to be n*1.8432 MHz.
Page 173 gram consistency checking or because a part of the program that should be executing peri- odically is not executing and the watchdog times out. The Virtual Driver’s periodic interrupt hits the hardware watchdog timer with a 2 second time-out. If the periodic interrupt stops working, then the watchdog will time out after 2 seconds.
Page 174 Rabbit 2000 Microprocessor...
Page 175: Chapter 17. Other Rabbit Software
16 clocks. Only about 3 instructions could be executed between ticks. A different set of rules applies in the ultra slow or “sleepy” mode. The Rabbit 2000 auto- matically disables periodic interrupts when the clock mode is switched to 32 kHz or one of the multiples of 32 kHz.
Page 176: Reading And Writing I/O Registers
17.2 Reading and Writing I/O Registers The Rabbit has two I/O spaces: internal I/O registers and external I/O registers. 17.2.1 Using Assembly Language The fastest way to read and write I/O registers in Dynamic C is to use a short segment of assembly language inserted in the C program.
Page 177: Shadow Registers
17.3 Shadow Registers Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates on the chip, making possible greater capability at lower cost. Write-only registers are eas- ier to use if a memory location, called a shadow register, is associated with each write- only register.
Page 178: Write-Only Registers Without Shadow Registers
For example, a write to the status register in the Rabbit serial ports is used to clear the transmitter interrupt request, but the data bits are ignored, and the status register is actually a read-only register except for the special functionality attached to the act of writing the register.
Page 179 , is also maintained by the Virtual Driver. MS_TIMER Two utility routines are provided that can be used to convert times between the traditional format (10-Jan-2000 17:34:12) and the seconds since 1-Jan-1980 format. // converts time structure to seconds unsigned long mktime(struct tm *timeptr);...
Page 180 Rabbit 2000 Microprocessor...
Page 181: Chapter 18. Rabbit Instructions
ABBIT NSTRUCTIONS Summary All bugs related to instructions have been fixed in revisions A–C of the Rabbit 2000 chip. See Appendix B for more information. Detailed information on instructions in provided in this chapter. “Load Immediate Data” on page 178 “8-bit Indexed Load and Store”...
Page 182 L/V is set to 1 for logical operations if any of the four most significant bits of the result are 1, and L/V is reset to 0 if all four of the most significant bits of the result are 0. Rabbit 2000 Microprocessor...
Page 183 Symbols Rabbit Z180 Meaning Bit select: 000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7 Condition code select:...
Page 184: Load Immediate Data
- - - - L = (IX+d); H = (IX+d+1) LD (IY+d),HL d - - - - (IY+d) = L; (IY+d+1) = H LD HL,(IY+d) s - - - - L = (IY+d); H = (IY+d+1) Rabbit 2000 Microprocessor...
Page 185: 16-Bit Load And Store 20-Bit Address
18.5 16-bit Load and Store 20-bit Address Instruction I S Z V C Operation LDP (HL),HL - - - - (HL) = L; (HL+1) = H. (Adr[19:16] = A[3:0]) LDP (IX),HL - - - - (IX) = L; (IX+1) = H. (Adr[19:16] = A[3:0]) LDP (IY),HL - - - -...
Page 186: Exchange Instructions
HL = HL + ss + CF -- ss=BC, DE, HL, SP ADD HL,ss - - - * HL = HL + ss ADD IX,xx - - - * IX = IX + xx -- xx=BC, DE, IX, SP Rabbit 2000 Microprocessor...
Page 187: 8-Bit Arithmetic And Logical Ops
ADD IY,yy - - - * IY = IY + yy -- yy=BC, DE, IY, SP ADD SP,d - - - * SP = SP + d -- d=0 to 255 AND HL,DE * * L 0 HL = HL & DE AND IX,DE * * L 0 IX = IX &...
Page 188: 8-Bit Bit Set, Reset And Test
(HL) = (HL) + 1 INC (IX+d) b * * V - (IX+d) = (IX+d) + 1 INC (IY+d) b * * V - (IY+d) = (IY+d) + 1 INC r * * V - r = r + 1 Rabbit 2000 Microprocessor...
Page 189: 8-Bit Fast A Register Operations
18.13 8-bit Fast A register Operations Instruction I S Z V C Operation - - - - A = ~A * * V * A = 0 - A - - - * {CY,A} = {A,CY} RLCA - - - * A = {A[6,0],A[7]};...
Page 190: Instruction Prefixes
Interrupts can occur between dif- ferent repeats, but not within an iteration equivalent to LDD or LDI. Return from the inter- rupt is to the first byte of the instruction which is the I/O prefix byte if there is one. Rabbit 2000 Microprocessor...
Page 191: Control Instructions - Jumps And Calls
18.17 Control Instructions - Jumps and Calls Instruction I S Z V C Operation CALL mn - - - - (SP-1) = PCH; (SP-2) = PCL; PC = mn; SP = SP-2 DJNZ j - - - - B = B-1; if {B != 0} PC = PC + j JP (HL) - - - - PC = HL...
Page 192: Privileged Instructions
If an interrupt was allowed between the and set instructions, another routine could set the semaphore and two routines could think that they both owned the semaphore. Rabbit 2000 Microprocessor...
Page 193: Chapter 19. Differences Rabbit Vs. Z80/Z180 Instructions
ABBIT VS NSTRUCTIONS The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. The more important instructions that were dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler.
Page 194 R register LD IIR,A LD A,IIR ; was I register The following Z80/Z180 instructions have been dropped and are not supported. Alterna- tive Rabbit instructions are provided. Z80/Z180 Instructions Dropped Rabbit Instructions to Use CALL CC,ADR JR (JP) ncc,xxx ; reverse condition...
Page 195: Chapter 20. Instructions In Alphabetical Order With Binary Encoding
20. I NSTRUCTIONS IN LPHABETICAL RDER INARY NCODING Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag Description ALTD selects alternate flags ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI and IOE (“I” Column) Symbol Key Flag Description IOI and IOE affect source and destination...
Page 196 Word register select: 00 = BC, 01 = DE, 10 = HL, 11 = AF Logical zero if all four of the most significant bits of the result are 0. † Logical one if any of the four most significant bits of the result are 1. Rabbit 2000 Microprocessor...
Page 197 Instruction Byte 1 Byte 2 Byte 3 Byte 4 I S Z V C ADC A,(HL) 10001110 s * * V * ADC A,(IX+d) 11011101 10001110 ----d--- s * * V * ADC A,(IY+d) 11111101 10001110 ----d--- s * * V * ADC A,n 11001110 ----n---...
Page 198 LD (mn),ss 11101101 01ss0011 ----n--- ----m--- d - - - - LD (SP+n),HL 11010100 ----n--- - - - - LD (SP+n),IX 11011101 11010100 ----n--- - - - - LD (SP+n),IY 11111101 11010100 ----n--- - - - - Rabbit 2000 Microprocessor...
Page 199 Instruction Byte 1 Byte 2 Byte 3 Byte 4 I S Z V C LD A,(BC) 00001010 s - - - - LD A,(DE) 00011010 s - - - - LD A,(mn) 00111010 ----n--- ----m--- s - - - - LD A,EIR 11101101 01010111...
Page 200 11001011 ----d--- 00011110 b * * L * RR DE 11111011 * * L * RR HL 11111100 * * L * RR IX 11011101 11111100 * * L * RR IY 11111101 11111100 * * L * Rabbit 2000 Microprocessor...
Page 201 Instruction Byte 1 Byte 2 Byte 3 Byte 4 I S Z V C RR r 11001011 00011-r- * * L * 00011111 - - - * RRC (HL) 11001011 00001110 b * * L * RRC (IX+d) 11011101 11001011 ----d--- 00001110 b * * L * RRC (IY+d)
Page 202 Rabbit 2000 Microprocessor...
Page 203: Appendix
CMOS driver. The STATUS pin is used to by the Rabbit-based target to request attention when a breakpoint is encountered in the target under test. The SMODE pins are pulled up by a +5 V/+3 V level from the interface.
Page 204: Use Of The Programming Port As A Diagnostic/Setup Port
C. Using these two ports plus the STATUS pin as an output clock, the user can create a synchronous clocked communication port using instructions to toggle the clock and data. Another Rabbit-based board can be used to translate the clocked serial signal to an asyn- Rabbit 2000 Microprocessor...
Page 205: Suggested Rabbit Crystal Frequencies
A.4 Suggested Rabbit Crystal Frequencies Table 15-2 provides a list of suggested Rabbit operating frequencies. The crystal can be half the operating frequency if the clock doubler is used up to approximately 29.5 MHz.
Page 206 Rabbit 2000 Microprocessor...
Page 207: Appendix
Rabbit 2000A through Rabbit 2000C revisions. 2. First revision (Rabbit 2000A)—identified by IQ3T on the package. This version began shipping in January, 2002. All the bugs in the original Rabbit 2000 were fixed, and additional new features were added: (a) Support for separate I &...
Page 208 EMI in April, 2002. This part was phased out and will be replaced by the Rabbit 2000C for volume orders. This version has the clock spectrum spreader, but lacks the early I/O enable, which results in tight specifications for memory I/O enable.
Page 209: Discussion Of Fixes And Improvements
B.2 Discussion of Fixes and Improvements Table B-1 lists bug fixes, improvements, and additions for the various revisions of the Rabbit 2000. Table B-1. Summary of Rabbit 2000 Fixes and Improvements Rabbit Rabbit Rabbit Rabbit 2000 2000A 2000B 2000C Description...
Page 210: Rabbit Internal I/O Registers
B.2.1 Rabbit Internal I/O Registers Table B-2 summarizes the reset state of the new I/O registers added in the Rabbit 2000 revisions. Table B-2. Reset State of Rabbit 2000x I/O Registers Present Register Name Mnemonic Reset in Rev. Address Global Clock Modulator 0 Register B–C...
Page 211: Revision-Level Id Register
One register identifies the CPU (GCPU), and the other register is reserved for revision identification (GREV). The CPU identification (GCPU) of all revisions of the Rabbit 2000 microprocessor is the same. Rabbit 2000 revi- sions are differentiated by the value in the GREV register.
Page 212 (read only) 1 Ignore the SMODE pins program fetch function. read These bits report the state of the SMODE pins. 00000 Revision identifier for the Rabbit 2000 00001 Revision identifier for the Rabbit 2000A 00010 Revision identifier for the Rabbit 2000B...
Page 213: Serial Port Changes
In the original Rabbit 2000 it was difficult to transmit the additional stop bit. This could only be done by inserting a time delay before the next byte was transmitted. An additional register, the long stop register, was added in revisions A–C. The register serves as an alter- nate data-out register, and data stored in this register will be transmitted with 2 stop bits (high level at the Tx pin).
Page 214 Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port PB0 The Serial Port interrupt is disabled. The Serial Port uses Interrupt Priority 1. The Serial Port uses Interrupt Priority 2. Rabbit 2000 Microprocessor...
Page 215: Improved Battery-Backup Circuit
Improvements were made in revisions A–C to reduce the internal power consumption of the RTC circuit. In addition, external circuitry was designed to further reduce power con- sumption by the overall oscillator circuit in board-level products based on the Rabbit 2000.
Page 216 For a 5 V p-p swing, the power is 1.5 µW. The power is 1.0 µW for 4 V p-p, and the power is 0.5 µW for 3 V p-p. TN235, External 32.768 kHz Oscillator Circuits, provides further information on oscilla- tor circuits and crystals. Rabbit 2000 Microprocessor...
Page 217: Added Support For Instruction/Data Split
This option is available on revisions A–C. Code generated for the Rabbit 2000A will run on the Rabbit 2000B or 2000C, but not vice versa. The separate I & D space allows the root segment and the data segment, normally the first 52K of the 64K address space, to be mapped into separate spaces for instruction fetch (I space) and data fetch or store (D space).
Page 218 /CS1 enable option used to improve the access time of battery-backable SRAM. NOTE: Bits [7:5] and [3:0] were always written with zero in the original Rabbit 2000 chip. Table B-9. MMU Instruction/Data Register (MMIDR = 0x010)
Page 219: Write Inhibit (/We0) After Reset
100,000. B.2.7 Chip Selects Inactive During Internal I/O In the original Rabbit 2000, it was found that whichever chip select was mapped to MB0CR would become active during internal I/O operations. This behavior did not cause any problems, but was corrected in revisions A–C.
Page 220: Ddcb/Fdcb Instruction Page And Wait State Bug Fixes
ROOT and/or DATASEG regions. However, all subsequent iterations took place in the code region (without any address inversion). This problem was fixed in revisions B and C of the Rabbit 2000. Rabbit 2000 Microprocessor...
Page 221: Clock Spectrum Spreader Module
B.2.12 Clock Spectrum Spreader Module This is a feature introduced on the Rabbit 3000 and migrated to revisions B and C of the Rabbit 2000. The clock spectrum spreader and early memory output enable are turned on by default for the Rabbit 2000C in Dynamic C version 7.32 and higher. The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 dB.
Page 222 The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station’s band. If the spreader is engaged, the pattern will disappear Rabbit 2000 Microprocessor...
Page 223 4% and lengthens the other by 4% if the clock is doubled. Early output enable is enabled by default on the Rabbit 2000C, but may be disabled. The clock low time is controlled by the clock doubler control register, and is assumed to be a minimum of 14 ns in the above example.
Page 224: Early Memory Output-Enable Feature
B.2.13 Early Memory Output-Enable Feature The early I/O enable feature was added to the Rabbit 2000C revision to relax the tight tim- ing requirements for memory access when using the clock spectrum spreader. The early I/O option extends the output enable time for the /OEx strobes and the write enable time for the /WEx strobes by a half clock cycle.
Page 225: Notice To Users
OTICE TO SERS RABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE-SUPPORT DEVICES OR SYSTEMS UNLESS A SPECIFIC WRITTEN AGREEMENT REGARDING SUCH INTENDED USE IS ENTERED INTO BETWEEN THE CUSTOMER AND RABBIT SEMICONDUCTOR PRIOR TO USE. Life-support devices or systems are devices or systems intended for sur- gical implantation into the body or to sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling and user’s...
Page 227: Index
..172 compiler operation .... 97 cold boot ....... 45 early output enable ..218 comparison Rabbit 2000 vs. I and D space ....95 instructions ....22, 175 Z80/Z180 ....187 I/O access time (no extra wait alphabetic order ....
Page 228 PQFP package ....49 MB0CR ....204, 213 WDTTR ......81 ports MBxCR ......94 XPC register ....18, 19 Rabbit slave port ....137 memory bank control ..94 reset .........82, 83 slave port lines ....142 memory mapping segments 92 revision history ....201, 203 slave port registers ...143 MMIDR ......212...
Page 229 clocked serial ports (Ports A– slave port ....... 46, 137 B) ........ 125 applications ..... 145 timers ........111 clocked serial timing ..128 hardware design ....143 Timer A ......113 controlling RS-485 driver and messaging protocol ..146 Timer B ......
Page 230 Rabbit 2000 Microprocessor...

Rabbit 2000 User Manual

Chapter 1. Introduction

Chapter 2. Rabbit Design Features

Chapter 3 . Details on Rabbit

Chapter 4. Rabbit Capabilities

Chapter 5. Pin Assignments and Functions

Chapter 6. Rabbit Internal I/O Registers

Chapter 7. Miscellaneous I/O Functions

Chapter 8. Memory Mapping and Interface

Chapter 9. Parallel Ports

Chapter 10. I/O Bank Control Registers

Chapter 11. Timers

Chapter 12. Rabbit Serial Ports

Chapter 13. Rabbit Slave Port

Chapter 14. Rabbit 2000 Clocks

Chapter 15. AC Timing Specifications

Chapter 16. Rabbit BIOS and Virtual Driver

Chapter 17. Other Rabbit Software

Chapter 18. Rabbit Instructions

Chapter 19. Differences Rabbit Vs. Z80/Z180 Instructions

Chapter 20. Instructions in Alphabetical Order with Binary Encoding

Appendix

Appendix

Notice to Users

Index

Quick Links

Need help?

Questions and answers

Related Manuals for Rabbit 2000

Summary of Contents for Rabbit 2000