Page 1 ® Rabbit 4000 Microprocessor User’s Manual 019–0152 • 070720–H...
Page 2 Rabbit and Dynamic C are registered trademarks of Rabbit Semiconductor Inc. Rabbit 4000 is a trademark of Rabbit Semiconductor Inc. The latest revision of this manual is available on the Rabbit Semiconductor Web site, www.rabbit.com, for free, unregistered download. Rabbit Semiconductor Inc.
Page 3: Table Of Contents
ABLE OF ONTENTS Chapter 1. The Rabbit 4000 Processor 1.1 Introduction............................1 1.2 Features ..............................1 1.3 Block Diagram ............................4 1.4 Basic Specifications ..........................5 1.5 Comparing Rabbit Microprocessors .....................6 Chapter 2. Clocks 2.1 Overview...............................9 2.1.1 Block Diagram ...........................10 2.1.2 Registers .............................10 2.2 Dependencies ............................11 2.2.1 I/O Pins ............................11...
Page 4 9.1.2 Registers ............................ 78 9.2 Dependencies ............................. 78 9.2.1 I/O Pins ............................78 9.2.2 Clocks ............................78 9.2.3 Other Registers .......................... 78 9.2.4 Interrupts ............................ 79 9.3 Operation ............................79 9.4 Register Descriptions ......................... 79 Rabbit 4000 Microprocessor User’s Manual...
Page 5 Chapter 10. Parallel Port C 10.1 Overview............................81 10.1.1 Block Diagram .........................82 10.1.2 Registers ...........................82 10.2 Dependencies ............................83 10.2.1 I/O Pins ............................83 10.2.2 Clocks ............................83 10.2.3 Other Registers .........................83 10.2.4 Interrupts ..........................83 10.3 Operation ............................83 10.4 Register Descriptions ........................84 Chapter 11. Parallel Port D 11.1 Overview............................87 11.1.1 Block Diagram .........................89 11.1.2 Registers ...........................90...
Page 6 17.4 Register Descriptions ........................155 Chapter 18. Slave Port 18.1 Overview ............................161 18.1.1 Block Diagram ........................162 18.1.2 Registers ..........................162 18.2 Dependencies ..........................163 18.2.1 I/O Pins ..........................163 18.2.2 Clocks ............................ 163 18.2.3 Interrupts ..........................163 Rabbit 4000 Microprocessor User’s Manual...
Page 7 18.3 Operation ............................164 18.3.1 Master Setup ..........................165 18.3.2 Slave Setup ..........................165 18.3.3 Master/Slave Communication ....................166 18.3.4 Slave/Master Communication ....................166 18.3.5 Handling Interrupts ........................166 18.3.6 Example ISR ..........................166 18.3.7 Other Configurations ......................167 18.3.8 Timing Diagrams ........................168 18.4 Register Descriptions ........................170 Chapter 19. DMA Channels 19.1 Overview............................173 19.1.1 Block Diagram ........................175 19.1.2 Registers ..........................176...
Page 8 24.1.3 I/O Handshake ........................249 24.1.4 Block Diagram ........................250 24.1.5 Registers ..........................250 24.2 Dependencies ..........................251 24.2.1 I/O Pins ..........................251 24.2.2 Clocks ............................ 251 24.2.3 Other Registers ........................251 24.2.4 Interrupts ..........................251 Rabbit 4000 Microprocessor User’s Manual...
Page 9 24.3 Operation ............................252 24.3.1 Auxiliary I/O Bus ........................252 24.3.2 I/O Strobes ..........................252 24.3.3 I/O Handshake ........................252 24.4 Register Descriptions ........................253 Chapter 25. Breakpoints 25.1 Overview............................263 25.1.1 Block Diagram ........................264 25.1.2 Registers ..........................265 25.2 Dependencies ..........................266 25.2.1 I/O Pins ..........................266 25.2.2 Clocks .............................266 25.2.3 Other Registers ........................266 25.2.4 Interrupts ..........................266 25.3 Operation ............................266...
Page 10 Appendix A. Parallel Port Pins with Alternate Functions A.1 Alternate Parallel Port Pin Outputs ....................329 A.2 Alternate Parallel Port Pin Inputs ....................331 Appendix B. Rabbit 4000 ESD Design Guidelines and Bug Workarounds B.1 ESD Sensitivity..........................334 B.1.1 ESD Design Guidelines ......................334 B.2 Bugs ..............................
Page 11: Chapter 1. The Rabbit 4000 Processor
The Rabbit 4000 is fast, running at up to 60 MHz, with compact code and support for up to 16 MB of memory. Operating with a 1.8 V core and 3.3 or 1.8 V I/O, the Rabbit 4000...
Page 12 A remote cold boot enables startup and programming via a serial port or the slave port. The Rabbit 4000 features five 8-bit parallel ports, yielding a total of 40 digital I/O. Six CMOS-compatible serial ports are available. All six are configurable as asynchronous (including output pulses in IrDA format), while four are configurable as clocked serial (SPI) and two are configurable as SDLC/HDLC.
Page 13 Ethernet standard, including support for auto-negotiation, link detection, multicast filter- ing, and broadcast addresses. All digital components of the 10Base-T MAC and PHY are present inside the Rabbit 4000; all that is needed to interface to an Ethernet network is some simple analog filtering and wave-shaping components.
Page 14: Block Diagram
1.3 Block Diagram battery- backable Rabbit 4000 Microprocessor User’s Manual...
Page 15: Basic Specifications
1.4 Basic Specifications Table 1-1. Rabbit 4000 Specifications and Features Package 128-pin LQFP 128-ball TFBGA Package Size 16 mm × 16 mm × 1.5 mm 10 mm × 10 mm × 1.2 mm Operating Voltage 1.8 V DC core, 3.3 V DC I/O ring Operating Current 0.35 mA/MHz @ 1.8 V/3.3 V...
Page 16: Comparing Rabbit Microprocessors
1.5 Comparing Rabbit Microprocessors The Rabbit 2000, Rabbit 3000, and Rabbit 4000 features are compared below. Feature Rabbit 4000 Rabbit 3000 Rabbit 2000 Maximum Clock Speed, industrial 60 MHz 55.5 MHz 30 MHz Maximum Clock Speed, commercial 60 MHz 58.8 MHz...
Page 17 Asynch Serial Ports With Support for None IrDA Communication Serial Ports with Support for SDLC/ None HDLC IrDA Communication Maximum Asynchronous Baud Rate Clock Speed/8 Clock Speed/8 Clock Speed/32 Ethernet Port 10Base-T None None Input Capture Units None Chapter 1 The Rabbit 4000 Processor...
Page 18 Rabbit 4000 Microprocessor User’s Manual...
Page 19: Chapter 2. Clocks
LOCKS 2.1 Overview The Rabbit 4000 supports up to three separate clocks—the main clock, the 32 kHz clock, and the 20 MHz Ethernet clock. The main clock is used to derive the processor clock and the peripheral clock inside the processor. The 32 kHz clock is used to drive the asynchro- nous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers.
Page 20: Block Diagram
Register Name Mnemonic I/O Address Reset Global Control/Status Register GCSR 0x0000 11000000 Global Clock Modulator 0 Register GCM0R 0x000A 00000000 Global Clock Modulation 1 Register GCM1R 0x000B 00000000 Global Clock Double Register GCDR 0x000F 00000000 Rabbit 4000 Microprocessor User’s Manual...
Page 21: Dependencies
2.2 Dependencies 2.2.1 I/O Pins The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to remove problems with noise on slowly-transitioning signals. The main clock disable output is on the CLKIEN pin. Its state is changed by one of the bit combinations of bits 4:2 in GCSR.
Page 22: Operation
When the 32 kHz clock is enabled in GCSR, it can be further divided by 2, 4, 6, or 8 to generate even lower frequencies by enabling those modes in bits 0–2 of GPSCR. See Table 2-4 for more details. Rabbit 4000 Microprocessor User’s Manual...
Page 23: Spectrum Spreader
2.3.2 Spectrum Spreader When enabled, the spectrum spreader stretches and compresses the main clock in a complex pattern that spreads the energy of the clock harmonics over a wider range of frequencies. Figure 2-1. Effects of Spectrum Spreader There are three settings that correspond to normal and strong spreading in the 0–50 MHz and >50 MHz main clock range.
Page 24 If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. Rabbit 4000 Microprocessor User’s Manual...
Page 25: Clock Doubler
2.3.3 Clock Doubler The clock doubler allows a lower frequency crystal to be used for the main oscillator and to provide an added range over which the clock frequency can be adjusted. The clock dou- bler is controlled via the Global Clock Double Register (GCDR). The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock.
Page 26 52% / 48%, the clock generated by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. Memory access time is not affected because memory bus cycle is 2 clocks long and includes both a long and a short Rabbit 4000 Microprocessor User’s Manual...
Page 27 clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly The maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler.
Page 28: 32 Khz Clock
If these features are not used in a design, the use of the 32 kHz clock is optional. A simplified version of the recommended oscillator circuit for the Rabbit 4000 is shown below. The values of resistors and capacitors may need to be adjusted for various frequen- cies and crystal load capacitances.
Page 29 The 32 kHz oscillator can be used to drive as the processor and peripheral clock to provide significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided by 2, 4, 8, or 16 to provide clock speeds as low as 2.048 kHz. Special self-timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra-sleepy mode is enabled;...
Page 30: Register Descriptions
Processor clock from the main clock, divided by 6. Peripheral clock from the main clock, divided by 6. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 31 Global Clock Modulator 0 Register (GCM0R) (Address = 0x000A) Bit(s) Value Description Clock dither in 1 ns steps, from 0 ns to 26 ns. Do not modify while the dither function is enabled. Clock dither in 0.5 ns steps, from 0 ns to 13 ns. Clock dither in 2 ns steps, from 0 ns to 52 ns.
Page 32 20 ns nominal low time. 10001 3 ns nominal low time. 10010 4 ns nominal low time. 10011 5 ns nominal low time. other Any bit combination not listed is reserved and must not be used. Rabbit 4000 Microprocessor User’s Manual...
Page 33 STATUS pin is high. /WDTOUT pin functions normally. Enable /WDTOUT for test mode. Rabbit Semiconductor internal use only. /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz). This bit combination is reserved and should not be used.
Page 34 Enable full-duplex operation. If auto-negotiation is disabled, this forces full- duplex operation. If auto-negotiation is enabled, this allows advertising full- duplex capability. This bit is unused and should be written with zero. Rabbit 4000 Microprocessor User’s Manual...
Page 35: Chapter 3. Reset And Bootstrap
Serial Port A or the slave port. In this mode, bytes can be written to internal registers to set up the Rabbit 4000 for a particular configuration, or to memory to load a program. The processor can begin normal operation once the bootstrap operation is completed.
Page 36: Registers
3.2 Dependencies 3.2.1 I/O Pins SMODE0, SMODE1 — When the Rabbit 4000 is first powered up or when it is reset, the state of the SMODE0 and SMODE1 pins controls its operation. /RESET — Pulling the /RESET pin low will initialize everything in the Rabbit 4000 except for the real-time clock registers and the onchip-encryption RAM.
Page 37: Operation
3.3 Operation Pulling the /RESET pin low will initialize everything in the Rabbit 4000 except for the real-time clock registers and the onchip-encryption RAM. The reset of the Rabbit 4000 is delayed until the completion of any write cycles in progress; reset takes effect immedi- ately when no write cycles are occurring.
Page 38 As a security feature, any attempt to enter bootstrap mode from either the SMODE pins or by writing to bit 7 of SPCR will erase the data stored in the onchip-encryption RAM. This prevents loading a small program in memory to read out the data. Rabbit 4000 Microprocessor User’s Manual...
Page 39: Register Descriptions
3.4 Register Descriptions Slave Port Control Register (SPCR) (Address = 0x0024) Bit(s) Value Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. Read These bits report the state of the SMODE pins. Write These bits are ignored and should be written with zero.
Page 40 Rabbit 4000 Microprocessor User’s Manual...
Page 41: Chapter 4. System Management
The 48-bit width provides a 272-year span before rollover occurs. There are two watchdog timers in the Rabbit 4000, both clocked by the 32 kHz clock. The main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the pro- cessor if not reloaded within that time.
Page 42: Block Diagram
Secondary Watchdog Timer Register SWDTR 0x000C 11111111 Global Output Control Register GOCR 0x000E 00000000 Global CPU Configuration Register GCPU 0x002E 0xx00010 Global Revision Register GREV 0x002F 0xx00000 Battery-Backed Onchip-Encryption RAM Byte VRAM00– 0x0600–0x061F xxxxxxxx 00–1F VRAM1F Rabbit 4000 Microprocessor User’s Manual...
Page 43: Dependencies
4.2 Dependencies 4.2.1 I/O Pins The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of these pins can be used as general-purpose outputs by driving them high or low: • the CLK pin can output the peripheral clock, the peripheral clock divided by two, or be driven high or low;...
Page 44: Operation
0x40 – 0xC0 to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time clock. The byte increment mode is disabled by writing 0x00 to RTCCR. Rabbit 4000 Microprocessor User’s Manual...
Page 45: Watchdog Timer
The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing 0x5F to WDTCR. The following steps explain how to use the secondary watchdog timer.
Page 46: Register Descriptions
Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 47 Real-Time Clock Control Register (RTCCR) (Address = 0x0001) Bit(s) Value Description No effect on the real-time clock counter, or disable the byte increment function, 0x00 or cancel the real-time clock reset command. Arm the real-time clock for reset or byte increment. This command must be 0x40 written prior to either the real-time clock reset command or the first byte increment write.
Page 48 The timer counts modulo n + 1, where n is the programmed time constant. The secondary watchdog timer can be disabled by writing the sequence 0x5A – 0x52 – 0x44 to this register. Rabbit 4000 Microprocessor User’s Manual...
Page 49 STATUS pin is high. /WDTOUT pin functions normally. Enable /WDTOUT for test mode. Rabbit Semiconductor internal use only. /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz). This bit combination is reserved and should not be used.
Page 50 Battery-Backed Onchip-Encryption RAM (VRAM00) (Address = 0x0600) through through (VRAM1F) (Address = 0x061F) Bit(s) Value Description General-purpose RAM locations. Cleared by Intrusion Detect conditions. Rabbit 4000 Microprocessor User’s Manual...
Page 51: Chapter 5. Memory Management
ANAGEMENT 5.1 Overview The Rabbit 4000 supports both 8-bit and 16-bit external flash and SRAM devices; three chip selects and two read/write-enable strobes allow up to six external devices to be attached at once. The 8-bit mode allows 0, 1, 2, or 4 wait states to be specified for each device, and the 16-bit mode allows 0 to 9 wait states depending on the settings.
Page 52 64KB logical memory space. Special call and return instructions to physical addresses are provided that automatically update the XPC register as necessary. Figure 5-2. Logical and Physical Memory Mapping Rabbit 4000 Microprocessor User’s Manual...
Page 53: Block Diagram
These two features allow both code and data to access separate 64KB logical spaces instead of sharing a single space. It is possible to protect memory in the Rabbit 4000 at three different levels: each of the memory banks can be made read-only, physical memory can be write-protected in 64KB blocks, and two of those 64KB blocks can be protected with a granularity of 4KB.
Page 54: Registers
Write-Protect Segment B Low Register WPSBLR 0x0485 00000000 Write-Protect Segment B High Register WPSBHR 0x0486 00000000 Stack Limit Control Register STKCR 0x0444 00000000 Stack Low Limit Register STKLLR 0x0445 xxxxxxxx Stack High Limit Register STKHLR 0x0446 xxxxxxxx Rabbit 4000 Microprocessor User’s Manual...
Page 55: Dependencies
5.2 Dependencies 5.2.1 I/O Pins There are three chip select pins: /CS0, /CS1, and /CS2; two read strobes, /OE0 and /OE1; and two write strobes, /WE0 and /WE1. There are eight dedicated data bus pins, D0 through D7. If the 16-bit mode is enabled, then PD0–PD7 automatically act as the upper byte of the data bus, D8 through D15.
Page 56: Operation
The data and stack segment mappings are set by writing to the appropriate register, as shown in Table 5-1. The DATASEG and STACKSEG registers provide backwards compatibility to the Rabbit 2000 and 3000 processors; these registers map directly to DATASEGL and STACKSEGL but the corresponding uppermost four bits are set to zero.
Page 57: 8-Bit Operation
Figure 5-3. MMU Operation 5.3.2 8-bit Operation On startup Memory Bank 0 is enabled to use /CS0, /OE0, and /WE0 with four wait states and write protection enabled; it is expected that an external flash device containing startup code be attached to those strobes. The other memory banks come up undefined and should be set via the appropriate MBxCR register to a valid setting before use.
Page 58 It is possible to force /CS1 to be always active in MMIDR; enabling this will cause con- flicts only if a device shares a /OE or /WE strobe with another device. This option allows faster access to particular memory devices. Rabbit 4000 Microprocessor User’s Manual...
Page 59: 16-Bit And
5.3.3 16-bit and Page Modes The Rabbit 4000 supports two additional memory modes to access both 16-bit and page- mode devices on /CS0 and /CS1, and can be enabled by writing to MACR. The first mode supports a 16-bit memory device in addition to the normal 8-bit memory devices. With this option, the memory device connected to /CS0 or /CS1 (or both) is assumed to have a 16-bit data path.
Page 60 Page-mode memories provide for a faster access time if the requested data is in the same page as the previous data. In the Rabbit 4000 (and most memory devices) a page is 16 bytes. Thus, if an address is identical to the previous address except in the lower four bits, the access time is assumed to be faster.
Page 61 Page Mode. The third setting selects from five to nine automatic wait states for memory-write bus cycles. The choices available for the advanced bus wait states are suffi- cient to allow interfacing to a variety of standard memories for any Rabbit 4000 speed grade.
Page 62: Separate Instruction And Data Space
It provides a “window” that uses the instruction address decoding when read or written as data. The Rabbit 4000 Designer’s Handbook provides further details on the use of the separate instruction and data space feature. 5.3.5 Memory Protection Memory blocks may be protected at three separate granularities, as shown in Table 5-4.
Page 63: Register Descriptions
5.4 Register Descriptions MMU Instruction/Data Register (MMIDR) (Address = 0x0010) Bit(s) Value Description Internal I/O addresses are decoded using only the lower eight bits of the internal I/O address bus. This restricts internal I/O addresses to the range 0x0000– 0x00FF. Internal I/O addresses are decoded using all 15 bits of the address internal I/O address bus.
Page 64 Bit(s) Value Description These bits are reserved and should always be written as zero. These bits always return zeros when read. Four MSBs of physical address offset to use if: SEGSIZ[3:0] <= Addr[15:12] < SEGSIZ[7:4] Rabbit 4000 Microprocessor User’s Manual...
Page 65 Segment Size Register (SEGSIZ) (Address = 0x0013) Bit(s) Value Description Read The current contents of this register are reported. Write Boundary value for switching from DATSEG to STKSEG for translation. Write Boundary value for switching from none to DATSEG for translation. Memory Bank x Control Register (MB0CR) (Address = 0x0014)
Page 66 Extended timing for /WE1 (falling edge to falling edge, two clocks minimum). Normal timing for /WE0 (rising edge to falling edge, one and one-half clocks minimum). Extended timing for /WE0 (falling edge to falling edge, two clocks minimum). Rabbit 4000 Microprocessor User’s Manual...
Page 67 Memory Alternate Control Register (MACR) (Address = 0x001D) Bit(s) Value Description These bits are reserved and must not be used. Normal 8-bit operation for /CS1. Use MBxCR for wait states unless Page Mode. Advanced 16-bit operation for /CS1. Enable prefetch mechanism for instructions and word-write accelerator for 16-bit write operations.
Page 68 Disable RAM segment limit checking. Select data-type MMU translation if PC[15:10] is equal to RAMSR[7:2]. Select data-type MMU translation if PC[15:11] is equal to RAMSR[7:3]. Select data-type MMU translation if PC[15:12] is equal to RAMSR[7:4]. Rabbit 4000 Microprocessor User’s Manual...
Page 69 Write Protection Control Register (WPCR) (Address = 0x0440) Bit(s) Value Description These bits are reserved and should be written with zeros. Write protection in User Mode only. Write protection in System and User modes. Chapter 5 Memory Management...
Page 70 Each write-protect register controls 8 64K blocks. Now that you have the register address, you need to know that the register bit selects the correct 64K block. This is calculated using blk64, a value between 0–255. bitnum = blk64 & 0x7 Rabbit 4000 Microprocessor User’s Manual...
Page 71 Write-Protect Segment x Register (WPSAR) (Address = 0x0480) (WPSBR) (Address = 0x0484) Bit(s) Value Description When these eight bits [23:16] match bits of the physical address, write-protect that 64K range in 4K increments using WPSxLR and WPSxHR. Write-Protect Segment x Low Register (WPSALR) (Address = 0x0481) (WPSBLR)
Page 72 (Address = 0x0445) Bit(s) Value Description Lower limit for stack-limit checking. If a stack operation or stack-relative memory access is attempted at an address less than {STKLLR, 0x10}, a stack- limit violation interrupt is generated. Rabbit 4000 Microprocessor User’s Manual...
Page 73 Stack High Limit Register (STKHLR) (Address = 0x0446) Bit(s) Value Description Upper limit for stack-limit checking. If a stack operation or stack-relative memory access is attempted at an address greater than {STKHLR, 0xEF}, a stack-limit violation interrupt is generated. Chapter 5 Memory Management...
Page 74 Rabbit 4000 Microprocessor User’s Manual...
Page 75: Chapter 6. Interrupts
NTERRUPTS 6.1 Overview The Rabbit 4000 can operate at one of four priority levels, 0–3, with Priority 0 being the expected standard operating level. The current priority and up to three previous priority levels are kept in the processor’s 8-bit IP register, where bits 0–1 contain the current priority.
Page 76: Operation
Input Capture 0xB0 Timer B Stack Limit Violation 0xC0 Serial Port A Serial Port E 0xD0 Serial Port B Serial Port F 0xE0 Serial Port C Network Port A 0xF0 Serial Port D Timer C Rabbit 4000 Microprocessor User’s Manual...
Page 77 Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector falls on a 16-byte boundary inside the table. Table 6-2. External Interrupt Vector Table Structure Offset 0x0000+ 0x00 External Interrupt 0 0x10 External Interrupt 1 0x20 —...
Page 78 Serial Port C Tx: Write to SCDR, SCAR, SCLR or dummy write to SCSR. Rx: Read from SDDR or SDAR. Lowest Serial Port D Tx: Write to SDDR, SDAR, SDLR or dummy write to SDSR. Rabbit 4000 Microprocessor User’s Manual...
Page 79: Chapter 7. External Interrupts
The signal on the external interrupt pin must be present for at least three peripheral clock cycles to be detected. In addition, the Rabbit 4000 has a minimum latency of 10 clocks to respond to an interrupt, so the minimum external interrupt response time is three periph- eral clock cycles plus 10 processor clock cycles.
Page 80: Registers
7.3.1 I/O Pins The external interrupts can be enabled on pins PD0, PD1, PE0, PE1, PE4, and PE5. Each pin is associated with a particular interrupt vector as shown in Table 7-1 below. Table 7-1. Rabbit 4000 Interrupt Vectors Vector Register...
Page 81: Register Descriptions
7.5 Register Descriptions Interrupt x Control Register (I0CR) (Address = 0x0098) (I1CR) (Address = 0x0099) Bit(s) Value Description Parallel Port D low nibble interrupt disabled. Parallel Port D low nibble interrupt on falling edge. Parallel Port D low nibble interrupt on rising edge. Parallel Port D low nibble interrupt on both edges.
Page 82 Rabbit 4000 Microprocessor User’s Manual...
Page 83: Chapter 8 Parallel Port A
8. P ARALLEL 8.1 Overview Parallel Port A is a byte-wide port that can be used as an input or an output port. Parallel Port A is also used as the data bus for the slave port and auxiliary I/O bus. The Slave Port Control Register (SPCR) is used to configure how Parallel Port A is used.
Page 84: Dependencies
Parallel Port A is not available for general-purpose I/O while the slave port or the auxiliary I/O bus is selected. Selecting these options for Parallel Port A affects Parallel Port B because Parallel Port B is then used for address and control signals. Rabbit 4000 Microprocessor User’s Manual...
Page 85: Register Descriptions
8.4 Register Descriptions Parallel Port A Data Register (PADR) (Address = 0x0030) Bit(s) Value Description Read The current state of Parallel Port A pins PA7–PA0 is reported. The Parallel Port A buffer is written with this value for transfer to the Parallel Write Port A output register on the next rising edge of the peripheral clock.
Page 86 Rabbit 4000 Microprocessor User’s Manual...
Page 87: Chapter 9 Parallel Port B
9. P ARALLEL 9.1 Overview Parallel Port B is a byte-wide port with each bit programmable for direction. The Parallel Port B pins are also used to access other peripherals on the chip—the slave port, the auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B.
Page 88: Block Diagram
I/O bus; as control signals for the slave port; or as clocks for Serial Ports A and B. On startup, bits 6 and 7 are outputs set low for backwards compatibility with the Rabbit 2000. All other pins are inputs.
Page 89: Interrupts
9.2.4 Interrupts There are no interrupts associated with Parallel Port B. 9.3 Operation The following steps must be taken before using Parallel Port B. 1. Select the desired input/output direction for each pin via PBDDR. Note that this setting is superseded for some pins if the slave port or auxiliary I/O bus is enabled in SPCR or if the clocked serial mode is enabled for serial ports A or B.
Page 90 Enable the auxiliary I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 91: Chapter 10. Parallel Port C
10. P ARALLEL 10.1 Overview Parallel Port C is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port C Data Reg- ister (PCDR). All the Parallel Port C pins have alternate output functions, and most of them can be used as inputs to various on-chip peripherals.
Page 92: Block Diagram
(the odd-numbered bits). For compatibility with the Rabbit 2000 and the Rabbit 3000 microprocessors, these outputs are driven with a logic zero (low) on PC6 and a logic one (high) on PC4, PC2, and PC0. When PCDR is read, the value of the volt- age on the pin is returned.
Page 93: Dependencies
The input capture peripheral can also watch pins PC7, PC5, PC3, and PC1. On startup, PC4, PC2, and PC0 are outputs set high, PC6 is set low, and the other pins are inputs for compatibility with the Rabbit 3000. The individual pins can be set to be open-drain via PCDCR.
Page 94: Register Descriptions
Parallel Port C bit 0 alternate output 0 (TXD). Parallel Port C bit 0 alternate output 1 (I0). Parallel Port C bit 0 alternate output 2 (TIMER C0). Parallel Port C bit 0 alternate output 3 (TCLKF). Rabbit 4000 Microprocessor User’s Manual...
Page 95 Parallel Port C Alternate High Register (PCAHR) (Address = 0x0053) Bit(s) Value Description Parallel Port C bit 7 alternate output 0 (TXA). Parallel Port C bit 7 alternate output 1 (I7). Parallel Port C bit 7 alternate output 2 (PWM3). Parallel Port C bit 7 alternate output 3 (SCLKC).
Page 96 Rabbit 4000 Microprocessor User’s Manual...
Page 97: Chapter 11 Parallel Port D
11. P ARALLEL 11.1 Overview Parallel Port D is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port D Data Register (PDDR). All of the Parallel Port D pins have alternate output functions, and all of them can be used as inputs to various on-chip peripherals.
Page 98 — — — × RCLKE — — — — — TCLKE — — — × DREQ1 — QRD2A — SCLKC — DREQ0 — QRD2B × RCLKF — INT1 QRD1A — SCLKD TCLKF — INT0 QRD1B Rabbit 4000 Microprocessor User’s Manual...
Page 99: Block Diagram
11.1.1 Block Diagram Chapter 11 Parallel Port D...
Page 100: Registers
All outputs on Parallel Port D are clocked by the peripheral clock unless changed in PDCR, where the option of updating the Parallel Port D pins can be synchronized to the output of Timer A1, Timer B1, or Timer B2. Rabbit 4000 Microprocessor User’s Manual...
Page 101: Other Registers
11.2.3 Other Registers Register Function SACR, SBCR, SCCR, Select a Parallel Port D pin as serial data (and SDCR, SECR, SFCR optional clock) input. Select a Parallel Port D pin as a start/stop condition ICS1R, ICS2R input. QDCR Select a Parallel Port D pin as a decoder input. Select a Parallel Port D pin as an external interrupt I0CR, I1CR input.
Page 102: Register Descriptions
Parallel Port D bit 0 alternate output 0 (SCLKD). Parallel Port D bit 0 alternate output 1 (I0). Parallel Port D bit 0 alternate output 2 (TIMER C0). Parallel Port D bit 0 alternate output 3 (TCLKF). Rabbit 4000 Microprocessor User’s Manual...
Page 103 Parallel Port D Alternate High Register (PDAHR) (Address = 0x0063) Bit(s) Value Description Parallel Port D bit 7 alternate output 0 (IA7). Parallel Port D bit 7 alternate output 1 (I7). Parallel Port D bit 7 alternate output 2 (PWM3). Parallel Port D bit 7 alternate output 3 (SCLKC).
Page 104 These bits are ignored. The port buffer (bit 1) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock Rabbit 4000 Microprocessor User’s Manual...
Page 105 Parallel Port D Bit 2 Register (PDB2R) (Address = 0x006A) Bit(s) Value Description 7:3,1:0 These bits are ignored. The port buffer (bit 2) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port D Bit 3 Register (PDB3R)
Page 106 These bits are ignored. The port buffer (bit 7) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock Rabbit 4000 Microprocessor User’s Manual...
Page 107: Chapter 12 Parallel Port E
12. P ARALLEL 12.1 Overview Parallel Port E is a byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port E Data Register (PEDR). All of the Parallel Port E pins have alternate output functions, and all of them can be used as inputs to various on-chip peripherals.
Page 108 INT1 — — — — TCLKE — INT0 — — × DREQ1 — QRD2A — — SCLKC — DREQ0 — QRD2B — × RCLKF — INT1 QRD1A — — SCLKD TCLKF — INT0 QRD1B — Rabbit 4000 Microprocessor User’s Manual...
Page 109: Block Diagram
12.1.1 Block Diagram Chapter 12 Parallel Port E...
Page 110: Registers
All outputs on Parallel Port E are clocked by the peripheral clock unless changed in PECR, where the option of updating the Parallel Port E pins can be synchronized to the output of Timer A1, Timer B1, or Timer B2. Rabbit 4000 Microprocessor User’s Manual...
Page 111: Other Registers
12.2.3 Other Registers Register Function SACR, SBCR, SCCR, Select a Parallel Port E pin as serial data (and SDCR, SECR, SFCR optional clock) input. Select a Parallel Port E pin as a start/stop condition ICS1R, ICS2R input. QDCR Select a Parallel Port E pin as a decoder input. Select a Parallel Port E pin as an external interrupt I0CR, I1CR input.
Page 112: Register Descriptions
Parallel Port E bit 0 alternate output 0 (I0). Parallel Port E bit 0 alternate output 1 (A20). Parallel Port E bit 0 alternate output 2 (TIMER C0). Parallel Port E bit 0 alternate output 3 (TCLKF). Rabbit 4000 Microprocessor User’s Manual...
Page 113 Parallel Port E Alternate High Register (PEAHR) (Address = 0x0073) Bit(s) Value Description Parallel Port E bit 7 alternate output 0 (I7). Parallel Port E bit 7 alternate output 1 (/ACT). Parallel Port E bit 7 alternate output 2 (PWM3). Parallel Port E bit 7 alternate output 3 (SCLKC).
Page 114 These bits are ignored. The port buffer (bit 1) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock Rabbit 4000 Microprocessor User’s Manual...
Page 115 Parallel Port E Bit 2 Register (PEB2R) (Address = 0x007A) Bit(s) Value Description 7:3,1:0 These bits are ignored. The port buffer (bit 2) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 3 Register (PEB3R)
Page 116 These bits are ignored. The port buffer (bit 7) is written with the value of this bit. The port buffer will be Write transferred to the port output register on the next rising edge of the peripheral clock Rabbit 4000 Microprocessor User’s Manual...
Page 117: Chapter 13 Timer A
Timers A2–A7 can be used to generate baud rates for Serial Ports A–F, or they can be used as general-purpose timers if the dedicated timers on the Rabbit 4000 serial ports are used. The three remaining timers (A8–A10) serve as prescalers for the input capture, PWM, and quadrature decoder peripherals respectively.
Page 118 After these bits are cleared, they cannot cause an interrupt. The proper rule to follow is for the interrupt routine to handle all bits that it sees set. Rabbit 4000 Microprocessor User’s Manual...
Page 119: Block Diagram
13.1.1 Block Diagram Chapter 13 Timer A...
Page 120: Registers
The timers in Timer A can be clocked by either perclk or perclk/2, as selected in TAPR. In addition, timers A2–A7 can be clocked by the output of timer A1 by selecting that option in TACSR. 13.2.3 Other Registers Register Function GCSR Select peripheral clock mode. Rabbit 4000 Microprocessor User’s Manual...
Page 121: Interrupts
13.2.4 Interrupts A Timer A interrupt can be generated whenever timers A1–A7 decrement to zero by enabling the appropriate bit in TACSR. The interrupt request is cleared when TACSR is read. The Timer A interrupt vector is in the IIR at offset 0x0A0. It can be set as priority 1, 2, or 3 in TACR.
Page 122: Register Descriptions
These bits are reserved and should be written with zero. The main clock for Timer A is the peripheral clock (perclk). The main clock for Timer A is the peripheral clock divided by two (perclk/2). Rabbit 4000 Microprocessor User’s Manual...
Page 123 Timer A Control Register (TACR) (Address = 0x00A4) Bit(s) Value Description Timer A7 clocked by the main Timer A clock. Timer A7 clocked by the output of Timer A1. Timer A6 clocked by the main Timer A clock. Timer A6 clocked by the output of Timer A1. Timer A5 clocked by the main Timer A clock.
Page 124 Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Rabbit 4000 Microprocessor User’s Manual...
Page 125: Chapter 14 Timer B
14. T IMER 14.1 Overview The Timer B peripheral consists of a ten-bit free running up-counter, two match registers, and two step registers. Timer B is driven by perclk/2, by perclk/16, or by the output of timer A1. Timer B generates an output pulse whenever the counter reaches the match value.
Page 126: Registers
Select peripheral clock mode. 14.2.4 Interrupts A Timer B interrupt can be generated whenever the counter equals one of the match registers by enabling the appropriate bit in TBCSR. The interrupt request is cleared when TBCSR is read. Rabbit 4000 Microprocessor User’s Manual...
Page 127: Operation
14.3 Operation The following steps explain how to set up a Timer B countdown timer. 1. Select perclk/2, perclk/16, or countdown timer A1 in TBCR. 2. Use TBCR to select whether countdown timers B1–B2 operate normally with the match registers or whether they use the step registers to calculate match values. 3.
Page 128: Register Descriptions
Timer B clocked by main Timer B clock divided by 8 (perclk/16). Timer B interrupts are disabled. Timer B interrupt use Interrupt Priority 1. Timer B interrupt use Interrupt Priority 2. Timer B interrupt use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 129 Timer B Count MSB x Register (TBM1R) (Address = 0x00B2) (TBM2R) (Address = 0x00B4) Bit(s) Value Description Two MSBs of the compare value for the Timer B comparator. This compare value will be loaded into the actual comparator when the current compare detects a match.
Page 130 Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Rabbit 4000 Microprocessor User’s Manual...
Page 131: Chapter 15 Timer C
15. T IMER 15.1 Overview The Timer C peripheral is a 16-bit up-counter clocked by the peripheral clock divided by 2, by the peripheral clock divided by 16, or by the output of countdown timer A1. The counter counts from zero to the limit programmed into the Timer C divider registers and then restarts at zero, so the overall cycle count is the value in the divider registers plus one.
Page 132: Block Diagram
15.1.1 Block Diagram Rabbit 4000 Microprocessor User’s Manual...
Page 133: Registers
15.1.2 Registers Register Name Mnemonic I/O Address Reset Timer C Control/Status Register TCCSR 0x0500 xxxx0000 Timer C Control Register TCCR 0x0501 xx000000 Timer C Divider Low Register TCDLR 0x0502 00000000 Timer C Divider High Register TCDHR 0x0503 00000000 Timer C Set 0 Low Register TCS0LR 0x0508 xxxxxxxx...
Page 134: Dependencies
Alternate port output selection PEFR, PEALR 15.2.4 Interrupts A Timer C interrupt is enabled in TCCR, and will occur whenever the count limit value is reached. The interrupt request is cleared when TCCSR is read. Rabbit 4000 Microprocessor User’s Manual...
Page 135: Operation
15.3 Operation The following steps explain how to set up a Timer C timer. 1. Select perclk/2, perclk/16, or countdown timer A1 in TCCR. 2. Load the desired upper limit for the counter into TCDLR and TCDHR. The overall clock count per Timer C cycle will be the value loaded into the divider registers plus one.
Page 136: Register Descriptions
The eight LSBs of the divider limit value for Timer C are stored. Timer C Divider High Register (TCDHR) (Address = 0x0503) Bit(s) Value Description The eight MSBs of the divider limit value for Timer C are stored. Rabbit 4000 Microprocessor User’s Manual...
Page 137 Timer C Set x Low Register (TCS0LR) (Address = 0x0508) (TCS1LR) (Address = 0x050C) (TCS2LR) (Address = 0x0518) (TCS3LR) (Address = 0x051C) Bit(s) Value Description Eight LSBs of the match value to set Timer C Output x. Timer C Set x High Register (TCS0HR) (Address = 0x0509) (TCS1HR)
Page 138 Processor clock from the main clock, divided by four. Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. Peripheral clock from the main clock, divided by six. Rabbit 4000 Microprocessor User’s Manual...
Page 139: Chapter 16 Serial Ports A - D
16. S A – D ERIAL ORTS 16.1 Overview Serial Ports A, B, C, and D are identical, except for the source of the data clock and the transmit, receive, and clock pins. Serial Port A is special because it can be used to boot- strap the processor.
Page 140 When Serial Port A is used in the asynchronous bootstrap mode, the 32 kHz clock is used to generate the expected 2400 bps data rate. An external clock must be supplied for the clocked serial bootstrap mode. Rabbit 4000 Microprocessor User’s Manual...
Page 141: Block Diagram
The behavior of the serial port during a break (line held low) is configurable; character assembly can continue during the break condition to allow for timing the break, or charac- ter assembly can be inhibited to reduce the interrupt overhead. 16.1.1 Block Diagram Chapter 16 Serial Ports A –...
Page 142: Registers
0xx00000 Serial Port D Control Register SDCR 0x00F4 xx000000 Serial Port D Extended Register SDER 0x00F5 00000000 Serial Port D Divider Low Register SDDLR 0x00F6 xxxxxxxx Serial Port D Divider High Register SDDHR 0x00F7 0xxxxxxx Rabbit 4000 Microprocessor User’s Manual...
Page 143: Dependencies
16.2 Dependencies 16.2.1 I/O Pins Serial Port A can transmit on parallel port pins PC7, PC6, or PD6, and can receive on pins PC7, PD7, or PE7. If the clocked serial mode is enabled, the serial clock is either transmit- ted or received on PB1.
Page 144: Clocks
• Serial Port C at offset 0x0E0 • Serial Port D at offset 0x0F0 Each of them can be set as Priority 1, 2, or 3 in SxCR, where x is A – D for the four serial ports. Rabbit 4000 Microprocessor User’s Manual...
Page 145: Operation
16.3 Operation 16.3.1 Asynchronous Mode The following steps explain how to set up Serial Ports A – D for asynchronous operation. The serial ports can be used by polling the status byte, but their performance will be better with an interrupt. These instructions also apply to the asynchronous operation of Serial Ports E –...
Page 146: Clocked Serial Mode
The following steps explain how to set up Serial Ports A – D for the clocked serial mode. When the internal clock is selected, the Rabbit 4000 is in control of all transmit and receive operations. When an external clock is selected the other device controls all trans- mit and receive operation.
Page 147 A sample clocked serial interrupt handler is shown below for Serial Port B. clocked_serb_isr:: push af ; save used registers ioi ld a, (SASR) ; get status bit a,7 ; check if byte ready in RX buffer push af ; save status for next check z, check_for_tx rx_ready: ioi ld a, (SADR)
Page 148: Register Descriptions
(Address = 0x00E0) (SDLR) (Address = 0x00F0) Bit(s) Value Description Read Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a “one” address bit, Write for transmission. Rabbit 4000 Microprocessor User’s Manual...
Page 149 Serial Port x Status Register (SASR) (Address = 0x00C3) (Asynchronous Mode Only) (SBSR) (Address = 0x00D3) (SCSR) (Address = 0x00E3) (SDSR) (Address = 0x00F3) Bit(s) Value Description The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set.
Page 150 The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in the clocked serial mode. Rabbit 4000 Microprocessor User’s Manual...
Page 151 Serial Port x Control Register (SACR) (Address = 0x00C4) (SBCR) (Address = 0x00D4) (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) Bit(s) Value Description No operation. These bits are ignored in the asynchronous mode. In the clocked serial mode, start a byte-receive operation. In the clocked serial mode, start a byte-transmit operation.
Page 152 Continue character assembly during break to allow timing the break condition. Inhibit character assembly during break. One character (all zeros, with framing error) at start and one character (garbage) at completion. This bit is ignored in the asynchronous mode. Rabbit 4000 Microprocessor User’s Manual...
Page 153 Serial Port x Extended Register (SAER) (Address = 0x00C5) (Clocked Serial Mode Only) (SBER) (Address = 0x00D5) (SCER) (Address = 0x00E5) (SDER) (Address = 0x00F5) Bit(s) Value Description Normal clocked serial operation. Timer-synchronized clocked serial operation. Timer-synchronized clocked serial uses Timer B1. Timer-synchronized clocked serial uses Timer B2.
Page 154 Enable the serial port divider, and use its output to clock the serial port. The serial port divider counts modulo n + 1 and is clocked by the peripheral clock. Seven MSBs of the divider that generates the serial clock for this channel. Rabbit 4000 Microprocessor User’s Manual...
Page 155: Chapter 17 Serial Ports E - F
17. S E – F ERIAL ORTS 17.1 Overview Serial Ports E and F are identical to each other, and their asynchronous operation is identi- cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes, and the transmit, receive, and clock pins.
Page 156: Block Diagram
For more on the clock synchro- nization and data encoding, see Section 17.3.3. 17.1.1 Block Diagram Rabbit 4000 Microprocessor User’s Manual...
Page 157: Registers
17.1.2 Registers Register Name Mnemonic I/O Address Reset Serial Port E Data Register SEDR 0x00C8 xxxxxxxx Serial Port E Address Register SEAR 0x00C9 xxxxxxxx Serial Port E Long Stop Register SELR 0x00CA xxxxxxxx Serial Port E Status Register SESR 0x00CB 0xx00000 Serial Port E Control Register SECR...
Page 158: Dependencies
17.2.3 Other Registers Register Function TAT2R Time constant for Serial Port E TAT3R Time constant for Serial Port F PCFR, PCAHR, PCALR PDFR, PDAHR, PDALR Alternate port output selection PEFR, PEAHR, PEALR Rabbit 4000 Microprocessor User’s Manual...
Page 159: Interrupts
17.2.4 Interrupts In the asynchronous mode, a serial port interrupt can be generated whenever a byte is available in the receive buffer or when a byte is finished being transmitted out of the trans- mit buffer. In the HDLC mode, interrupts are also generated by the reception of an end-of- frame (with abort, valid CRC, or CRC error), at the end of a transmission of a CRC, by an abort sequence, or by a closing flag.
Page 160: Operation
The following steps explain how to set up Serial Ports E – F for the HDLC mode. When the internal clock is selected, the Rabbit 4000 is in control of all transmit and receive operations, so an interrupt is not required. When an external clock is selected, operations can be han- dled by either polling the status byte or by a serial port interrupt;...
Page 161: More On Clock Synchronization And Data Encoding
A sample HDLC interrupt handler is shown below for Serial Port E. hdlc_sere_isr:: push af ioi ld a, (SESR) ; get status bit a,7 ; check if byte ready in RX buffer push af ; save status for next check z, check_for_tx rx_ready: ;...
Page 162 DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If the transition occurs later than expected, it means that the bit-cell boundaries are late with Rabbit 4000 Microprocessor User’s Manual...
Page 163 respect to the DPLL-tracked bit-cell boundaries, so the count is lengthened by either one or two counts. The decision to adjust by one or by two depends on how far off the DPLL- tracked bit cell boundaries are. This tracking allows for minor differences in the transmit and receive clock frequencies.
Page 164 Decoding biphase-level data requires that the data be sampled at either the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to sample the data. Rabbit 4000 Microprocessor User’s Manual...
Page 165: Register Descriptions
Biphase-mark encoding and biphase-space encoding are identical as far as the DPLL is concerned, and are similar to biphase-level encoding. The primary difference is the place- ment of the clock and data transitions. With these encodings the clock transitions are at the bit-cell boundary, the data transitions are at the center of the bit cell, and the DPLL opera- tion is adjusted accordingly.
Page 166 The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. These bits are always zero in async mode. Rabbit 4000 Microprocessor User’s Manual...
Page 167 Serial Port x Status Register (SESR) (Address = 0x00CB) (HDLC Mode Only) (SFSR) (Address = 0x00DB) Bit(s) Value Description The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set.
Page 168 If necessary, the receiver and transmitter clocks can be output via parallel port pins. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 169 Serial Port x Extended Register (SEER) (Address = 0x00CD) (Asynchronous Mode Only) (SFER) (Address = 0x00DD Bit(s) Value Description Disable parity generation and checking. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used. This bit combination is reserved and should not be used.
Page 170 Enable the serial port divider, and use its output to clock the serial port. The serial port divider counts modulo n + 1 and is clocked by the peripheral clock. Seven MSBs of the divider that generates the serial clock for this channel. Rabbit 4000 Microprocessor User’s Manual...
Page 171: Chapter 18. Slave Port
18. S LAVE 18.1 Overview The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output regis- ters, and a status register. The data input registers are written by the master (the external device) and are read by the processor.
Page 172: Block Diagram
Slave Port Data 0 Register SPD0R 0x0020 xxxxxxxx Slave Port Data 1 Register SPD1R 0x0021 xxxxxxxx Slave Port Data 2 Register SPD2R 0x0022 xxxxxxxx Slave Port Status Register SPSR 0x0023 00000000 Slave Port Control Register SPCR 0x0024 0xx00000 Rabbit 4000 Microprocessor User’s Manual...
Page 173: Dependencies
18.2 Dependencies 18.2.1 I/O Pins When the slave port is enabled by writing to SPCR, the following pins are enabled for slave port mode. Note that enabling the slave port mode will override any general-purpose I/O or auxiliary I/O bus settings for these pins; when the slave port is enabled they will perform slave port functionality.
Page 174: Operation
18.3 Operation Figure 18-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves. Figure 18-1. Master/Slave Port Connections Rabbit 4000 Microprocessor User’s Manual...
Page 175: Master Setup
/SLVATTN (from Slave #2) Note that the slave port on the master Rabbit processor is not used; the master uses the data bus to send and receive data to the slave port data registers on the slave devices. In this setup, pins PD6 and PD7 are set up as I/O strobe chip selects for the two slave devices, and PE0 and PE1 are used as external interrupt inputs to monitor the /SLVATTN signals from the slaves.
Page 176: Master/Slave Communication
(SPD1R), a ld a, (to_mas_d0) ioi ld (SPD0R), a ; this write asserts /SLVATTN ; the interrupt request is cleared by any read/write of the registers pop af ; restore used registers ipres Rabbit 4000 Microprocessor User’s Manual...
Page 177: Other Configurations
18.3.7 Other Configurations There are other slave port configurations possible: • The master could use the auxiliary I/O bus instead of the memory bus. • All devices could poll the slave port status register to determine when data is present instead of relying on interrupts.
Page 178: Timing Diagrams
18.3.8 Timing Diagrams Figure 18-2 shows the sequence of events when the master reads/writes the slave port registers. Slave Port Read Cycle Slave Port Write Cycle Figure 18-2. Slave Port R/W Timing Diagram Rabbit 4000 Microprocessor User’s Manual...
Page 179 The following table explains the parameters used in Figure 18-2. Minimum Maximum Symbol Parameter (ns) (ns) Tsu(SCS) /SCS Setup Time — Th(SCS) /SCS Hold Time — Tsu(SA) SA Setup Time — Th(SA) SA Hold Time — Tw(SRD) /SRD Low Pulse Width —...
Page 180: Register Descriptions
Slave port write byte 2 is full. Slave port write byte 1 is empty. Slave port write byte 1 is full. Slave port write byte 0 is empty. Slave port write byte 0 is full. Rabbit 4000 Microprocessor User’s Manual...
Page 181 Slave Port Control Register (SPCR) (Address = 0x0024) Bit(s) Value Description Program fetch as a function of the SMODE pins. Ignore the SMODE pins program fetch function. Read These bits report the state of the SMODE pins. Write These bits are ignored and should be written with zero. Disable the slave port.
Page 182 Rabbit 4000 Microprocessor User’s Manual...
Page 183: Chapter 19. Dma Channels
HANNELS 19.1 Overview There are eight independent DMA channels on the Rabbit 4000. All eight channels are identical, and are capable of transferring data to or from memory, external I/O, or internal I/O. The priority between the channels can be either fixed or rotating, and the DMA use of the bus can be limited to guarantee interrupt latency or CPU throughput.
Page 184 CPU operating level, DMA transfers will occur on demand. When the CPU operating level is greater than the programmed DMA operating level, no DMA transfers can occur. This allows interrupt services routines, or other critical Rabbit 4000 Microprocessor User’s Manual...
Page 185: Block Diagram
DMA transfer request will be resolved in favor of the DMA transfer request. The DMA and Ethernet peripherals were optimized to work together; if the Rabbit 4000’s built-in Ethernet peripheral is used it is expected that two DMA channels will be dedicated for that purpose.
Page 186: Registers
DyLA1R 0x01zD (z = y + 8) R/W xxxxxxxx DMA y Link Address [23:16] Register DyLA2R 0x01zE (z= y + 8) xxxxxxxx NOTE: The y in “DMA y …” expresses the DMA channel number (0–7). Rabbit 4000 Microprocessor User’s Manual...
Page 187: Dependencies
19.2 Dependencies 19.2.1 I/O Pins External DMA Request 0 can be enabled from pins PD2, PE2, or PE6. External DMA Request 1 can be enabled from pins PD3, PE3, or PE7. The DMA can use either the memory management unit or the auxiliary I/O bus to perform its transfers, and so will use the appropriate pins for each operation.
Page 188: Operation
6. Select a byte to terminate the transfer on by writing to the appropriate DyTBR and DyTMR registers. 7. The desired control, length, and address registers should be written to a buffer descrip- tor (or descriptors) in memory if not done already. Rabbit 4000 Microprocessor User’s Manual...
Page 189: Handling Interrupts
19.3.3 DMA Priority with the Processor Since the Rabbit 4000 DMA uses the memory management unit to perform transfers, normal code execution cannot occur while the DMA is active. This includes handling interrupts, so it is important to limit the amount of time that the DMA can operate.
Page 190 The total number of clocks listed in Table 19-3 is related to the number of bystes per burst by the following formula. Total Clocks = 4 × Number of Bytes per Burst + 7 (for overhead) Rabbit 4000 Microprocessor User’s Manual...
Page 191: Dma Channel Priority
It is possible to control the priority between separate DMA channels. There are three channel-priority options in the Rabbit 4000. The first is fixed priority after every byte where the priority of each channel is equal to its number, i.e., if both DMA Channels 3 and 4 have a pending transfer request, DMA Channel 4 will always be enabled first.
Page 192: Single Buffer
The simplest version of the buffer array is a double buffer, which is frequently used to provide a reserve buffer in case the application is slow in handling the first buffer once received (in this case, both buffers are enabled to interrupt on completion). Rabbit 4000 Microprocessor User’s Manual...
Page 193: Linked List
19.3.5.3 Linked List A linked list is similar to a buffer array, except that 16-byte descriptors are used and the descriptors are not necessarily adjacent in memory. The advantage of this mode is the ability to spread descriptors. Chapter 19 DMA Channels...
Page 194: Circular Queue
(which can be located anywhere in memory). This method could be useful where a message is broken down into separate transfers, but entire messages could be scattered/gathered from anywhere in memory. Rabbit 4000 Microprocessor User’s Manual...
Page 195: Dma With Peripherals
19.3.6 DMA with Peripherals When the DMA is directed towards an internal I/O address, the DMA transfer request signals will be connected as appropriate for that peripheral. For example, when a DMA transfer is performed to Serial Port D’s data register, the transfer request will be enabled whenever the serial port transmit buffer is empty, and will be disabled whenever it is not.
Page 196: Dma/Block Copy Interaction
• Make sure that the DMA will not return to this channel before the transmitter has sent one byte from the transmit FIFO. • Place the end-of-frame byte in a separate DMA buffer. The Ethernet driver provided by Rabbit Semiconductor in Dynamic C is written so that this bug never occurs. 19.3.8 DMA/Block Copy Interaction When a DMA transfer occurs during a block copy instruction (LDIR, LDDR, COPY, COPYR, UMA, or UMS) while executing code out of 16-bit memory with the “advanced...
Page 197: Register Descriptions
19.4 Register Descriptions DMA Master Control/Status Register (DMCSR) (Address = 0x0100) Bit(s) Value Description No effect on the corresponding DMA channel. Start (or restart) the corresponding DMA channel using the contents of the DMA (Write- channel registers. This command should only be issued after all the DMA only) channel registers (source, destination, length, and link if applicable) have been loaded.
Page 198 DMA transfers at Priority 2. No DMA transfers while CPU operates at Priority 3. DMA transfers at Priority 3. DMA transfers at any time. DMA interrupts are disabled. DMA interrupts use Interrupt Priority 1. DMA interrupts use Interrupt Priority 2. DMA interrupts use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 199 DMA Master Timing Control Register (DMTCR) (Address = 0x0105) Bit(s) Value Description Fixed DMA channel priority. Higher channel number has higher priority. Rotating DMA channel priority. Priority rotates highest channel number to lowest channel number after every byte is transferred. Rotating DMA channel priority.
Page 200 External DMA Request 0 supplied to DMA Channel 4. External DMA Request 0 supplied to DMA Channel 5. External DMA Request 0 supplied to DMA Channel 6. External DMA Request 0 supplied to DMA Channel 7. Rabbit 4000 Microprocessor User’s Manual...
Page 201 DMA Master Request 1 Control Register (DMR1CR) (Address = 0x0107) Bit(s) Value Description External DMA Request 1 disabled. External DMA Request 1 enabled from Parallel Port D3. External DMA Request 1 enabled from Parallel Port E3. External DMA Request 1 enabled from Parallel Port E7. This bit is reserved and should be written with zero.
Page 202 The eight LSBs of the limit value for the DMA timed request timer are stored. DMA Timed Request Divider High Register (DTRDHR) (Address = 0x0117) Bit(s) Value Description Write The eight MSBs of the limit value for the DMA timed request timer are stored. Rabbit 4000 Microprocessor User’s Manual...
Page 203 DMA y Termination Byte Register (D0TBR) (Address = 0x0108) (D1TBR) (Address = 0x0118) (D2TBR) (Address = 0x0128) (D3TBR) (Address = 0x0138) (D4TBR) (Address = 0x0148) (D5TBR) (Address = 0x0158) (D6TBR) (Address = 0x0168) (D7TBR) (Address = 0x0178) Bit(s) Value Description Byte value that, if matched, will terminate a buffer.
Page 204 (Address = 0x012E) (D3IA2R) (Address = 0x013E) (D4IA2R) (Address = 0x014E) (D5IA2R) (Address = 0x015E) (D6IA2R) (Address = 0x016E) (D7IA2R) (Address = 0x017E) Bit(s) Value Description Bits 23:16 of the initial address are stored in this register. Rabbit 4000 Microprocessor User’s Manual...
Page 205 DMA y State Machine Register (D0SMR) (Address = 0x0180) (D1SMR) (Address = 0x0190) (D2SMR) (Address = 0x01A0) (D3SMR) (Address = 0x01B0) (D4SMR) (Address = 0x01C0) (D5SMR) (Address = 0x01D0) (D6SMR) (Address = 0x01E0) (D7SMR) (Address = 0x01F0) Bit(s) Value Description 11111110 Idle (disabled).
Page 206 Source address is memory (three-byte) address, auto-increment. Destination address is fixed internal I/O (two-byte) address. Destination address is fixed external I/O (two-byte) address. Destination address is memory (three-byte) address, auto-decrement. Destination address is memory (three-byte) address, auto-increment. Rabbit 4000 Microprocessor User’s Manual...
Page 207 DMA y Length[7:0] Register (D0L0R) (Address = 0x0182) (D1L0R) (Address = 0x0192) (D2L0R) (Address = 0x01A2) (D3L0R) (Address = 0x01B2) (D4L0R) (Address = 0x01C2) (D5L0R) (Address = 0x01D2) (D6L0R) (Address = 0x01E2) (D7L0R) (Address = 0x01F2) Bit(s) Value Description Bits 7:0 of the buffer length value are stored in this register. The DMA does a transfer followed by a decrement of this register, so an initial value of 0x0000 will result in a 65536-byte transfer.
Page 208 (Address = 0x01A6) (D3SA2R) (Address = 0x01B6) (D4SA2R) (Address = 0x01C6) (D5SA2R) (Address = 0x01D6) (D6SA2R) (Address = 0x01E6) (D7SA2R) (Address = 0x01F6) Bit(s) Value Description Bits 23:16 of the source address are stored in this register. Rabbit 4000 Microprocessor User’s Manual...
Page 209 DMA y Destination Addr[7:0] Register (D0DA0R) (Address = 0x0188) (D1DA0R) (Address = 0x0198) (D2DA0R) (Address = 0x01A8) (D3DA0R) (Address = 0x01B8) (D4DA0R) (Address = 0x01C8) (D5DA0R) (Address = 0x01D8) (D6DA0R) (Address = 0x01E8) (D7DA0R) (Address = 0x01F8) Bit(s) Value Description Bits 7:0 of the destination address are stored in this register.
Page 210 (Address = 0x01AE) (D3LA2R) (Address = 0x01BE) (D4LA2R) (Address = 0x01CE) (D5LA2R) (Address = 0x01DE) (D6LA2R) (Address = 0x01EE) (D7LA2R) (Address = 0x01FE) Bit(s) Value Description Bits 23:16 of the link address are stored in this register. Rabbit 4000 Microprocessor User’s Manual...
Page 211: Chapter 20 10Base-T Ethernet
The Rabbit 4000 does not implement the 10Base-T physical layer on-chip, but provides differential transmit data to simplify the external circuitry required to drive the 10Base-T cabling with the required waveform.
Page 212 Since the network port requires a 20.000 MHz clock, the clock should normally be supplied from the port pin. Using the system clock or a derivative to drive the network port precludes the use of the clock modulator. Rabbit 4000 Microprocessor User’s Manual...
Page 213: Block Diagram
The network port receiver uses two pins with various options for the behavior. The network port transmitter uses four pins to provide differential signals with wave-shaping capability. See Section 20.4 for more details. 20.1.1 Block Diagram Chapter 20 10Base-T Ethernet...
Page 214: Registers
Network Port A CRC Error Register NACER 0x0223 00000000 Network Port A Checksum 0 Register NAC0R 0x0224 00000000 Network Port A Checksum 1 Register NAC1R 0x0225 00000000 Network Port A Missed Frame Register NAMFR 0x0226 00000000 Rabbit 4000 Microprocessor User’s Manual...
Page 215: Dependencies
If the processor clock is used, the clock doubler and dither should be disabled. NOTE: Unlike the other clock inputs on the Rabbit 4000, the PE6 network clock input does not have a Schmitt trigger inside the device. It is strongly recommended that you place an external Schmitt trigger on the input to PE6 if PE6 is to be used as the network clock input.
Page 216: Operation
(or error). Note that network interrupts will occur when the data appear in the Ethernet peripheral, but DMA interrupts will occur when the DMA transfer is complete. Rabbit 4000 Microprocessor User’s Manual...
Page 217: Handling Interrupts
20.3.4 Handling Interrupts The network port interrupt is automatically cleared by reading NACSR. A sample interrupt handler is shown below. network_isr:: push af ioi ld a, (NACSR) ; read the interrupt status push af ; save status byte for later bit 6,a ;...
Page 218: Multicast Addressing
0x5F 0x43 0x4D 0x51 0xCD 0xD1 0xDF 0xC3 NAMF2R 0x91 0x8D 0x83 0x9F 0x03 0x1F 0x11 0x0D NAMF1R 0x87 0x9B 0x95 0x89 0x15 0x09 0x07 0x1B NAMF0R 0x49 0x55 0x5B 0x47 0xDB 0xC7 0xC9 0xD5 Rabbit 4000 Microprocessor User’s Manual...
Page 219: Ethernet Interface Circuit
20.4 Ethernet Interface Circuit This is the recommended circuit for the Rabbit 4000 10Base-T Ethernet interface. All resistors are 1/16 W, 1%, unless otherwise noted. – RECEIVE optional – optional TRANSMIT CLOCK optional The transmit data output pins consist of two pins for each side of the differential signal.
Page 220: Register Descriptions
DMA. Loads the transmit buffer with the last data byte of a frame to enable the Write subsequent transmission of the CRC. The DMA automatically writes the last byte of the frame to this address. Rabbit 4000 Microprocessor User’s Manual...
Page 221 Network Port A Transmit Status Register (NATSR) (Address = 0x0202) Bit(s) Value Description 0000 Transmitter is disabled or has not yet sent a frame after being enabled. 0xx1 Frame transmission aborted because of a FIFO underrun. 0x1x Frame transmission aborted because of excessive collisions (16). 01xx Transmitter is deferring frame transmission.
Page 222 Either a link status change or jabber condition has been detected. only) The Network Port interrupt is disabled. The Network Port uses Interrupt Priority 1. The Network Port uses Interrupt Priority 2. The Network Port uses Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 223 Network Port A Status Register (NASR) (Address = 0x0205) Bit(s) Value Description This bit is unused. Link operating half-duplex. Link operating full-duplex. This bit is unused. Auto-negotiation process not completed. Auto-negotiation process completed. These bits are unused. Link is down. Link is up.
Page 224 Enable full-duplex operation. If auto-negotiation is disabled, this forces full- duplex operation. If auto-negotiation is enabled, this allows advertising full- duplex capability. This bit is unused and should be written with zero. Rabbit 4000 Microprocessor User’s Manual...
Page 225 Network Port A Pin Control Register (NAPCR) (Address = 0x0208) (network port clock enabled in NACR) Bit(s) Value Description RXD+ and RXD- normal operation (differential inputs). RXD+ singled-ended true input. RXD- is the valid-signal qualifier (active high). RXD+ single-ended true input. RXD- not used by receiver. RXD+ single-ended negative input.
Page 226 Receive frames with broadcast address accepted Receive frames with multicast addresses ignored. Receive frames with multicast addresses accepted if passing hashing filter. Receive frames with mismatched physical addresses are ignored. Receive frames with any physical address accepted. Promiscuous mode. Rabbit 4000 Microprocessor User’s Manual...
Page 227 Network Port A Physical Address x Register (NAPA0R) (Address = 0x0210) (NAPA1R) (Address = 0x0211) (NAPA2R) (Address = 0x0212) (NAPA3R) (Address = 0x0213) (NAPA4R) (Address = 0x0214) (NAPA5R) (Address = 0x0215) Bit(s) Value Description Write Byte of physical address for receive address filtering. Network Port A Multicast Filter x Register (NAMF0R) (Address = 0x0218)
Page 228 The MSB of the checksum for the completed frame is returned in this register. Network Port A Missed Frame Register (NAMFR) (Address = 0x0226) Bit(s) Value Description The current value of the missed-frame counter is returned. This counter is cleared read by a read of this register. Rabbit 4000 Microprocessor User’s Manual...
Page 229: Chapter 21. Input Capture
21. I NPUT APTURE 21.1 Overview The input capture peripheral consists of two channels, each of which contains a 16-bit counter and edge-detection circuitry. The input capture channels are usually used to deter- mine the time between events. An event is signaled by a rising or falling edge (or option- ally by either edge) on one of 12 input pins that can be selected as the input for either of the two channels.
Page 230: Input-Count Mode
MSB and LSB registers. This allows an interrupt to be generated and the counter halted when a particular count is reached. The stop condition will never occur if no value is written into the registers. 21.1.3 Block Diagram Rabbit 4000 Microprocessor User’s Manual...
Page 231: Registers
21.1.4 Registers Register Name Mnemonic I/O Address Reset Input Capture Ctrl/Status Register ICCSR 0x0056 00000000 Input Capture Control Register ICCR 0x0057 00000000 Input Capture Trigger 1 Register ICT1R 0x0058 00000000 Input Capture Source 1 Register ICS1R 0x0059 xxxxxxxx Input Capture LSB 1 Register ICL1R 0x005A xxxxxxxx...
Page 232: Dependencies
Because of this, there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR. Rabbit 4000 Microprocessor User’s Manual...
Page 233: Operation
21.3 Operation 21.3.1 Input-Capture Channel The following steps explain how to set up an input-capture channel. 1. Configure Timer A8 via TAT8R to provide the desired input-capture clock. 2. Configure ICTxR to provide the desired start/stop operation and conditions. 3. Configure ICSxR to select the input pins for the start and stop conditions. 4.
Page 234: Capture Mode
6. If a match value is enabled and generates an interrupt, you can re-enable the count mode by clearing the counter via ICCSR and re-enable the mode in ICTxR back to run- ning continuously until the stop condition occurs. Rabbit 4000 Microprocessor User’s Manual...
Page 235: Register Descriptions
21.4 Register Descriptions Input Capture Control/Status Register (ICCSR) (Address = 0x0056) Bit(s) Value Description The Input Capture 2 Start condition has not occurred. (Read) The Input Capture 2 Start condition has occurred. The Input Capture 2 Stop condition has not occurred. (Read) The Input Capture 2 Stop condition has occurred.
Page 236 These bits are reserved and should be written with zero. Input Capture interrupts are disabled. Input Capture interrupt use Interrupt Priority 1. Input Capture interrupt use Interrupt Priority 2. Input Capture interrupt use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 237 Input Capture Trigger x Register (ICT1R) (Address = 0x0058) (ICT2R) (Address = 0x005C) Bit(s) Value Description Disable the counter. Applies even in Counter operation. The counter runs from the Start condition until the Stop condition. The counter runs continuously. The counter runs continuously, until the Stop condition. Disable the count latching function.
Page 238 Reading the MSB of the count opens these latches on the MSB of the count. In Counter operation, if no latching condition is specified the value written to this register is returned. Write The eight LSBs of the match value for counter mode are stored. Rabbit 4000 Microprocessor User’s Manual...
Page 239 Input Capture MSB x Register (ICM1R) (Address = 0x005B) (ICM2R) (Address = 0x005F) Bit(s) Value Description The most significant eight bits of the latched Input capture count are returned. In Read Counter operation, if no latching condition is specified the value written to this register is returned.
Page 240 Rabbit 4000 Microprocessor User’s Manual...
Page 241: Chapter 22. Quadrature Decoder
ECODER 22.1 Overview The Rabbit 4000 has a two-channel Quadrature Decoder that accepts inputs via specific pins on Parallel Ports D and E. Each channel has two inputs, the in-phase (I) input and the 90 degree or quadrature-phase (Q) input. An 8 or 10-bit up/down counter counts encoder steps in the forward and backward directions, and provides interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00.
Page 242 (0x3FF in 10-bit mode). The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt and status bits are cleared by reading the QDCSR. Rabbit 4000 Microprocessor User’s Manual...
Page 243: Block Diagram
22.1.1 Block Diagram 22.1.2 Registers Register Name Mnemonic I/O Address Reset Quad Decode Ctrl/Status Register QDCSR 0x0090 xxxxxxxx Quad Decode Control Register QDCR 0x0091 00000000 Quad Decode Count 1 Register QDC1R 0x0094 xxxxxxxx Quad Decode Count 1 High Register QDC1HR 0x0095 xxxxxxxx Quad Decode Count 2 Register...
Page 244: Dependencies
The Quadrature Decoder interrupt vector is in the IIR at offset 0x190. It can be set as Priority 1, 2, or 3. The status bits in the QDCSR are set coincident with the interrupt request and are reset when QDCSR is read. Rabbit 4000 Microprocessor User’s Manual...
Page 245: Operation
22.3 Operation The following steps explain how to set up a Quadrature Decoder channel. 1. Configure Timer A10 via TAT10R to provide the desired Quadrature Decoder clock speed. 2. Configure QDCR to select the input pins for the two channels. 3.
Page 246: Register Descriptions
Quadrature Decoder 1 decremented from zero to the maximum count. This bit is only) cleared by a read of this register. This bit always reads as zero. No effect on the Quadrature Decoder 1. (Write- Reset Quadrature Decoder 1 to all zeros, without causing an interrupt. only) Rabbit 4000 Microprocessor User’s Manual...
Page 247 Quad Decode Control Register (QDCR) (Address = 0x0091) Bit(s) Value Description Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. Quadrature Decoder 2 inputs from Parallel Port D bits 3 and 2. Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2.
Page 248 Rabbit 4000 Microprocessor User’s Manual...
Page 249: Chapter 23. Pulse Width Modulator
23. P ULSE IDTH ODULATOR 23.1 Overview The Pulse Width Modulator (PWM) consists of a 10-bit free running counter and four width registers. A PWM output consists of a train of periodic pulses within a 1024-count frame with a duty cycle that varies from 1/1024 to 1024/1024. Each PWM output is high for n + 1 counts out of the 1024-clock count cycle, where n is the value held in the width register.
Page 250 Operation in the spread mode reduces the filtering requirements on the PWM output in most cases. The DMA channels on the Rabbit 4000 are designed to work with fixed I/O addresses. To allow DMA control of the PWM, a separate PWM Block Access Register (PWBAR) and PWM Block Pointer Register (PWBPR) are available.
Page 251: Block Diagram
pointer register is initialized to 0x88 (the first PWM register) and the DMA then transfers blocks of eight bytes to completely reprogram the PWM. 0x88 -> 0x89 -> 0x8A -> 0x8B -> 0x8C -> 0x8D -> 0x8E -> 0x8F -> When the DMA destination address is the PWBAR, the DMA request from the PWM is automatically connected to the DMA.
Page 252: Dependencies
The interrupt request is cleared by a write to any PWM register. The PWM interrupt vector is in the IIR at offset 0x170. It can be set as Priority 1, 2, or 3 by writing to PWL0R. Rabbit 4000 Microprocessor User’s Manual...
Page 253: Operation
23.3 Operation The following steps explain how to set up a PWM channel. 1. Configure Timer A9 via TAT9R to provide the desired PWM clock frequency. 2. Configure PWLxR to select whether to spread the PWM output throughout the cycle. 3.
Page 254: Register Descriptions
Suppress PWM interrupts seven out of eight iterations of PWM counter. Suppress PWM interrupts three out of four iterations of PWM counter. Suppress PWM interrupts one out of two iterations of PWM counter. PWM output High for single block. Spread PWM output throughout the cycle. Rabbit 4000 Microprocessor User’s Manual...
Page 255 PWM LSB x Register (PWL2R) (Address = 0x008C) (PWL3R) (Address = 0x008E Bit(s) Value Description Least significant two bits for the Pulse Width Modulator count. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter. Suppress PWM output one out of two iterations of PWM counter.
Page 256 Rabbit 4000 Microprocessor User’s Manual...
Page 257: Chapter 24. External I/O Control
ONTROL 24.1 Overview The Rabbit 4000’s external I/O space consists of 64KB that is accessed by prefixing a read or write instruction with the IOE instruction. These accesses can go onto the memory bus or onto the external I/O bus (described below). There are three dedicated signal pins (/IORD, /IOWR, /BUFEN) that toggle for all external I/O accesses, and eight I/O strobes that can be associated with this external I/O space and directed out of Parallel Ports C, D, or E.
Page 258: I/O Strobes
24.1.2 I/O Strobes There are eight I/O strobes available in the Rabbit 4000. Each has a separate 8KB address range that can be enabled as a chip select, read strobe, write strobe, or a read/write strobe. The number of wait states can be set to 1, 3, 7, or 15, and the signal can be active high or low.
Page 259: I/O Handshake
I/O banks. The external device holds this signal (active high or low) when it is busy and cannot accept a transaction. The Rabbit 4000 will then hold midway through the transaction until either the handshake signal goes inactive or a timeout occurs.
Page 260: Block Diagram
IB3CR 0x0083 00000000 I/O Bank 4 Control Register IB4CR 0x0084 00000000 I/O Bank 5 Control Register IB5CR 0x0085 00000000 I/O Bank 6 Control Register IB6CR 0x0086 00000000 I/O Bank 7 Control Register IB7CR 0x0087 00000000 Rabbit 4000 Microprocessor User’s Manual...
Page 261: Dependencies
24.2 Dependencies 24.2.1 I/O Pins The auxiliary I/O bus uses PA0–PA7 for data, and either PB2–PB7 or PB0–PB7 for address lines, depending on the setting in SPCR. Address bits 6 and 7 can also be enabled on pins PD1, PD3, PD5, or PD7, which allows PB0 and PB1 to be used as clocked serial I/O instead of as external I/O..
Page 262: Operation
3. Select the handshake timeout value by writing to IHTR. Once enabled, the handshake will be checked for every external I/O transaction in a bank that was enabled in IHSR. After these transactions, the program should check for a time- out by reading IHTR. Rabbit 4000 Microprocessor User’s Manual...
Page 263: Register Descriptions
24.4 Register Descriptions I/O Handshake Control Register (IHCR) (Address = 0x0028) Bit(s) Value Description These bits are reserved and should be written with zeros. I/O handshake is active low (I/O transaction held until signal goes high). I/O handshake is active high (I/O transaction held until signal goes low). This bit is reserved and should be written with zero.
Page 264 Time constant for the I/O handshake timeout counter. This time constant (times 32) selects the number of clocks that the I/O handshake input may delay completion of an I/O transaction before the I/O transaction will complete automatically. Rabbit 4000 Microprocessor User’s Manual...
Page 265 I/O Bank x Control Register (IB0CR) (Address = 0x0080) (IB1CR) (Address = 0x0081) (IB2CR) (Address = 0x0082) (IB3CR) (Address = 0x0083) (IB4CR) (Address = 0x0084) (IB5CR) (Address = 0x0085) (IB6CR) (Address = 0x0086) (IB7CR) (Address = 0x0087) Bit(s) Value Description Fifteen wait states for accesses in this bank.
Page 266 Enable the auxiliary I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus. Slave port interrupts are disabled. Slave port interrupts use Interrupt Priority 1. Slave port interrupts use Interrupt Priority 2. Slave port interrupts use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 267 Parallel Port C Alternate Low Register (PCALR) (Address = 0x0052) Bit(s) Value Description Parallel Port C bit 3 alternate output 0 (TXC). Parallel Port C bit 3 alternate output 1 (I3). Parallel Port C bit 3 alternate output 2 (TIMER C3). Parallel Port C bit 3 alternate output 3 (SCLKD).
Page 268 Parallel Port C bit 4 alternate output 3 (TCLKE). Parallel Port C Function Register (PCFR) (Address = 0x0055) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 10- Rabbit 4000 Microprocessor User’s Manual...
Page 269 Parallel Port D Alternate Low Register (PDALR) (Address = 0x0062) Bit(s) Value Description Parallel Port D bit 3 alternate output 0 (IA7). Parallel Port D bit 3 alternate output 1 (I3). Parallel Port D bit 3 alternate output 2 (TIMER C3). Parallel Port D bit 3 alternate output 3 (SCLKD).
Page 270 Parallel Port D bit 4 alternate output 3 (TCLKE). Parallel Port D Function Register (PDFR) (Address = 0x0065) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 11-1. Rabbit 4000 Microprocessor User’s Manual...
Page 271 Parallel Port E Alternate Low Register (PEALR) (Address = 0x0072) Bit(s) Value Description Parallel Port E bit 3 alternate output 0 (I3). Parallel Port E bit 3 alternate output 1 (A23). Parallel Port E bit 3 alternate output 2 (TIMER C3). Parallel Port E bit 3 alternate output 3 (SCLKD).
Page 272 Parallel Port E bit 4 alternate output 3 (TCLKE). Parallel Port E Function Register (PEFR) (Address = 0x0075) Bit(s) Value Description The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output. See Table 12- Rabbit 4000 Microprocessor User’s Manual...
Page 273: Chapter 25. Breakpoints
REAKPOINTS 25.1 Overview The Rabbit 4000 contains seven hardware breakpoints to support debugging. Each hard- ware breakpoint consists of a 24-bit address match register and a 24-bit mask register. A breakpoint can be generated on an address match for address execution, data read, data write, or any combination thereof.
Page 274: Block Diagram
25.1.1 Block Diagram Rabbit 4000 Microprocessor User’s Manual...
Page 275: Registers
25.1.2 Registers Register Name Mnemonic I/O Address Reset Breakpoint Debug/Control Register BDCR 0x001C 00000000 Breakpoint 0 Control Register B0CR 0x030B 00000000 Breakpoint 1 Control Register B1CR 0x031B 00000000 Breakpoint 2 Control Register B2CR 0x032B 00000000 Breakpoint 3 Control Register B3CR 0x033B 00000000 Breakpoint 4 Control Register...
Page 276: Dependencies
• If single-step functionality is desired, the breakpoint interrupt should be re-enabled by writing the appropriate bit to BDCR. If this is done, the interrupt handler needs to be exited in a particular manner (see below). Rabbit 4000 Microprocessor User’s Manual...
Page 277: Example Isr
25.3.2 Example ISR A sample interrupt handler is shown below. breakpoint_isr:: push af ioi ld a, (BDCR) ; determine which interrupts are pending and ; clear the interrupt request ; handle all breakpoints here ; reenable any breakpoints by writing to BDCR pop af ipres ;...
Page 278: Register Descriptions
Breakpoint x on User Mode write address match. Breakpoint x on System Mode write address match. Breakpoint x on System or User Mode write address match. These bits are reserved and should be written with zeros. Rabbit 4000 Microprocessor User’s Manual...
Page 279 Breakpoint x Address 0 Register (B0A0R) (Address = 0x030C) (B1A0R) (Address = 0x031C) (B2A0R) (Address = 0x032C) (B3A0R) (Address = 0x033C) (B4A0R) (Address = 0x034C) (B5A0R) (Address = 0x036C) (B6A0R) (Address = 0x037C) Bit(s) Value Description Breakpoint x Address [7:0]. Breakpoint x Address 1 Register (B0A1R) (Address = 0x030D)
Page 280 (Address = 0x033A) (B4M2R) (Address = 0x034A) (B5M2R) (Address = 0x036A) (B6M2R) (Address = 0x037A) Bit(s) Value Description Breakpoint x Mask [23:16]. (A one in a bit position inhibits the address compare for that bit position. Rabbit 4000 Microprocessor User’s Manual...
Page 281: Chapter 26 Low-Power Operation
The Rabbit 4000 contains several power-saving features. Since the power consumed by the processor is proportional to the clock speed, the Rabbit 4000 provides 12 clock modes that can go as low as 2 kHz. To further reduce power consumption in those ultra-sleepy modes, various shortened chip select strobes are available to reduce current draw by the attached memory devices.
Page 282: Registers
Figure 26-2. Typical Current Draw for the Ultra Sleepy Modes 26.1.1 Registers Register Name Mnemonic I/O Address Reset Global Control/Status Register GCSR 0x0000 11000000 Global Power Save Control Register GPSCR 0x000D 00000000 Global Clock Double Register GCDR 0x000F 00000000 Rabbit 4000 Microprocessor User’s Manual...
Page 283: Operation
26.2.2 Clock Rates The processor and peripheral clocks in the Rabbit 4000 can be run in six different modes using the main oscillator: full speed; divided by 2, 4, 6, or 8; and the processor clock divided by 8 with the peripheral clock at full speed.
Page 284: Short Chip Selects
However, when the processor clock is running off of the 32 kHz clock, it is recommended that the Rabbit 4000 be performing a tight polling loop, waiting for a wakeup event.
Page 285 Chapter 26 Low-Power Operation...
Page 286 32 kHz clock (30.5 microseconds); oth- erwise the timing is identical to the short chip select options based off the main oscillator. Read strobe figures are shown below. Rabbit 4000 Microprocessor User’s Manual...
Page 287 Chapter 26 Low-Power Operation...
Page 288 Rabbit 4000 Microprocessor User’s Manual...
Page 289: Self-Timed Chip Selects
26.2.4 Self-Timed Chip Selects Self-timed chip selects can be enabled via GPSCR to reduce power consumption even more when running off the 32kHz oscillator. When self-timed chip selects are enabled, the chip select is only active for a short (selectable) period of time. A sample read and write timing diagram is shown below.
Page 290: Register Descriptions
Processor clock from the fast clock, divided by 6. Peripheral clock from the fast clock, divided by 6. Periodic interrupts are disabled. Periodic interrupts use Interrupt Priority 1. Periodic interrupts use Interrupt Priority 2. Periodic interrupts use Interrupt Priority 3. Rabbit 4000 Microprocessor User’s Manual...
Page 291 Global Power Save Control Register (GPSCR) (Address = 0x000D) Bit(s) Value Description Self-timed chip selects are disabled. 230 ns self-timed chip selects for read and write. 170 ns self-timed chip selects for read and write. 110 ns self-timed chip selects for read and write. 290 ns self-timed chip selects for read only.
Page 292 20 ns nominal low time. 10001 3 ns nominal low time. 10010 4 ns nominal low time. 10011 5 ns nominal low time. other Any bit combination not listed is reserved and must not be used. Rabbit 4000 Microprocessor User’s Manual...
Page 293: Chapter 27. System/User Mode
YSTEM 27.1 Overview The Rabbit 4000 provides support for two tiers of control in the processor: System Mode, which provides full access to all processor resources; and User Mode, a more restricted mode. Table 27-1 describes the essential differences between the System Mode and the User Mode.
Page 294: Registers
0x3E0 00000000 Serial Port D User Enable Register SDUER 0x3F0 00000000 Serial Port E User Enable Register SEUER 0x03C8 00000000 Serial Port F User Enable Register SFUER 0x3D8 00000000 Enable Dual-Mode Register EDMR 0x0420 00000000 Rabbit 4000 Microprocessor User’s Manual...
Page 295: Dependencies
27.2 Dependencies 27.2.1 I/O Pins There are no pin dependencies for the System/User Mode. 27.2.2 Clocks There are no clock dependencies for the System/User Mode. 27.2.3 Other Registers Any writes to the internal I/O registers listed in Table 27-2 are ignored when the System/ User Mode is enabled and the processor is in the User Mode.
Page 296: Interrupts
When the System/User Mode is enabled, it is critical to handle the SU stack in interrupts as well as the IP stack; always perform a before the at the end of the SURES IPRES interrupt. Rabbit 4000 Microprocessor User’s Manual...
Page 297: Operation
The System/User Mode is designed to work with the memory and stack protection features of the Rabbit 4000 processor to provide a seamless framework for protection of critical code. However, there are many levels at which the System/User Mode can be used —...
Page 298: Mixed System/User Mode Operation
If any critical interrupts occur (stack limit violation, system mode violation, write protec- tion violation), System Mode handlers can perform any of a number of operations: restart the application code, signal another device, halt operation, and so on. Rabbit 4000 Microprocessor User’s Manual...
Page 299: Enabling The System/User Mode
Figure 27-3 shows an overview of this level of operation. System Mode User Mode Return from interrupts Interrupt Application handlers code Flash file User-defined system interrupts SYSCALL handler Interrupts, SYSCALL, RST Figure 27-3. System/User Mode Setup for Operating System 27.3.4 Enabling the System/User Mode The following steps describe how to enable the System/User Mode.
Page 300: System/User Mode Instructions
User Mode), or an interrupt occurs, or is executed (to enter System SYSCALL Mode), the current mode is pushed onto the SU register. When a is executed, the SURES previous mode is popped off the SU register. Rabbit 4000 Microprocessor User’s Manual...
Page 301: System Mode Violation Interrupt
The effects of each instruction are: • The instruction puts the processor into the User Mode by pushing the correct SETUSR value into the SU register. push and pop the single-byte SU register on/off the SP stack. • PUSH SU POP SU pops the current processor mode off the SU register, returning it to the previous •...
Page 302: Handling Interrupts In The System/User Mode
When enabled for User Mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Priority 2 or 1. INTERRUPT UNDER SYSTEM CONTROL INTERRUPT UNDER USER CONTROL Figure 27-4. Interrupt Handing in the System/User Mode Rabbit 4000 Microprocessor User’s Manual...
Page 303 Some sample code for both System Mode interrupts and User Mode interrupts is shown below. The use of provides checks against stack mismatches and SETUSRP SETSYSP incorrect System/User Modes coming out of the User Mode handler. systemmode_isr: ; jumped to from interrupt vector table ...
Page 304: Register Descriptions
Bit(s) Value Description Disable User Mode access to Parallel Port C (I/O addresses 0x0050–0x0055). Enable User Mode access to Parallel Port C (I/O addresses 0x0050–0x0055). These bits are reserved and should be written with zeros. Rabbit 4000 Microprocessor User’s Manual...
Page 305 Parallel Port D User Enable Register (PDUER) (Address = 0x0360) Bit(s) Value Description Disable User Mode access to Parallel Port D (I/O addresses 0x0060–0x006F). Enable User Mode access to Parallel Port D (I/O addresses 0x0060–0x006F). These bits are reserved and should be written with zeros. Parallel Port E User Enable Register (PEUER) (Address = 0x0370)
Page 306 Description Disable User Mode access to the Quadrature Decoder (I/O addresses 0x0090– 0x0097). Enable User Mode access to the Quadrature Decoder (I/O addresses 0x0090– 0x0097). These bits are reserved and should be written with zeros. Rabbit 4000 Microprocessor User’s Manual...
Page 307 External Interrupt User Enable Register (IUER) (Address = 0x0398) Bit(s) Value Description These bits are reserved and should be written with zeros. Disable User Mode access to External Interrupt 1 (I/O address 0x0099). Enable User Mode access to External Interrupt 1 (I/O addresses 0x0099). Disable User Mode access to External Interrupt 0 (I/O address 0x0098).
Page 308 Bit(s) Value Description Disable User Mode access to Serial Port E (I/O addresses 0x00C8–0x00CF). Enable User Mode access to Serial Port E (I/O addresses 0x00C8–0x00CF). These bits are reserved and should be written with zeros. Rabbit 4000 Microprocessor User’s Manual...
Page 309 This bit combination is reserved and must not be used. This bit combination is reserved and must not be used. Enhanced (Rabbit 4000) instruction set. These bits are reserved and should be written with zeros. Normal (System Mode only) operation.
Page 310 Rabbit 4000 Microprocessor User’s Manual...
Page 311: Chapter 28 Specifications
28. S PECIFICATIONS 28.1 DC Characteristics Table 28-1. Preliminary DC Electrical Characteristics Parameter Symbol Operating Temperature -40°C 85°C Storage Temperature -55°C 125°C Core Supply Voltage 1.65 V 1.8 V 1.90 V CORE Core Current @ 29.4912 MHz, 25°C 6.0 mA Core current @ 7.3728 MHz, 25°C 3.7 mA CORE...
Page 312 1.7 µA 2.7 µA VBAT VBATIO Supply Voltage (device powered) VBATIO 1.65 V 3.3 V 3.6 V (device powered down) 1.65 V 1.8 V 3.6 V VBATIO Current (device powered down) 0.1 µA 0.2 µA VBATIO Rabbit 4000 Microprocessor User’s Manual...
Page 313: Ac Characteristics
28.2 AC Characteristics Table 28-3. Preliminary AC Electrical Characteristics ± ± ° ° (VDD = 1.8 V 10%, VDD = 3.3 V 10%, T = -40 C to 85 CORE Parameter Symbol Main Clock Frequency on CLKI 60 MHz main Real-Time Clock Frequency on CLK32K 32.768 kHz Ethernet Clock Frequency on PE6...
Page 314: Memory Access Times
8 ns 90 pF 11 ns 30 pF 6 ns Clock to Memory Read Strobe Delay 60 pF 8 ns 90 pF 11 ns Data Setup Time 1 ns setup Data Hold Time 0 ns hold Rabbit 4000 Microprocessor User’s Manual...
Page 315: Memory Writes
28.3.2 Memory Writes Table 28-5. Preliminary Memory Write-Time Delays ± ± ° ° (VDD = 1.8 V 10%, VDD = 3.3 V 10%, T = -40 C to 85 CORE Parameter Symbol Loading 30 pF 6 ns Clock to Address Delay 60 pF 8 ns 90 pF...
Page 316 Memory Read (no wait states) valid valid Memory Write (no extra wait states) valid valid Figure 28-1. Memory Read and Write Cycles Rabbit 4000 Microprocessor User’s Manual...
Page 317 Memory Read (no wait states) valid valid Memory Write (no extra wait states) valid valid Figure 28-2. Memory Read and Write Cycles—Early Output Enable and Write Enable Timing Chapter 28 Specifications...
Page 318: External I/O Reads
90 pF 11 ns 30 pF 6 ns Clock to I/O Buffer Enable Delay 60 pF 8 ns BUFEN 90 pF 11 ns Data Setup Time 1 ns setup Data Hold Time 1 ns hold Rabbit 4000 Microprocessor User’s Manual...
Page 319: External I/O Writes
28.3.4 External I/O Writes Table 28-7. Preliminary External I/O Write Time Delays ± ± ° ° (VDD = 1.8 V 10%, VDD = 3.3 V 10%, T = -40 C to 85 CORE Parameter Symbol Loading 30 pF 6 ns Clock to Address Delay 60 pF 8 ns...
Page 320 External I/O Read (no extra wait states) valid valid External I/O Write (no extra wait states) valid valid Figure 28-3. I/O Read and Write Cycles—No Extra Wait States NOTE: /IOCSx can be programmed to be active low (default) or active high. Rabbit 4000 Microprocessor User’s Manual...
Page 321: Memory Access Times
28.3.5 Memory Access Times In computing memory requirements, the important considerations are the address access time, output-enable access time, and minimum write-pulse required. Increasing the clock doubler delay increases the output-enable time, but decreases the memory write-pulse width. The early write-pulse option can be used to ensure a long-enough write pulse, but then it must be ensured that the write pulse does not begin before the address lines have stabilized.
Page 322 All important signals on the Rabbit 4000 are output-synchronized with the internal clock. The internal clock is closely synchronized with the external clock, which is available on the CLK pin. The delay in signal output depends on the capacitive load on the output lines.
Page 323 Similarly, the gross output-enable access time is T + minimum clock low time (it is assumed that the early output enable option is enabled). This is reduced by the spectrum spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetry of the original oscillator clock.
Page 324: Clock Speeds
0 wait states without wait states The Rabbit 4000 is rated for a minimum clock period of 16 ns for both commercial and industrial specifications (preliminary). The commercial rating calls for a ±5% voltage variation from 3.3 V, and a temperature range from -40 to + 70°C. The industrial ratings stretch the voltage variation to ±10% over a temperature range from -40 to + 85°C.
Page 325 Table 28-11. Preliminary Maximum Clock Speeds ±10%, Temp. -40°C to +85°C) Industrial Ratings Duty Cycle Minimum Maximum Conditions Requirements Period Frequency (ns) (ns) (MHz) No Doubler or 58.8 Spreader Spreader Only 50.0 Normal Spreader Only 47.6 Strong Doubler Only 1 > (clock low - 52.6 (8 ns delay) clock high) >...
Page 326 50% duty cycle, to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty-cycle adjustment by changing the resistance of the power and ground connections as shown below. Figure 28-4. External Oscillator Buffer Rabbit 4000 Microprocessor User’s Manual...
Page 327: Power And Current Consumption
28.5 Power and Current Consumption Various mechanisms contribute to the current consumption of the Rabbit 4000 processor while it is operating, including current that is proportional to the voltage alone (leakage current) and dependent on both voltage and frequency (switching and crossover current).
Page 328: Sleepy Mode Current Consumption
28.5.1 Sleepy Mode Current Consumption The Rabbit 4000 supports designs with very low power consumption by using features such as the ultra-sleepy modes and self-timed chip selects. At the low frequencies possible in the ultra-sleepy modes (as low as 2 kHz), the external memory devices become signifi- cant factors in the current consumption unless one of the short or self-timed chip selects are used.
Page 329: Battery-Backed Clock Current Consumption
28.5.2 Battery-Backed Clock Current Consumption For the battery-backed features of the Rabbit 4000 to perform while the processor is pow- ered down, both the VBAT and BATIO pins need to be supplied properly. The VBAT pin powers the internal real-time clock and the battery-backed SRAM, while VBATIO powers the /RESET, /CS1, CLK32K, and RESOUT pins.
Page 330 Rabbit 4000 Microprocessor User’s Manual...
Page 331: Chapter 29. Package Specifications And Pinout
29. P ACKAGE PECIFICATIONS INOUT 29.1 LQFP Package 29.1.1 Pinout Figure 29-1. Package Outline and Pin Assignments Chapter 29 Package Specifications and Pinout...
Page 332: Mechanical Dimensions And Land Pattern
29.1.2 Mechanical Dimensions and Land Pattern Figure 29-2. Mechanical Dimensions Rabbit LQFP Package Rabbit 4000 Microprocessor User’s Manual...
Page 333 Figure 29-3 shows the PC board land pattern for the Rabbit 4000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pat- tern Standard, IPC, Northbrook, IL, 1999.
Page 334: Ball Grid Array Package
29.2 Ball Grid Array Package 29.2.1 Pinout Figure 29-4. Ball Grid Array Pinout Looking Through the Top of Package Rabbit 4000 Microprocessor User’s Manual...
Page 335: Mechanical Dimensions And Land Pattern
29.2.2 Mechanical Dimensions and Land Pattern TOP VIEW BOTTOM VIEW Figure 29-5. BGA Package Outline Chapter 29 Package Specifications and Pinout...
Page 336 NSMD Defined Land Diameter 0.406 (0.016) Land to Mask Clearance (min.) 0.050 (0.002) Conductor Width (max.) 0.127 (0.005) Conductor Spacing (typ.) 0.127 (0.005) Via Capture Pad (max.) 0.406 (0.016) Via Drill Size (max.) 0.254 (0.010) Rabbit 4000 Microprocessor User’s Manual...
Page 337: Rabbit Pin Descriptions
29.3 Rabbit Pin Descriptions Table 29-3 lists all the pins on the Rabbit 4000 along with the data direction of the pin, its function, and the pin number on the die. Table 29-3. Rabbit 4000 Pin Descriptions Pin Group Pin Name...
Page 338 Table 29-3. Rabbit 4000 Pin Descriptions Pin Group Pin Name Direction Function LQFP Pin TFBGA Ball TXD+ TXD- Output Network Transmit 124–127 TXDD+ Network TXDD- RXD+ Input Network Receive 121–122 RXD- Rabbit 4000 Microprocessor User’s Manual...
Page 339: Appendix A Parallel Port Pins With Alternate Functions
A. P PPENDIX ARALLEL INS WITH LTERNATE UNCTIONS A.1 Alternate Parallel Port Pin Outputs Table A-1. Alternate Parallel Port A and B Pin Outputs Alternate Output Options Serial Clock I/O Mode Slave Mode PA[7:0] — Data — — /SLVATN — —...
Page 340 PD0 becomes SCLKD and is not available for other use. However, all the Parallel Port D pins are used for the 16-bit data bus, and so a pin on another parallel port then has to be selected for the clock output Rabbit 4000 Microprocessor User’s Manual...
Page 341: Alternate Parallel Port Pin Inputs
A.2 Alternate Parallel Port Pin Inputs Table A-3. Alternate Parallel Port Pin Inputs Serial Serial Quad- Slave Input External Ports Ports Hand- Network rature Capture Interrupt Port shake Decoder A–D E–F PA[7:0] — — — — — Data — — —...
Page 342 A–D E–F — — INT0 — QRD1B — — TCLKE DREQ1 — — QRD2A — — DREQ0 — — QRD2B — SCLKC — INT1 — QRD1A — RCLKF — INT0 — QRD1B — SCLKD TCLKF Rabbit 4000 Microprocessor User’s Manual...
Page 343: Appendix B. Rabbit 4000 Esd Design Guidelines And Bug Workarounds
ESIGN UIDELINES AND ORKAROUNDS The Rabbit 4000 began shipping in 2006, and has undergone one minor respin since that time. Several bugs were found in the design after the chip was produced, and are discussed in this appendix. Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds...
Page 344: Esd Sensitivity
ESD sensitivity on the VBAT pin once the chip is installed in a design as long as the design guidelines recommended below are followed. The design was respun to improve the ESD protection on the VBAT pin. Rabbit 4000 processors with the following markings have this additional protection: •...
Page 345: Bugs
B.2 Bugs The following bugs have been identified in the Rabbit 4000 design, and are present in all devices currently available. 1. Primary/secondary watchdog timer interaction — if the secondary watchdog timer is enabled when a primary watchdog timeout occurs (resetting the processor), the sec- ondary watchdog timer is still enabled when the device comes out of reset, which is not the documented behavior (the secondary watchdog should be disabled on reset).
Page 346 By checking the value of BC and jumping back to the block copy instruction if it is nonzero, the block copy instruction is restarted with all the current register values (source and destination pointers) and will continue where it left off. Rabbit Semicon- ductor’s Dynamic C compiler automatically includes this wrapper code whenever it identifies a block copy instruction.
Page 347 It is highly likely that any SRAM device that you are executing code in will support the advanced 16-bit mode with byte-writes enabled, which will also improve the overall performance as a result of the 16-bit data fetches. Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds...
Page 348 Rabbit 4000 Microprocessor User’s Manual...
Page 349 ....177 PWM ....... 241 DMA/block copy interac- quadrature decoder ..233 tion ...... 186, 336 Rabbit 4000 ......4 clock modes ......12 external requests ..... 173 reset ........25 clocks ........9 interrupts ..174, 177, 179 Serial Ports A –...
Page 350 ISR ....223 mapping ......42 example ISR ....117 load parallel port output regis- register descriptions ..53 Timer C ....124, 125 ters .......220 registers ....44, 45, 46 example ISR ....125 measure pulse widths ..219 memory protection ....52 Rabbit 4000 Microprocessor User’s Manual...
Page 351 ..31 register descriptions ..75 Rabbit 3000 ......6 pin descriptions ....327 registers ......73 Rabbit 4000 ......1 alternate pin functions slave port data bus ..... 73 block diagram ..... 4 Parallel Port A and B Parallel Port B .......
Page 352 ....215 PEUER ......295 DxLA2R ......200 NAPCR (network port PWBAR .......245 DxSA0R ......198 enabled) ....215 PWBPR .......245 DxSA1R ......198 NARCR .......216 PWL0R ......244 DxSA2R ......198 NARR ......213 PWL1R ......244 DxSMR ......195 NARSR ......211 PWLxR ......245 Rabbit 4000 Microprocessor User’s Manual...
Page 353 registers registers registers alphabetic listing (continued) alphabetic listing (continued) clocks (continued) PWMxR ...... 245 TBCMR ....... 119 Global Control/Status PWUER ....... 296 TBCR ......118 Register ...... 20 QDCR ......237 TBCSR ......118 Global Output Control QDCSR ....... 236 TBLxR ......
Page 354 Network Port A Status Reg- ........71 Stack Segment Low ister ......213 Register .......54 Network Port A Transmit Stack Segment Register .53 Control Register ..216 Write Protect Segment x Network Port A Transmit High Register ....62 Status Register ..211 Rabbit 4000 Microprocessor User’s Manual...
Page 355 registers (continued) registers registers (continued) Parallel Port A ....73 Parallel Port D (continued) reset ........26 Parallel Port A Data Parallel Port D Drive reset/bootstrap Register ...... 75 Control Register ..94 Slave Port Control Register Slave Port Control Register Parallel Port D Function ........
Page 356 Register .....298 Timer C Block Access use of clocked Serial Port D Serial Port B User Enable Register .....127 ........133 Register .....298 Timer C Block Pointer Serial Port C User Enable Register .....128 Register .....298 Rabbit 4000 Microprocessor User’s Manual...
Page 357 serial ports (continued) specifications (continued) System/User mode (continued) Serial Ports E – F .... 145 clock speeds ....314 overview ......283 asynchronous mode ..145 recommended clock/mem- register descriptions ..294 block diagram ....146 ory configurations ..314 registers ......
Page 358 ..35 primary/secondary watchdog timer bug ....35, 335 secondary watchdog timer .35 settings .......35 Rabbit 4000 Microprocessor User’s Manual...

Rabbit 4000 User Manual

Chapter 1. The Rabbit 4000 Processor

Chapter 2. Clocks

Chapter 3. Reset and Bootstrap

Chapter 4. System Management

Chapter 5. Memory Management

Chapter 6. Interrupts

Chapter 7. External Interrupts

Chapter 8 Parallel Port a

Chapter 9 Parallel Port B

Chapter 10. Parallel Port C

Chapter 11 Parallel Port D

Chapter 12 Parallel Port E

Chapter 13 Timer a

Chapter 14 Timer B

Chapter 15 Timer C

Chapter 16 Serial Ports a - D

Chapter 17 Serial Ports E - F

Chapter 18. Slave Port

Chapter 19. DMA Channels

Chapter 20 10Base-T Ethernet

Chapter 21. Input Capture

Chapter 22. Quadrature Decoder

Chapter 23. Pulse Width Modulator

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Summary of Contents for Rabbit Rabbit 4000