Handling Interrupts; Example Isr - Rabbit 6000 User Manual

5. If using an internal-timed DMA transfer, enable the internal-timed transfer request by writing to
DTRCR. Select the divider value by writing to DTRDLR and DTRDHR. Note that this enable will
be logical-ANDed to any internal DMA enables if the DMA transfer is to/from an internal
peripheral.
6. Select a byte to terminate the transfer on by writing to the appropriate DyTBR and DyTMR regis-
ters.
7. The desired control, length, and address registers should be written to a buffer descriptor (or descrip-
tors) in memory if not done already. Several automatic options (auto-increment, auto-decrement, spe-
cial peripheral enables) can be overridden by settings in DySCR.
8. The initial address registers (DyIAnR) should be loaded with the physical address of the first buffer
descriptor.
9. The buffer descriptor can be loaded and the DMA transfer started by writing to the appropriate bit of
DMALLR or DMALMR.

24.3.1 Handling Interrupts

The DMA interrupt request is cleared automatically when the interrupt is handled. A DMA interrupt will
occur at the end of a transfer for any buffer descriptor that has bit 4 of DyCR set.

24.3.2 Example ISR

A sample interrupt handler is shown below.
dma_isr::
push af
; do something with the data in the current buffer
; the interrupt request is automatically cleared
pop af
ipres
ret
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