Page 1 Rabbit 3000 ™ Microprocessor User’s Manual 019–0108 • 020426–A...
Page 2 Rabbit 3000 Microprocessor User’s Manual Part Number 019-0108 • 020426–A • Printed in U.S.A. ©2002 Rabbit Semiconductor • All rights reserved. Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit 3000 is a trademark of Rabbit Semiconductor.
Page 3: Table Of Contents
................2 1.1 Features and Specifications Rabbit 3000 .................6 1.2 Summary of Rabbit 3000 Advantages ................7 1.3 Differences Rabbit 3000 vs. Rabbit 2000 Chapter 2. Rabbit 3000 Design Features ..............10 2.1 The Rabbit 8-bit Processor vs. Other Processors ..............11 2.2 Overview of On-Chip Peripherals and Features 2.2.1 5 V Tolerant Inputs ........................11...
Page 4 4.2 Open-Drain Outputs Used for Key Scan ........................52 4.3 Cold Boot ......................53 4.4 The Slave Port 4.4.1 Slave Rabbit As A Protocol UART ................... 54 Chapter 5. Pin Assignments and Functions ..................55 5.1 Package Schematic and Pinout ..................56 5.2 Package Mechanical Dimensions 5.2.1 Ball Grid Array Pinout ......................
Page 5 13.1 Hardware Design of Slave Port Interconnection ....................186 13.2 Slave Port Registers ............188 13.3 Applications and Communications Protocols for Slaves 13.3.1 Slave Applications .........................188 13.3.2 Master-Slave Messaging Protocol ..................189 Chapter 14. Rabbit 3000 Clocks ....................191 14.1 Low-Power Design User’s Manual...
Page 6 ..................217 16.6 Memory Current Consumption ..............218 16.7 Battery-Backed Clock Current Consumption ...............219 16.8 Reduced-Power External Main Oscillator Chapter 17. Rabbit BIOS and Virtual Driver ........................221 17.1 The BIOS 17.1.1 BIOS Services ........................221 17.1.2 BIOS Assumptions ........................ 222 ......................222 17.2 Virtual Driver 17.2.1 Periodic Interrupt ........................
Page 7 Chapter 20. Differences Rabbit vs. Z80/Z180 Instructions Chapter 21. Instructions in Alphabetical Order With Binary Encoding Appendix A..................253 A.1 The Rabbit Programming Port ............254 A.2 Use of the Programming Port as a Diagnostic/Setup Port ..................254 A.3 Alternate Programming Port ................255...
Page 8 Rabbit 3000 Microprocessor...
Page 9: Chapter 1. Introduction
C-language development system (Dynamic C). Z-World is providing the soft- ware development tools for the Rabbit 3000. The Rabbit 3000 is easy to use. Hardware and software interfaces are as uncluttered and are as foolproof as possible. The Rabbit has outstanding computation speed for a micro- processor with an 8-bit bus.
Page 10: Features And Specifications Rabbit 3000
FCC or CE EMI tests as long as minimal design precautions are followed. • The Rabbit may be cold-booted via a serial port or the parallel access slave port. This means that flash program memory may be soldered in unprogrammed, and can be reprogrammed at any time without any assumption of an existing program or BIOS.
Page 11 The IRDA protocol is also supported in SDLC format by the two ports that sup- port SDLC. • A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of communication.
Page 12 10-pin connector can be used to download and debug software using Z-World’s Dynamic C and a simple connection to a PC serial port. The incremental cost of the programming port is extremely small. Figure 1-1 shows a block diagram of the Rabbit. Rabbit 3000 Microprocessor...
Page 13 TCLKE, RCLKE TXF, RXF TCLKF, RCLKF PWM[3:0] ID[7:0] IA[5:0] QD1A, QD1B QD2A, QD2B I[7:0] AQD1A, AQD1B AQD2A, AQD2B PC[7,5,3,1] PD[7,5,3,1] PF[7,5,3,1] INT0A, INT1A PG[7,5,3,1] INT0B, INT1B SD[7:0] SA[1:0], /SCS, /SRD, /SWR, /SLAVEATTN Figure 1-1. Rabbit 3000 Block Diagram User’s Manual...
Page 14: Summary Of Rabbit 3000 Advantages
32 kHz or even as slow as 2 kHz. • The Rabbit may be used to create an intelligent peripheral or a slave processor. For example, protocol stacks can be off loaded to a Rabbit slave. The master can be any processor.
Page 15: Differences Rabbit 3000 Vs. Rabbit 2000
1.3 Differences Rabbit 3000 vs. Rabbit 2000 For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rab- bit 3000 is contrasted with the Rabbit 2000 in the table below. Feature Rabbit 3000 Rabbit 2000 Maximum clock speed...
Page 16 Feature Rabbit 3000 Rabbit 2000 Serial ports with support for SDLC/HDLC IrDA None communications Maximum asynchronous baud rate clock speed/8 clock speed/32 Input capture unit None Rabbit 3000 Microprocessor...
Page 17: Chapter 2. Rabbit 3000 Design Features
Rabbit 2000. Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a sub- stantial number of new instructions.
Page 18: The Rabbit 8-Bit Processor Vs. Other Processors
RAM. • The Rabbit 3000 operates at 3.6 V or less, but it has 5 V tolerant inputs and has a sec- ond complete bus for I/O operations that is separate from the memory bus. This second auxiliary bus can be enabled by the application as a designer option.
Page 19: Overview Of On-Chip Peripherals And Features
2.2.1 5 V Tolerant Inputs The Rabbit 3000 operates on a voltage in the range of 1.8 V to 3.6 V, but most Rabbit 3000 input pins are 5 V tolerant. The exceptions are the power supply pins, and the oscillator buffer pins.
Page 20: System Clock
Serial ports A, B, C and D can be operated in the clocked serial mode. In this mode, a clock line synchronously clocks the data in or out. Either the Rabbit serial port or the remote device can supply the clock. When the Rabbit provides the clock, the baud rate can be up to 1/2 of the system clock frequency.
Page 21: Parallel I/O
Applications include communications signaling, pulse width modulation and driving stepper motors. (A separate pulse width modulation facility is also included in the Rabbit 3000.) External Input Filtered Input...
Page 22: Slave Port
2.2.6 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor, which could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data port. The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port.
Page 23: Auxiliary I/O Bus
EMI and ground bounce problems. 5 V signals can appear on the I/O bus since the Rabbit 3000 inputs are 5 V tolerant. 5 V signals could easily cause problems on the main bus if non 5 V tolerant 3.3 V memories are connected.
Page 24: Input Capture Channels
Timer_B2 match reg match preload Figure 2-4. Rabbit Timers A and B 2.2.9 Input Capture Channels The input capture channels are used to determine the time at which an event takes place. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 16 input pins that can be selected as input for either of the two channels.
Page 25: Quadrature Encoder Inputs
The Rabbit 3000 has 2 quadrature encoder units. Each unit has 2 inputs, one being the nor- mal input and the other the 90 degree or quadrature input. An 8 bit up down counter counts encoder steps in the forward and backward direction.
Page 26: Spread Spectrum Clock
2.2.13 Separate Core and I/O Power Pins The silicon die that constitutes the Rabbit 3000 processor is divided into the core logic and the I/O ring. The I/O ring located on the 4 edges of the die holds the bonding pads and the large transistors used to create the I/O buffers that drive signals to the external world.
Page 27: Standard Bios
PC under Windows 32-bit operating systems. Dynamic C provides a combined compiler, editor, and debugger. The usual method for debugging a target system based on the Rabbit is to implement the 10-pin programming connector that connects to the PC serial port via a standard converter cable.
Page 28 Rabbit 3000 Microprocessor...
Page 29: Chapter 3. Details On Rabbit Microprocessor Features
EATURES 3.1 Processor Registers The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are new. The EIR register is the same as the Z80 I register, and is used to point to a table of interrupt vectors for the exter- nally generated interrupts.
Page 30 The registers IX, IY and HL can also serve as index registers. They point to memory addresses from which data bits are fetched or stored. Although the Rabbit can address a megabyte or more of memory, the index registers can only directly address 64K of mem- ory (except for certain extended addressing instructions).
Page 31: Memory Mapping
3.2 Memory Mapping Although the Rabbit memory mapping scheme is fairly complex, the user rarely needs to worry about it because the details are handled by the Dynamic C development system. Except for a handful of special instructions (see Section 19.5, “16-bit Load and Store 20- bit Address”.), the Rabbit instructions directly address a 64K data memory space.
Page 32 The root segment is mapped to the base of flash memory and contains the startup code as well as other code that may happen to be stored there. The data segment usage varies depending on the overall strategy for setting up memory. It may be an extension of Rabbit 3000 Microprocessor...
Page 33 the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or the data segment. Special instructions support executing code that is visible in the XPC segment.
Page 34: Extended Code Space
16-bit variables. The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16- bit address. The Rabbit paging scheme uses the concept of a sliding page, which is 8K long.
Page 35: Separate I And D Space - Extending Data Memory
64k space using 16 bit addresses. The Rabbit 3000 supports separate I and D or Instruction and Data spaces. When separate I and D space is enabled it applies only to addresses in the root segment or data segment.
Page 36 A19 is normally inverted for data accesses to the data segment, causing the data accesses in the data segment to be moved to an address 512k higher in the 20 bit space, an address normally mapped to RAM. The stack segment and the XPC segment do Rabbit 3000 Microprocessor...
Page 37: Using The Stack Segment For Data Storage
not have split I and D space and memory accesses to these segments do not distinguish between I and D space. The advantage of having more root code space is that root code executes faster because short calls using a 16 bit address are used to call it. This compares to long calls that have a 20 bit address for extended code.
Page 38: Practical Memory Considerations
Although the Rabbit can support code size approaching a megabyte, it is anticipated that the majority of applications will use less then 250K of code, equivalent to approximately 10,000–20,000 C statements.
Page 39 Directly accessible C variables are limited to approximately 44K of memory, split between data stored in flash and RAM. This will be more than adequate for many embed- ded applications. Some applications may require large data arrays or tables that will require additional data memory.
Page 40: Instruction Set Outline
Many instructions in the Z180 require a substantial number of additional clocks. The Rabbit usually requires two clocks for each byte of the op code and for each data byte read. Three clocks are needed for each data byte written. One additional clock is required if a memory address needs to be computed or an index register is used for addressing.
Page 41: Load Immediate Data To A Register
I/O space. There are two I/O spaces, internal peripherals and external I/O devices. Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit (see Chapter 20, “Differences Rabbit vs. Z80/Z180 Instructions”). Most of the deleted instructions are obsolete or are little-used instructions that can be emulated by several Rabbit instructions.
Page 42: Load Or Store Data Using An Index Register
; store HL at address pointed to ; by IX plus -128 to +127 offset LD HL,(IX+d) LD HL’,(IX+d) LD (IY+d),HL ; store HL at address pointed to ; by IY plus -128 to +127 offset LD HL,(IY+d) LD HL’,(IY+d) Rabbit 3000 Microprocessor...
Page 43: Register-To-Register Move
The alternate 8-bit registers can be a destination, for example: LD a’,c LD d’,b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of the required prefix byte. Instructions such as are not allowed.
Page 44: Push And Pop Instructions
16-bit operations. The Z180/Z80 has a weak set of 16-bit operations, and as a practical matter the programmer has to resort to combinations of 8-bit operations in order to perform many 16-bit operations. The Rabbit has many new op codes for 16-bit operations, removing some of this weakness.
Page 45 instruction is a special instruction designed to help test the HL register. BOOL BOOL sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed. The flags are set according to the result. can also operate on IX and IY.
Page 46 If the number is unsigned or is to be treated as unsigned for a logical right shift, then an unsigned by unsigned multiply must be per- formed. The problem can be simplified by excluding the case where the multiplier is 2^^15. Rabbit 3000 Microprocessor...
Page 47: Input/Output Instructions
3.3.8 Input/Output Instructions The Rabbit uses an entirely different scheme for accessing input/output devices. Any memory access instruction may be prefixed by one of two prefixes, one for internal I/O space and one for external I/O space. When so prefixed, the memory instruction is turned into an I/O instruction that accesses that I/O space at the I/O address specified by the 16- bit memory address used.
Page 48: How To Do It In Assembly Language-Tips And Tricks
BOOL HL ; -1 to 1, zero to zero. 4 clocks total Logical operator— when HL/DE are 1 or 0. xor HL,DE ADD HL,DE RES 1,l ; 6 clocks total, clear bit 1 result of if 1+1=2 Rabbit 3000 Microprocessor...
Page 49: Comparisons Of Integers
3.4.4 Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation. The zero flag is set if the numbers are equal. With the instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from.
Page 50 A>B (!S & !V & !Z) v (S & V) A<B (S & !V) v (!S & V & !Z) A==B A>=B A<=B Rabbit 3000 Microprocessor...
Page 51: Atomic Moves From Memory To I/O Space
Another method of doing signed compare is to first map the signed integers onto unsigned integers by inverting bit 15. This is shown in Figure 3-8 on page 43. Once the mapping has been performed by inverting bit 15 on both numbers, the comparisions can be done as if the numbers were unsigned integers.
Page 52: Interrupt Structure
3.5 Interrupt Structure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con- trol is transferred to the address of the interrupt service routine. The address of the inter- rupt service routine has two parts: the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt.
Page 53 20 µs. The intention in the Rabbit is that most interrupting devices will use priority 1 level inter- rupts. Devices that need extremely fast response to interrupts will use priority level 2 or 3 interrupts.
Page 54: Multiple External Interrupting Devices
3.5.2 Multiple External Interrupting Devices The Rabbit 3000 has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge-sensitive, meaning that it requests an interrupt only when a rising or falling edge, whichever is specified in the setup registers, takes place.
Page 55: Critical Sections
The privileged instructions to manipulate the IP register are listed below. IPSET 0 ; shift IP left and set priority 00 in bits 1,0 IPSET 1 IPSET 2 IPSET 3 IPRES ; rotate IP right 2 bits, restoring previous priority RETI ;...
Page 56: Computed Long Calls And Jumps
A call to a computed address can be performed by the following code. ; A=xpc, IY=address LD A,newxpc LD IY,newaddress LCALL DOCALL ; call utility routine in the root ; The DOCALL routine DOCALL: LD xpc,a ; SET xpc JP (IY) ; go to the routine Rabbit 3000 Microprocessor...
Page 57: Chapter 4. Rabbit Capabilities
4.1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control. The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock.
Page 58: Pulse Width Modulation To Reduce Relay Power
For example, if the driver is switched to a 75% duty cycle using pulse width modu- lation after the initial period when the relay armature is picked, the holding current will be approximately 75% of the full duty-cycle current and the power consumption will be about 56% as great. Rabbit 2000 Microprocessor...
Page 59: Open-Drain Outputs Used For Key Scan
4.2 Open-Drain Outputs Used for Key Scan The Parallel Port D outputs can be individually programmed to be open drain. This is use- ful for scanning a switch matrix, as shown in Figure 4-2. A row is driven low, then the col- umns are scanned for a low input line, which indicates a key is closed.
Page 60: Cold Boot
Rabbit-based microprocessor board. • If the Rabbit is used as a slave processor, the master processor can cold boot it over via the slave port. This means the slave can operate without any nonvolatile memory. Only RAM is required.
Page 61: The Slave Port
The master can cold boot and download a program to the slave. The master does not have to be a Rabbit processor, but can be any type of pro- cessor capable of reading and writing standard registers.
Page 62: Slave Rabbit As A Protocol Uart
4.4.1 Slave Rabbit As A Protocol UART A prime application for the Rabbit used as a slave is to create a 4-port UART that can also handle the details of a communication protocol. The master sends and receives messages over the slave port.
Page 63: Chapter 5. Pin Assignments And Functions
5. P SSIGNMENTS AND UNCTIONS 5.1 Package Schematic and Pinout VDDIO VSSIO /OE1 /CS2 STATUS /OE0 /CS0 VDDCORE VSSCORE VSSCORE VDDCORE /WE0 VSSIO VDDIO VDDIO VSSIO PC0, TXD PC1, RXD VDDCORE VSSCORE VSSCORE VDDCORE /SCS, I7, PE7 PC2, TXC I6, PE6 PC3, RXC INT1B, I5, PE5 PAC4, TXB...
Page 64: Package Mechanical Dimensions
5.2 Package Mechanical Dimensions Figure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package. Figure 5-2. Mechanical Dimensions Rabbit LQFP Package Rabbit 3000 Microprocessor...
Page 65 Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pat- tern Standard, IPC, Northbrook, IL, 1999.
Page 66: Ball Grid Array Pinout
5.2.1 Ball Grid Array Pinout Rabbit 3000 AT56C55-IZ1T 128 Thin Map TFBGA 10x10 Body, 0.8 mm pitch VDDCORE VSSCORE VSSCORE VDDCORE VDDCORE VSSCORE VSSCORE VDDCORE Figure 5-4. Ball Grid Array Pinout Looking Through the Top of Package Rabbit 3000 Microprocessor...
Page 67: Rabbit Pin Descriptions
5.3 Rabbit Pin Descriptions Table 5-1 lists all the pins on the device, along with their direction, function, and pin num- ber on the package. Table 5-1. Rabbit Pin Descriptions Pin Group Pin Name Direction Function Numbers Numbers LQFP TFBGA...
Page 68 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Function Numbers Numbers LQFP TFBGA PB[7:0] Input / Output I/O Port B 116-123 75,74, 71- PC[7:0] 4 In / 4 Out I/O Port C PD[7:0] Input / Output I/O Port D...
Page 69: Bus Timing
5.4 Bus Timing The external bus has essentially the same timing for memory cycles or I/O cycles. A mem- ory cycle begins with the chip select and the address lines. One clock later, the output enable is asserted for a read. The output data and the write enable are asserted for a write. Address (20 for memory, 16 for I/O) /IOCSn or /CSn /OEn or /IORD and /BUFEN (/BUFEN rd or wr)
Page 70: Description Of Pins With Alternate Functions
PB[2] IOAddr[0] SLAVE_WRB PB[1] CLKA CLKA PB[0] CLKB CLKB PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0] PD[7] ALT_RXA PD[6] ALT_TXA PD[5] ALT_RXB PD[4] ALT_TXB PD[3] PD[2] PD[1] PD[0] PE[7] IOCTLB[7] /SCS (slave chip select) PE[6] IOCTLB[6] Rabbit 3000 Microprocessor...
Page 71 Table 5-2. Pins With Alternate Functions (continued) Pin Name Output Function Input Function Input Capture Option PE[5] IOCTLB[5] INT[1] PE[4] IOCTLB[4] INT[0] PE[3] IOCTLB[3] PE[2] IOCTLB[2] PE[1] IOCTLB[1] INT[1] PE[0] IOCTLB[0] INT[0] PF[7] PWM[3] QRD2_I PF[6] PWM[2] QRD2_Q PF[5] PWM[1] QRD1_I PF[4] PWM[0]...
Page 72: Dc Characteristics
5.6 DC Characteristics 5.6.1 3.3 Volts Table 5-3 outlines the DC characteristics for the Rabbit at 3.3 V over the recommended operating temperature range from T = –40°C to +85°C, V = 3.0 V to 3.6 V. Table 5-3. 3.3 Volt DC Characteristics...
Page 73: Chapter 6. Rabbit Internal I/O Registers
6. R I/O R ABBIT NTERNAL EGISTERS User’s Manual...
Page 74 Table 6-1. Rabbit 3000 Peripherals and Interrupt Service Vectors On-Chip Peripheral ISR Starting Address System Management {IIR, 00h} Memory Management No interrupts Slave Port {IIR, 80h} Parallel Port A No interrupts Parallel Port F No interrupts Parallel Port B No interrupts...
Page 75: Default Values For All The Peripheral Control Registers
(PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros. Table 6-2. Rabbit Internal I/O Registers Register Name...
Page 76 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Port A Data Register PADR 0x30 xxxxxxxx Port B Data Register PBDR 0x40 00xxxxxx Port B Data Direction Register PBDDR 0x47 11000000 Port C Data Register PCDR...
Page 77 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Port E Bit 7 Register PEB7R 0x7F xxxxxxxx Port F Data Register PFDR 0x38 xxxxxxxx Port F Control Register PFCR 0x3C xx00xx00 Port F Function Register PFFR...
Page 78 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset PWM MSB 0 Register PWM0R 0x89 xxxxxxxx PWM LSB 1 Register PWL1R 0x8A xxxxxxxx PWM MSB 1 Register PWM1R 0x8B xxxxxxxx PWM LSB 2 Register PWL2R 0x8C...
Page 79 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Timer A Time Constant 7 Register TAT7R 0xAF xxxxxxxx Timer B Control/Status Register TBCSR 0xB0 xxxxx000 Timer B Control Register TBCR 0xB1 xxxx0000 Timer B MSB 1 Register...
Page 80 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Mnemonic I/O Address Reset Serial Port D Status Register SDSR 0xF3 0xx00000 Serial Port D Control Register SDCR 0xF4 xx000000 Serial Port D Extended Register SDER 0xF5 00000000 Serial Port E Data Register...
Page 81: Chapter 7. Miscellaneous Functions
An oscillator buffer is built into the Rabbit 3000 that may be used to implement the main processor oscillator (Figure 7-1 on page 74). For lowest power an external oscillator may be substituted for the built in oscillator circuit.
Page 82 20 MΩ f/(1,2,4,8,16) CLK32K 300 kΩ Note: peripherals cannot be clocked Reference design for slower than processor 32.768 kHz oscillator peripheral clock Real-Time Watchdog Clock Timer internal external to Rabbit to Rabbit Figure 7-1. Clock Distribution Rabbit 3000 Microprocessor...
Page 83 Table 7-1. Global Control/Status Register (I/O adr = 00h) Global Control/Status Register (GCSR) (Address = 0x00) Bit(s) Value Description No Reset or Watchdog Timer time-out since the last read. The Watchdog Timer timed out. These bits are cleared by a read of this register.
Page 84: Clock Doubler
1% for each 5°C increase or decrease in temperature. The doubled clock is created by xor’ing the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since Rabbit 3000 Microprocessor...
Page 85 the duty cycle of the built-in oscillator can be as asymmetric as 52-48, the clock generated by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are always used.
Page 86 The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme. Rabbit 3000 Microprocessor...
Page 87: Clock Spectrum Spreader
7.3 Clock Spectrum Spreader When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz.
Page 88: Chip Select Options For Low Power
Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing. The Rabbit 3000 has optionally enabled modifi- cations to the chip select behavior that reduce this unnecessary power consumption when the Rabbit 3000 is running at reduced clock speed.
Page 89 When operating in 32 kHz mode it is also possible to further divide the clock to a fre- quency as low as 2 kHz, further reducing execution speed and current consumption. Global Power Save Control Register (GPSCR) (Address = 0x0D) Bit(s) Value Description...
Page 90 ADDR Valid DATA MEMCSxB MEMOExB Figure 7-4. Short Chip Select Memory Read 32KHz ADDR Valid DATA Valid MEMCSxB MEMOExB ~100nS Figure 7-5. Self-Timed Chip Select Memory Read Cycle Rabbit 3000 Microprocessor...
Page 91: Output Pins Clk, Status, /Wdtout, /Bufen
7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN Certain output pins can have alternate assignments as specified in Table 7-4. Table 7-4. Global Output Control Register (GOCR = 0Eh) Bit(s) Value Description CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. CLK pin is low.
Page 92: Time/Date Clock (Real-Time Clock)
Normally this would not be very productive since the cir- cuitry needed to provide the power switchover could also be used to battery-back a regular low-power static RAM. Rabbit 3000 Microprocessor...
Page 93 Table 7-5. Real-Time Clock RTCxR Data Registers Real-Time Clock x Holding Register (RTC0R) R/W (Address = 0x02) (RTC1R) (Address = 0x03) (RTC2R) (Address = 0x04) (RTC3R) (Address = 0x05) (RTC4R) (Address = 0x06) (RTC5R) (Address = 0x07) Bit(s) Value Description Read The current value of the 48-bit RTC holding register is returned.
Page 94: Watchdog Timer
If any have counted down to zero, the interrupt routine disables interrupts, and then enters an endless loop waiting for the reset. Hits of the virtual watchdogs are placed in the user’s program at “must exercise” locations. Rabbit 3000 Microprocessor...
Page 95 Table 7-8. Watchdog Timer Test Register (WDTTR adr = 09h) Bit(s) Value Description Clock the least significant byte of the WDT timer from the peripheral clock. (Intended for chip test and code 54h below only.) Clock the most significant byte of the WDT timer from the peripheral clock.
Page 96: System Reset
7.8 System Reset The Rabbit 3000 contains a master reset input (pin 42), which initializes everything in the device except for the Real Time Clock (RTC). This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory. If no write cycles are in progress the reset takes effect immediately.
Page 97: Rabbit Interrupt Structure
7.9 Rabbit Interrupt Structure An interrupt causes a call to be executed, pushing the PC on the stack and starting to exe- cute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively.
Page 98: External Interrupts
There are two external interrupts. Each interrupt has 2 input pins that can be used to trig- ger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either ris- ing or falling edges. Rabbit 3000 Microprocessor...
Page 99 INT1A [PE1] pulse catcher INT1B [PE5] pulse catcher #1 interrupt acknowledge INT0A [PE0] pulse catcher INT0B [PE4] pulse catcher #0 interrupt acknowledge Figure 7-6. External Interrupt Line Logic The external interrupts take place on a transition of the input, which is programmable for rising, falling or both edges.
Page 100: Interrupt Vectors: Int0 - Eir,00H/Int1 - Eir,08H
; save interrupt priority ipset 1 ; set to priority really desired (1, 2, etc.) ; insert body of interrupt routine here pop ip ; get back entry priority ipres ; restore interrupted routine’s priority ; return from interrupt Rabbit 3000 Microprocessor...
Page 101: Bootstrap Operation
7.10 Bootstrap Operation The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = (0, 0).
Page 102 In asynchronous mode at 2400 bps it takes about 4 ms to send each character, so no problem is likely unless the system clock is extremely slow. Rabbit 3000 Microprocessor...
Page 103: Pulse Width Modulator
7.11 Pulse Width Modulator The Pulse Width Modulator consists of a ten-bit free running counter, and four width reg- isters. Each PWM output is High for "n+1" counts out of the 1024-clock count cycle, where "n" is the value held in the width register. The PWM output High time can option- ally be spread throughout the cycle to reduce ripple on the externally filtered PWM output.
Page 104 (64 counts) (64 counts) n=257, spread (65 counts) (64 counts) (65 counts) (64 counts) n=258, spread (65 counts) (65 counts) (65 counts) (64 counts) n=259, spread (65 counts) (65 counts) (65 counts) (65 counts) n=259, normal (260 counts) Rabbit 3000 Microprocessor...
Page 105: Input Capture
7.12 Input Capture The two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel consists of a sixteen-bit counter that is clocked by the output of Timer A8, and can be connected to one or two out of sixteen parallel port pins. The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt.
Page 106 If the time-stamp feature is not needed, this mode gives the Rabbit 3000 up to four more external interrupt inputs. This mode works well for slower-speed pulse measurement, where the processor has enough time to read the count latched by the Start condition before the Stop condition occurs and latches a new count.
Page 107: Quadrature Decoder
7.13 Quadrature Decoder The two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an in- phase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rota- tion and provide interrupts when the count goes from 00h to FFh or from FFh to 00h.
Page 108 00h or when the counter decrements from 00h to FFh. The timing for the interrupt is shown below. Note that the status bits in the QDSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared by reading the QDSR. Rabbit 3000 Microprocessor...
Page 109: Chapter 8. Memory Interface And Mapping
Static memory chips generally have address lines, data line, a chip select line, an output enable line and a write enable. The Rabbit 3000 has these same lines that can connect directly to a number of static memory chips. The chip selects are not completely inter- changeable because certain chip selects have special functions.
Page 110 (8) Rabbit 3000 static memory flash address Lines (20) /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 static memory Figure 8-2. Typical Memory Chip Connection Rabbit 3000 Microprocessor...
Page 111: Memory Mapping Overview
See Section 3.2, “Memory Mapping,” for a discussion of Rabbit memory mapping. Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interface unit accepts the 20-bit addresses and generates control signals applied directly to the memory chips.
Page 112 STACKSEG = 11h Locates stack segment in physical memory. DATASEG = 12h Locates data segment in physical memory. Table 8-2. Segment Size Register Bits 7..4 Bits 3..0 SEGSIZE = 13h Boundary address stack segment. Boundary address data segment. Rabbit 3000 Microprocessor...
Page 113: Memory Interface Unit
Rabbit. There are three separate chip select output lines (/CS0, /CS1, and /CS2) that can be used to select one of three different memory chips. A field in the control register determines which chip select is selected for memory accesses to the quadrant.
Page 114: Memory Bank Control Registers
1M memory chip in the space normally allocated to a 256K chip. The larger memory can then be accessed as 4 pages of 256K each. There is no effect outside the quadrant that the memory bank control register is controlling. Rabbit 3000 Microprocessor...
Page 115: Optional A16, A19 Inversions By Segment (/Cs1 Enable)
Enable A16 and A19 inversion independent of instruction/data. Enable A16 and A19 inversion (controlled by bits 0-3) for data accesses only. This enables the instruction/data split. This bit is not present in the Rabbit 2000. This is separate I and D space.
Page 116 Normal operation. For an XPC access, use MB0CR independent of A19-A18. For an XPC access, use MB1CR independent of A19-A18. For an XPC access, use MB2CR independent of A19-A18. For an XPC access, use MB3CR independent of A19-A18. Rabbit 3000 Microprocessor...
Page 117: Allocation Of Extended Code And Data
8.6 Allocation of Extended Code and Data The Dynamic C compiler compiles code to root code space or to extended code space. Root code starts in low memory and compiles upward. Allocation of extended code starts above the root code and data. Allocation normally con- tinues to the end of the flash memory.
Page 118: Instruction And Data Space Support
Figure 8-5. In a combined I and D space model the root code segment holds both code and data constants in flash memory. The data segment holds data variables in RAM. In the separate I and D space model the root code segment and the data segment are Rabbit 3000 Microprocessor...
Page 119 mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in flash. In the I space the division between the root segment and the data segment is irrelevant because the DATASEG register contains zero and the division between the segments defined by the lower 4 bits of the SEGSIZE register does not mark a division in physical memory for code space.
Page 120 The user-program variables are allocated by the compiler starting just below the Dynamic C debugger data. The Dynamic C constants start at address zero. User constants are allo- cated stating at a low address just above the Dynamic C constants. Rabbit 3000 Microprocessor...
Page 121: How The Compiler Compiles To Memory
8.8 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory. In any but the smallest programs, most of the code is compiled to extended memory.
Page 122 Rabbit 3000 Microprocessor...
Page 123: Chapter 9. Parallel Ports
ARALLEL ORTS The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below.
Page 124: Parallel Port A
When the port is read, the value read reflects the voltages on the pins, "1" for high and "0" for low. This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage. Rabbit 3000 Microprocessor...
Page 125: Parallel Port B
9.2 Parallel Port B Parallel Port B, has eight pins that can programmed individually to be inputs and outputs. After reset, Parallel Port B comes up as six inputs (PB[5:0]) and two outputs (PB7 and PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low. Table 9-3.
Page 126: Parallel Port C
On reset the active (even-numbered) function register bits are zeroed resulting in Port C to behave as an I/O port. Bit 6 of the Port C data register is zeroed while the remaining even numbered bits are set to 1. Rabbit 3000 Microprocessor...
Page 127: Parallel Port D
9.4 Parallel Port D Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired.
Page 128 ARXA ATXA ARXB ATXB inputs perclk/2 I/O Data Driver—optional open drain Timer A1 Timer B1 Timer B2 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-1. Parallel Port D Block Diagram Rabbit 3000 Microprocessor...
Page 129 Table 9-8. Parallel Port D Register functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDDR (R/W) adr = 060h out = out = out = out = out = out = out = out = PDDCR (W)
Page 130 • PDCR—Parallel Port D control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero. Rabbit 3000 Microprocessor...
Page 131: Parallel Port E
9.5 Parallel Port E Parallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually pro- grammed as inputs or outputs. PE7 is used as the slave port chip select when the slave port is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four of the port E lines can be used as interrupt request inputs.
Page 132 In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with Port E are not initialized on reset. Rabbit 3000 Microprocessor...
Page 133 Table 9-11. Parallel Port E Register functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDR (R/W) adr = 070h PEFR (W) alt /I7 alt /I6 alt /I5 alt /I4 alt /I3 alt /I2 alt /I1 alt /I0...
Page 134: Parallel Port F
PFFR (W) pwm[3] pwm[2] pwm[1] pwm[0] sclk_c sclk_d adr = 03Dh PFDDR (W) dir = dir = dir = dir = dir = dir = dir = dir = adr = 03Fh Rabbit 3000 Microprocessor...
Page 135 Table 9-15. Parallel Port F Control Register (adr = 03Ch) Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 00—clock upper nibble on pclk/2 00—clock lower nibble on pclk/2 01—clock on timer A1 01—clock on timer A1 10—clock on timer B1 10—clock on timer B1 11—clock on timer B2...
Page 136: Parallel Port G
PGFR (W) SOUT_E RCLK_E TCLK_E SOUT_F RCLK_F TCLK_F adr = 04Dh PGDDR (W) dir = dir = dir = dir = dir = dir = dir = dir = adr = 04Fh Rabbit 3000 Microprocessor...
Page 137 Table 9-18. Parallel Port G Control Register (adr= 04Ch) Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 00—clock upper nibble on pclk/2 00—clock lower nibble on pclk/2 01—clock on timer A1 01—clock on timer A1 10—clock on timer B1 10—clock on timer B1 11—clock on timer B2 11—clock on timer B2...
Page 138 Rabbit 3000 Microprocessor...
Page 139: Chapter 10. I/O Bank Control Registers
10. I/O B ONTROL EGISTERS The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I/O bus cycle.
Page 140 NOTE: Refer to Section 3.3.8 for a fix to a bug that manifests itself if an I/O instruction (prefix IOI or IOE) is followed by one of 12 single-byte op codes that use HL as an index register. Rabbit 3000 Microprocessor...
Page 141: Chapter 11. Timers
11. T IMERS There are two timers—Timer A and Timer B. Timer A is intended mainly for generating the clock for various peripherals, baud clock for the serial ports, a periodic clock for clocking Parallel Ports D and E, or for generating periodic interrupts. Timers A1–A7 are general-purpose timers, and Timers A8–A10 are dedicated to specific peripherals.
Page 142: Timer A
The clock input to the serial port can be 8 or 16 times the baud rate for asynchronous mode and 8 times the baud rate for synchronous mode. The maximum asynchronous baud rate with a 11.0592 MHz clock would be (11,059,200/(1*8) = 1,382,400. Rabbit 3000 Microprocessor...
Page 143: Timer A I/O Registers
For seven of the counters (A1–A7), the terminal count condition is reported in a status regis- ter and can be programmed to generate an interrupt. There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has a bit for each timer that indicates if the output pulse for that timer has taken place since the last read of the status register.
Page 144 Bit 0—Write, set to a "1" to enable the clock (perclk/2) for Timer A, set to "zero" to dis- able the clock (perclk/2 in Figure 11-1). Bits 1-7 are written (write only) to enable the interrupt for the corresponding timer. Rabbit 3000 Microprocessor...
Page 145: Practical Use Of Timer A
The control register (TACR) is laid out as shown in Table 11-4. Table 11-4. Timer A Control Register (adr = 0A4h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits 1, 0 00—Interrupt disabled Source A7 Source A6 Source A5 Source A4...
Page 146 (maxi- mum 256 clocks). Then both timers’ reload registers can be set to new values before or after both are clocked. Rabbit 3000 Microprocessor...
Page 147: Timer B
11.2 Timer B Figure 11-1 shows a block diagram of Timer B. The Timer B counter can be driven directly by /2, by that clock divided by 8, or by the output of Timer A1. Timer B perclk has a continuously running 10-bit counter. The counter is compared against two match registers, the B1 match register and the B2 match register.
Page 148: Using Timer B
These bits will become the output bits on the next match pulse. (It is neces- sary to keep a shadow register for the parallel port unless the bit-addressable feature of ports D and E is used.) Rabbit 3000 Microprocessor...
Page 149 If it is desired to read the time from the Timer B counter, either during an interrupt caused by the match pulse or in some other interrupt routine asynchronous to the match pulse, a special procedure needs to be used to read the counter because the upper 2 bits are in a dif- ferent register than the lower 8 bits.
Page 150 Rabbit 3000 Microprocessor...
Page 151: Chapter 12. Rabbit Serial Ports
ERIAL ORTS The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can per- form asynchronous serial communications at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC syn- chronous communications in addition to standard asynchronous communications.
Page 152 Input to timers Timer A7 Serial Port D perclk /2 or perclk prescaled (Timer A1) RCLKE TCLKE Timer A2 Serial Port E RCLKF TCLKF Timer A3 Serial Port F Figure 12-1. Block Diagram of Rabbit Serial Ports Rabbit 3000 Microprocessor...
Page 153 The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster than that in the synchronous mode. Either 7 or 8 data bits may be transmitted and received in the asynchronous mode. The so-called "9th"...
Page 154: Serial Port Register Layout
Transmitting 0D6h Stop Bit Start Bit Bit 0 stop Transmitting 0D6h with 9th bit zero Start Bit 9th bit Stop Bit Signals Shown at Microprocessor Tx Pin Figure 12-2. Functional Block Diagram of a Serial Port Rabbit 3000 Microprocessor...
Page 155 One choice is the peripheral clock—with that choice and a well-chosen crystal frequency for the main oscillator, the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescaling timer A0 at the highest Rabbit clock fre- quencies (see Section A.4 in Appendix A).
Page 156: Serial Port Registers
Serial Port C Address Register SCAR 0xE1 xxxxxxxx Serial Port C Long Stop Register SCLR 0xE2 xxxxxxxx Serial Port C Status Register SCSR 0xE3 0xx00000 Serial Port C Control Register SCCR 0xE4 xx000000 Serial Port C Extended Register SCER 0xE5 00000000 Rabbit 3000 Microprocessor...
Page 157 Table 12-5. Serial Port D Registers Register Name Mnemonic I/O Address Reset Serial Port D Data Register SDDR 0xF0 xxxxxxxx Serial Port D Address Register SDAR 0xF1 xxxxxxxx Serial Port D Long Stop Register SDLR 0xF2 xxxxxxxx Serial Port D Status Register SDSR 0xF3 0xx00000...
Page 158 CRC and closing Flag transmission. In Clocked Write Serial mode writing the data to this register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. Rabbit 3000 Microprocessor...
Page 159 Table 12-10. Long Stop Register All Ports Serial Port x Long Stop Register (SALR) (Address = 0xC2) (SBLR) (Address = 0xD2) (SCLR) (Address = 0xE2) (SDLR) (Address = 0xF2) (SELR) (Address = 0xCA) (SFLR) (Address = 0xDA) Bit(s) Value Description Read Returns the contents of the receive buffer.
Page 160 This bit will cause an interrupt to be latched when it goes from busy to not busy status after the last character has been sent (there are no more data in the transmitter data register). These bits are always zero in async mode. Rabbit 3000 Microprocessor...
Page 161 Table 12-12. Status Register Clocked Serial (Ports A-D only) Serial Port x Status Register (SASR) (Address = 0xC3) (SBSR) (Address = 0xD3) (SCSR) (Address = 0xE3) (SDSR) (Address = 0xF3) Bit(s) Value Description (Clocked serial mode only) The receive data register is empty There is a byte in the receive buffer.
Page 162 The transmitter finished sending a closing Flag. Data written in response to this interrupt will cause at least two Flags to be transmitted between frames. The byte in the receiver buffer is 8 bits. The byte in the receiver buffer is less than 8 bits. Rabbit 3000 Microprocessor...
Page 163 Table 12-14. Serial Port Control Register Ports A and B Serial Port x Control Register (SACR) (Address = 0xC4) (SBCR) (Address = 0xD4) Bit(s) Value Description No operation. These bits are ignored in the Async mode. In clocked serial mode, start a byte receive operation. In clocked serial mode, start a byte transmit operation.
Page 164 Clocked serial mode with external clock. Clocked serial mode with internal clock. The serial port interrupt is disabled. The serial port uses Interrupt Priority 1. The serial port uses Interrupt Priority 2. The serial port uses Interrupt Priority 3. Rabbit 3000 Microprocessor...
Page 165 Table 12-16. Serial Port Control Register Ports E and F Serial Port x Control Register (SECR) (Address = 0xCC) (SFCR) (Address = 0xDC) Bit(s) Value Description No operation. These bits are ignored in the Async mode. In HDLC mode, force receiver in Flag Search mode. No operation.
Page 166 Fast Break termination. At the end of Break a dummy character is written to the buffer, and the receiver can start character assembly after one bit time. Async clock is 16X data rate. Async clock is 8X data rate. These bits are ignored in async mode. Rabbit 3000 Microprocessor...
Page 167 Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only) Serial Port x Extended Register (SAER) (Address = 0xC5) (SBER) (Address = 0xD5) (SCER) (Address = 0xE5) (SDER) (Address = 0xF5) Bit(s) Value Description (Clocked serial mode only) Normal clocked serial operation. Timer synchronized clocked serial operation.
Page 168 Enable RZI coding (1/4th bit cell IRDA-compliant). This mode can only be used with internal clock and NRZ data encoding. Idle line condition is Flags. Idle line condition is all ones. Transmit Flag on underrun. Transmit Abort on underrun. These bits are ignored in HDLC mode. Rabbit 3000 Microprocessor...
Page 169: Serial Port Interrupt
12.3 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts. There is a sepa- rate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3.
Page 170: Transmit Serial Data Timing
Normally, though, the interrupt service routine will return and there will be a final interrupt to give the routine a chance to disable the output buffers, as in the case for RS-485 transmission. Rabbit 3000 Microprocessor...
Page 171: Receive Serial Data Timing
12.5 Receive Serial Data Timing When the receiver is ready to receive data, a falling edge indicates that a start bit must be detected. The falling edge is detected as a different Rx input between two different clocks, the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are sampled at the middle of each data bit and are shifted into the receive shift register.
Page 172: Clocked Serial Ports
SxAR register automatically causes the receiver to start a byte receive operation, eliminating the need for software to issue the Start Receive command. Any data contained in the receive buffer will be read first before being replaced Rabbit 3000 Microprocessor...
Page 173 with new incoming data. Similarly, writing the data to the SxAR register causes the trans- mitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock.
Page 174 This is slightly more complicated since the receiver cannot initiate a message. If the receiver attempts to receive a character and the transmitter is not transmitting, the last bit sent will be received for all eight bits. Rabbit 3000 Microprocessor...
Page 175: Clocked Serial Timing
Figure 12-6. Full-Duplex Clocked Serial Timing Diagram with Internal Clock (Mode 00) 12.7.2 Clocked Serial Timing with External Clock In a system where the Rabbit serial clock is generated by an external device, the clock sig- nal has to be synchronized with the internal peripheral clock (...
Page 176 Valid Figure 12-8. Synchronous Serial Data Receive Timing with External Clock (Mode 00) When clocking the Rabbit externally, the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit . If...
Page 177: Synchronous Communications On Ports E And F
12.8 Synchronous Communications on Ports E and F Serial Port E and F are a dual-function serial ports that can be used in either asynchronous or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead.
Page 178 Mark (FM1). Examples of these encodings are shown in the Figure below. Note that in NRZI, Biphase-Space and Biphase-Mark the signal level does not convey information. Rather it is the placement of the transitions that determine the data. In Biphase-Level it is the polarity of the transition that determines the data. Rabbit 3000 Microprocessor...
Page 179 Serial Clock NRZ Data NRZI NRZI Biphase-Level Biphase-Space Biphase-Space Biphase-Mark Biphase-Mark data "1" "0" "1" "1" "0" "0" "1" "0" In HDLC mode the internal clock comes from the output of Timer A2. This timer output is divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop (DPLL) to form the receive clock.
Page 180 Bi-L adj ignore transitions subtract one none add one ignore transitions Bi-L Clock Bi-S adj none add one ignore transitions subtract one none Bi-S Clock Bi-M adj none add one ignore transitions subtract one none Bi-M Clock Rabbit 3000 Microprocessor...
Page 181: Serial Port Software Suggestions
With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell. If a transition occurs after the expected bit- cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up the bit-cell boundaries.
Page 182 ; 4 mask such as 11110000 if 16 buffer locs dec hl ld (hl),a ; 6 update the in pointer ioi ld a,(SCDR) ; 11 get data register port C, clears interrupt request ipres ; 4 restore the interrupt priority ; 68 clocks to here Rabbit 3000 Microprocessor...
Page 183: Controlling An Rs-485 Driver And Receiver
; to level before interrupt took place ; more interrupts could now take place, ; but receiver data is in registers ; now handle the rest of the receiver interrupt routine ld hl,bufbase ld d,0 add hl,de ; 2 location to store data ld (hl),a 6 put away the data byte pop de...
Page 184: Transmitting And Detecting A Break
Certain systems, such as some 8051-based multidrop communications systems, use a 9th data bit to mark the start of a message frame. The Rabbit 3000 can receive parity or message formats that contain a 9th bit without problem. Transmitting messages with parity or messages that always contain a 9th bit is also possible.
Page 185: Parity, Extra Stop Bits With 7-Data-Bit Characters
"1." Setting the 9th bit high or low can easily be done in the Rabbit 3000. The 9th bit can be set low by a write to the Serial Port A-F Address Register (SxAR) and the 9th bit can be set high by a write to the Serial Port A-F Long Stop Register (SxLR).
Page 186: Supporting 9Th Bit Communication Protocols
9th bit only by using special drivers. 12.9.9 Rabbit-Only Master/Slave Protocol If only Rabbit microprocessors are connected, the 9th bit low can be set on the address byte, and the remaining bytes can be transmitted in the normal 8-bit mode. This is more efficient than other 9th bit protocols because only the first byte requires 11 baud times;...
Page 187 the receiving interrupt service routine to detect this gap, it is suggested that dummy char- acters be transmitted to help detect the gap. This can be done in the following manner. The transmitter starts transmitting dummy characters when the first character interrupt is received.
Page 188 Rabbit 3000 Microprocessor...
Page 189: Chapter 13. Rabbit Slave Port
The slave port is a part of the slave Rabbit, but logically it is an independent device that is used to communicate between the two processors. A diagram of the slave port is shown in Figure 13-1.
Page 190 The registers appear to be internal I/O registers to the slave. To the master, at least for a Rabbit master, the registers appear to be external I/O registers. The figure below shows the sequence of events when the master reads/writes the slave port registers.
Page 191 The following table explains the parameters used in Figure 13-2. Minimum Maximum Symbol Parameter (ns) (ns) Tsu(SCS) /SCS Setup Time — Th(SCS) /SCS Hold Time — Tsu(SA) SA Setup Time — Th(SA) SA Hold Time — Tw(SRD) /SRD Low Pulse Width —...
Page 192 There is no requirement that the master and slave share a clock, but doing so makes it unnecessary to connect a crystal to the slaves. Each Rabbit in Figure 13-4 has to have RAM memory. The master must also have flash memory. However, the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program.
Page 193 • /SCS—Input. Slave chip select. The slave ignores read or write requests unless the chip select is low. If a Rabbit is used as a master, this line can be connected to one of the master’s programmable chip select lines /I0–/I7.
Page 194: Hardware Design Of Slave Port Interconnection
Figure 13-4 shows a typical circuit diagram for connecting two slave Rabbits to a master Rabbit. The designer has the option of cold-booting the slave and downloading the pro- gram to RAM on each cold start. Another option is to configure the slave with both RAM and flash memory.
Page 195 If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register, the user should be aware that all the bits might not change at the exact same time when the result changes, and a transitional value could be read from the register where some bits have changed to the new value and others have not.
Page 196: Applications And Communications Protocols For Slaves
Some possible applications are listed below. Keep in mind that the Rabbit can also be operated as a slave processor via a serial port and some of the protocols will work well via a serial communications connection. If a serial connection is used, the protocol becomes more complicated if errors in transmission need to be taken into account.
Page 197: Master-Slave Messaging Protocol
A typical slave system consists of a Rabbit microprocessor and a RAM memory con- nected to it. The clock can be provided either by connecting a crystal, or crystals to the slave or by providing an external clock, which could be the master’s clock.
Page 198 SPD1R and write a code to SPD0R indicating transmit and channel number. This will cause the slave to be interrupted, and the slave will take the character and handshake by reading SPD0R. This handshake does not interrupt the master. Rabbit 3000 Microprocessor...
Page 199: Chapter 14. Rabbit 3000 Clocks
ABBIT LOCKS The Rabbit 3000 normally uses two clocks, the main clock and the 32.768 kHz clock. The 32.768 kHz clock is needed for the battery-backable clock, the watchdog timer, and the cold-boot function. The main oscillator provides the run-time clock for the microproces- sor.
Page 200 The Rabbit 2000 does not have a "standby" mode that some microprocessors have. Instead, the Rabbit has the ability to switch its clock to the 32.768 kHz oscillator. This is called the sleepy mode. When this is done, the power consumption is decreased dramatically. The current consumption is often reduced to the region of 100 µA at this clock speed.
Page 201: Chapter 15. Emi Control
The high speed clock on PC board traces is a major cause of EMI. If all the EMI suppression features of the Rabbit 3000 are properly utilized and low EMI design techniques are used on the printed circuit board, system EMI will likely be reduced to a very low level, probably much lower than is necessary to pass government tests.
Page 202: Power Supply Connections And Board Layout
15.1 Power Supply Connections and Board Layout The Rabbit die and package are schematically shown in Figure 15-1 below. The die is divided into two power supply regions, the core and I/O ring. (A third power-supply region, the battery-backable region exists but is not important for EMI.) The core is pro- vided power by means of 8 pins, 4 of which are grounds and 4 of which provide nominal 3.3 V power.
Page 203 100 MHz region, than a larger 10 or 100 nF capacitor would. 10 nF and 100 nF capacitors can be distributed between the ground and power planes to provide bulk decou- pling for the power supply. Rabbit 3000 Core Ring Figure 15-2.
Page 204: Noise Generated In The I/O Ring
In addition, a series ferrite can be placed between VCC and the decoupling capacitor at each pin. However, these measures are probably overkill for the Rabbit 3000, especially when the spectrum spreader is enabled. 15.1.1 Noise Generated in the I/O Ring Any noise on the I/O ring power rails will propagate to all output pins, thus spreading potential EMI.
Page 205: Using The Clock Spectrum Spreader
15.2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 dB. This is a very large reduction since it is common to struggle to reduce EMI by 5 dB in order to pass government tests.
Page 206 The effect of pure harmonic noise on an FM station is to either completely block out a sta- tion near the harmonic frequency or to disturb reception of that station. If the spectrum spreader is engaged then interference will be spread across the band but will generally be Rabbit 3000 Microprocessor...
Page 207 so low as to be undetectable, except perhaps for extremely weak stations. The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station’s band. If the spreader is engaged the pattern will disappear unless the station is very weak, in which case the interference will be seen as noise distrib- uted over the screen.
Page 208 Rabbit 3000 Microprocessor...
Page 209: Chapter 16. Ac Timing Specifications
IMING PECIFICATIONS The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at temperatures from –40°C to +85°C with use possible use over the extended range -55°C to +105°C. For long life it is desirable not to exceed a die temperature of 125°C. Most users will operate the Rabbit at 3.3 V.
Page 210 If the doubler is not enabled, then every clock is shortened during the low part of the clock period. The maxi- mum shortening for a pair of clocks combined is shown in the table. Rabbit 3000 Microprocessor...
Page 211 Figure 16-2 and Figure 16-3 illustrate the memory and I/O read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified. Memory Read (no wait states) valid valid Memory Write (no extra wait states)
Page 212 Clock to memory write strobe delay (T 6 ns 8 ns 11 ns The measurements were taken at the 50% points under the same conditions that the mem- ory read delays were measured. See Table 16-2 for delays at other voltages. Rabbit 3000 Microprocessor...
Page 213 External I/O Read (no extra wait states) valid valid External I/O Write (no extra wait states) valid valid Figure 16-3. I/O Read and Write Cycles No Extra Wait States User’s Manual...
Page 214 The measurements were taken at the 50% points under the same conditions that the I/O read delays were measured. I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified. See Table 16-2 for delays at other voltages. Rabbit 3000 Microprocessor...
Page 215 Figure 16-4 illustrates the sources that create memory access time delays. clock period shortening due to spectrum spreader clock address data out clock to data in setup time address memory access output time output enable (early) memory output enable time Figure 16-4.
Page 216 Max. delay @ 1.8 V = 12.2 + 2.7(n - 6) Min. delay @ 1.8 V = 6.6 + 1.44(n - 6) 60.0 50.0 40.0 3.3 V 30.0 2.5 V 1.8 V 20.0 10.0 Nominal Delay (ns) Figure 16-5. Clock Doubler Max-Min Clock Low Times Rabbit 3000 Microprocessor...
Page 217 The following factors have to be taken into account when calculating the output enable access time required. • The gross output enable access time is T + minimum clock low time (it is asusmed that the early output enable option is enabled) This is reduced by the spectrum spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetery of the original oscillator clock.
Page 218: Further Discussion Of Bus And Clock Timing
The early write pulse option can be used to ensure a long-enough write pulse, but then it must be ensured that the write pulse does not begin before the address lines have stablized. Rabbit 3000 Microprocessor...
Page 219 Oscillator Oscillator delayed and inverted Doubled clock Delay time 0.48P 0.52P 0.48P 0.52P Address / CS Example Write Data out Cycle write pulse early write pulse option Address / CS Example data out from mem Read output enb Cycle early output enb option Figure 16-6.
Page 220: Power And Current Consumption
16.3 Power and Current Consumption With the Rabbit 3000 it is possible to design systems that perform their task with very low power consumption. Unlike competitive processors, the Rabbit 3000 has short chip select features designed to minimize power consumption by external memories, which can easily become the dominent power consumers at low clock frequencies if not well handled.
Page 221 Clock Frequency (MHz) Figure 16-7. Rabbit 3000 System Current vs. Frequency at 3.3 V xtal=25.80 xtal=14.74 xtal=11.05 xtal=3.68 Clock Frequency (MHz) Figure 16-8. Rabbit 3000 System Current vs. Frequency at 3.3 V User’s Manual...
Page 222 CMOS leakage may consume several µA, increasing with higher temperatures. The graph below shows current consumption including the tiny logic core, but not including memory or the reset controller. 1.8V 2.2V 2.7V 3.0V 3.3V 2.048 4.096 8.192 16.384 32.768 Clock Frequency (kHz) Figure 16-9. Sleepy Mode Current Consumption Rabbit 3000 Microprocessor...
Page 223: Current Consumption Mechanisms
16.4 Current Consumption Mechanisms The following mechanisms are important for the current consumption of the Rabbit 3000 while it is operating. 1. A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances. At 3.3 V (see 2 below) approximately 57% of the current is due to charging and 43% to crossover current.
Page 224: Sleepy Mode Current Consumption
Leakage, the standby current of the reset generator, the current consumption of the oscilla- tor and the real-time clock, and the current consumption of memories must be added to the sleepy mode current consumption. Generally the self-timed chip select mode is used to reduce memory current consumption. Rabbit 3000 Microprocessor...
Page 225: Memory Current Consumption
16.6 Memory Current Consumption Since there are many different memories available, let’s look at an example using one of the recommended flash and SRAM memories. Flash memory—SST part SST39LF512020, 256K × 8, 45 ns access time. Standby cur- rent: nil. •...
Page 226: Battery-Backed Clock Current Consumption
Below about 1.4 V most of the current draw is used to charge and discharge the capactive load. The current consumed by the battery-backed portion of the Rabbit 3000, which is driven by the 32.768 kHz oscillator, is given by Irab = 0.91×V...
Page 227: Reduced-Power External Main Oscillator
The power consumption is less because of the current- limiting resistors that cannot be used with the built-in buffer. The 2.2 kΩ series resistor must be reduced as the clock frequency increases, as must be the current-limiting resistors. To Rabbit 3000 XTALA1 SN74HCT1G04DBVR...
Page 228 Rabbit 3000 Microprocessor...
Page 229: Chapter 17. Rabbit Bios And Virtual Driver
IRTUAL RIVER When a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is auto- matically incorporated into the program. Virtual Driver is the name given to some initial- ization routines and a group of services performed by the periodic interrupt. The Rabbit BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is compiled to the target along with the application program.
Page 230: Bios Assumptions
Processors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is expected to be connected to /CS0, /WE0, and /OE0. (See the Rabbit 3000 Designer’s Handbook Memory Planning chapter if you want to design a board with RAM only.) The crystal frequency is expected to be n*1.8432 MHz.
Page 231 gram consistency checking or because a part of the program that should be executing peri- odically is not executing and the watchdog times out. The Virtual Driver’s periodic interrupt hits the hardware watchdog timer with a 2 second time-out. If the periodic interrupt stops working, then the watchdog will time out after 2 seconds.
Page 232 Rabbit 3000 Microprocessor...
Page 233: Chapter 18. Other Rabbit Software
Dynamic C libraries also provide functions to change clock speeds to enter and exit sleepy mode. See the Rabbit 3000 Designer’s Handbook chapter Low Power Design and Sup- port for more details. User’s Manual...
Page 234: Reading And Writing I/O Registers
18.2 Reading and Writing I/O Registers The Rabbit has two I/O spaces: internal I/O registers and external I/O registers. 18.2.1 Using Assembly Language The fastest way to read and write I/O registers in Dynamic C is to use a short segment of assembly language inserted in the C program.
Page 235: Shadow Registers
18.3 Shadow Registers Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates on the chip, making possible greater capability at lower cost. Write-only registers are eas- ier to use if a memory location, called a shadow register, is associated with each write- only register.
Page 236: Write-Only Registers Without Shadow Registers
For example, a write to the status register in the Rabbit serial ports is used to clear the transmitter interrupt request, but the data bits are ignored, and the status register is actually a read-only register except for the special functionality attached to the act of writing the register.
Page 237 Two library functions are provided to read and write the real-time clock: unsigned long int read_rtc(void) ; // read bits 15-46 rtc void write_rtc(unsigned long int time) ; // write bits 15-46 // note: bits 0-14 and bit 47 are zeroed However, it is not intended that the real-time clock be read and written frequently.
Page 238 Rabbit 3000 Microprocessor...
Page 239: Chapter 19. Rabbit Instructions
19. R ABBIT NSTRUCTIONS Summary “Load Immediate Data” on page 234 “8-bit Indexed Load and Store” on page 234 “16-bit Indexed Loads and Stores” on page 234 “16-bit Load and Store 20-bit Address” on page 235 “Register to Register Moves” on page 235 “Exchange Instructions”...
Page 240 L/V is set to 1 for logical operations if any of the four most significant bits of the result are 1, and L/V is reset to 0 if all four of the most significant bits of the result are 0. Rabbit 3000 Microprocessor...
Page 241 Symbols Rabbit Z180 Meaning Bit select: 000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7 Condition code select:...
Page 242: Load Immediate Data
- - - - L = (IX+d); H = (IX+d+1) LD (IY+d),HL d - - - - (IY+d) = L; (IY+d+1) = H LD HL,(IY+d) s - - - - L = (IY+d); H = (IY+d+1) Rabbit 3000 Microprocessor...
Page 243: 16-Bit Load And Store 20-Bit Address
19.5 16-bit Load and Store 20-bit Address Instruction I S Z V C Operation LDP (HL),HL - - - - (HL) = L; (HL+1) = H. (Adr[19:16] = A[3:0]) LDP (IX),HL - - - - (IX) = L; (IX+1) = H. (Adr[19:16] = A[3:0]) LDP (IY),HL - - - -...
Page 244: Exchange Instructions
HL = HL + ss + CF -- ss=BC, DE, HL, SP ADD HL,ss - - - * HL = HL + ss ADD IX,xx - - - * IX = IX + xx -- xx=BC, DE, IX, SP Rabbit 3000 Microprocessor...
Page 245: 8-Bit Arithmetic And Logical Ops
ADD IY,yy - - - * IY = IY + yy -- yy=BC, DE, IY, SP ADD SP,d - - - * SP = SP + d -- d=0 to 255 AND HL,DE * * L 0 HL = HL & DE AND IX,DE * * L 0 IX = IX &...
Page 246: 8-Bit Bit Set, Reset And Test
(HL) = (HL) + 1 INC (IX+d) b * * V - (IX+d) = (IX+d) + 1 INC (IY+d) b * * V - (IY+d) = (IY+d) + 1 INC r * * V - r = r + 1 Rabbit 3000 Microprocessor...
Page 247: 8-Bit Fast A Register Operations
19.13 8-bit Fast A register Operations Instruction I S Z V C Operation - - - - A = ~A * * V * A = 0 - A - - - * {CY,A} = {A,CY} RLCA - - - * A = {A[6,0],A[7]};...
Page 248: Instruction Prefixes
Interrupts can occur between dif- ferent repeats, but not within an iteration equivalent to LDD or LDI. Return from the inter- rupt is to the first byte of the instruction which is the I/O prefix byte if there is one. Rabbit 3000 Microprocessor...
Page 249: Control Instructions - Jumps And Calls
19.17 Control Instructions - Jumps and Calls Instruction I S Z V C Operation CALL mn - - - - (SP-1) = PCH; (SP-2) = PCL; PC = mn; SP = SP-2 DJNZ j - - - - B = B-1; if {B != 0} PC = PC + j JP (HL) - - - - PC = HL...
Page 250: Privileged Instructions
If an interrupt was allowed between the and set instructions, another routine could set the semaphore and two routines could think that they both owned the semaphore. Rabbit 3000 Microprocessor...
Page 251: Chapter 20. Differences Rabbit Vs. Z80/Z180 Instructions
ABBIT VS NSTRUCTIONS The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. The more important instructions that were dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler.
Page 252 R register LD IIR,A LD A,IIR ; was I register The following Z80/Z180 instructions have been dropped and are not supported. Alterna- tive Rabbit instructions are provided. Z80/Z180 Instructions Dropped Rabbit Instructions to Use CALL CC,ADR JR (JP) ncc,xxx ; reverse condition...
Page 253: Chapter 21. Instructions In Alphabetical Order With Binary Encoding
21. I NSTRUCTIONS IN LPHABETICAL RDER INARY NCODING Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag Description ALTD selects alternate flags ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI and IOE (“I” Column) Symbol Key Flag Description IOI and IOE affect source and destination...
Page 254 Word register select: 00 = BC, 01 = DE, 10 = HL, 11 = AF Logical zero if all four of the most significant bits of the result are 0. † Logical one if any of the four most significant bits of the result are 1. Rabbit 3000 Microprocessor...
Page 255 Instruction Byte 1 Byte 2 Byte 3 Byte 4 I S Z V C ADC A,(HL) 10001110 s * * V * ADC A,(IX+d) 11011101 10001110 ----d--- s * * V * ADC A,(IY+d) 11111101 10001110 ----d--- s * * V * ADC A,n 11001110 ----n---...
Page 256 LD (mn),ss 11101101 01ss0011 ----n--- ----m--- d - - - - LD (SP+n),HL 11010100 ----n--- - - - - LD (SP+n),IX 11011101 11010100 ----n--- - - - - LD (SP+n),IY 11111101 11010100 ----n--- - - - - Rabbit 3000 Microprocessor...
Page 257 Instruction Byte 1 Byte 2 Byte 3 Byte 4 I S Z V C LD A,(BC) 00001010 s - - - - LD A,(DE) 00011010 s - - - - LD A,(mn) 00111010 ----n--- ----m--- s - - - - LD A,EIR 11101101 01010111...
Page 258 11001011 ----d--- 00011110 b * * L * RR DE 11111011 * * L * RR HL 11111100 * * L * RR IX 11011101 11111100 * * L * RR IY 11111101 11111100 * * L * Rabbit 3000 Microprocessor...
Page 259 Instruction Byte 1 Byte 2 Byte 3 Byte 4 I S Z V C RR r 11001011 00011-r- * * L * 00011111 - - - * RRC (HL) 11001011 00001110 b * * L * RRC (IX+d) 11011101 11001011 ----d--- 00001110 b * * L * RRC (IY+d)
Page 260 Rabbit 3000 Microprocessor...
Page 261: Appendix
CMOS driver. The STATUS pin is used to by the Rabbit-based target to request attention when a breakpoint is encountered in the target under test. The SMODE pins are pulled up by a +5 V/+3 V level from the interface.
Page 262: Use Of The Programming Port As A Diagnostic/Setup Port
Port C. Using these two ports plus the STATUS pin as an output clock, the user can create a synchronous clocked communication port using instructions to toggle the clock and data. Another Rabbit-based board can be used to translate the clocked serial signal to Rabbit 3000 Microprocessor...
Page 263: Suggested Rabbit Crystal Frequencies
A.4 Suggested Rabbit Crystal Frequencies Table A-1 provides a list of suggested Rabbit operating frequencies. The crystal can be half the operating frequency if the clock doubler is used up to approximately 29.5 MHz.
Page 264 14.7456 14.7456 29.4912 14.7456 36.8640 36.8640 18.4320 18.4320 36.864 18.4320 44.2368 44.2368 22.1184 22.1184 44.2368 22.1184 on stock crystals Non stock Non stock crystals crystals 40.5504 20.2752 40.5504 20.2752 42.3936 40.5504 21.1968 20.2752 42.3936 21.1968 42.3936 21.1968 Rabbit 3000 Microprocessor...
Page 265: Legal Notice
Specifications are based on characterization of tested sample units rather than testing over temperature and voltage of each unit. Rabbit Semiconductor products may qualify components to operate within a range of parameters that is different from the manufacturer’s recommended range.

Rabbit 3000 User Manual

Chapter 1. Introduction

Chapter 2. Rabbit 3000 Design Features

Chapter 3. Details on Rabbit Microprocessor Features

Chapter 4. Rabbit Capabilities

Chapter 5. Pin Assignments and Functions

Chapter 6. Rabbit Internal I/O Registers

Chapter 7. Miscellaneous Functions

Chapter 8. Memory Interface and Mapping

Chapter 9. Parallel Ports

Chapter 10. I/O Bank Control Registers

Chapter 11. Timers

Chapter 12. Rabbit Serial Ports

Chapter 13. Rabbit Slave Port

Chapter 14. Rabbit 3000 Clocks

Chapter 15. EMI Control

Chapter 16. AC Timing Specifications

Chapter 17. Rabbit BIOS and Virtual Driver

Chapter 18. Other Rabbit Software

Chapter 19. Rabbit Instructions

Chapter 20. Differences Rabbit Vs. Z80/Z180 Instructions

Chapter 21. Instructions in Alphabetical Order with Binary Encoding

Appendix

Legal Notice

Quick Links

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Summary of Contents for Rabbit Rabbit 3000