Dma With Peripherals - Rabbit 6000 User Manual

24.3.6 DMA with Peripherals

When the DMA is directed towards an internal I/O address, the DMA transfer request signals will be con-
nected as appropriate for that peripheral. For example, when a DMA transfer is performed to Serial Port
D's data register, the transfer request will be enabled whenever the serial port transmit buffer is empty, and
will be disabled whenever it is not.
24.3.6.1 DMA with HDLC Serial Ports
The HDLC serial ports receive special handing by the DMA. When the DMA destination is Serial Port E's
or Serial Port F's data register (SxDR), the final byte of the transfer will be written to the appropriate last
data register (SxLDR) as required to complete an HDLC packet and append the CRC value. In addition,
the value in the appropriate status register (SxSR) will be written to the status byte in the buffer descriptor
pointed to by the initial address registers (not necessarily the buffer descriptor that is currently being used).
These features allow an application to automatically send and receive packets via DMA, only requiring
direct handling of a packet when an error occurs.
24.3.6.2 DMA with Ethernet
The Ethernet network peripheral also receives special handing by the DMA. When the DMA destination is
the network data register (NBDR), the final byte of the transfer will be written to the last data register
(NBLDR) as required to complete an Ethernet packet and append the CRC value. The Ethernet network
peripheral also has support for DMA fly-by transfers between the peripheral and external memory.
24.3.6.3 DMA with Wi-Fi
The Wi-Fi network peripheral has support for DMA fly-by transfers between the peripheral and memory.
However, the Wi-Fi peripheral has a minimum access time of 75 ns and typically requires wait states, so
fly-by DMA may not be the most efficient access method. There are two registers, NCCWR and NCDWR,
that set the wait states for access to the Wi-Fi peripheral, both directly and via DMA.
24.3.6.4 DMA with USB
The USB network peripheral has support for DMA fly-by transfers between the peripheral and memory.
However, the USB peripheral has a minimum access time of 250 ns and typically requires wait states, so
fly-by DMA may not be the most efficient access method.
24.3.6.5 DMA with PWM and Timer C
The PWM and Timer C peripherals have special support for DMA — the block access and pointer regis-
ters in each of these peripherals provide a means for the DMA to update the settings of these peripherals at
some desired rate. This allows complex PWM waveforms to be generated by using the DMA timed
request to update the PWM duty cycles at regular intervals.
digi.com
Rabbit 6000 User's Manual 263