DMA Timed Request Control Register
Bit(s)
Value
7
0
1
6
5:4
00
01
10
11
3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DMA Timed Request Divider Low Register
Bit(s)
Value
7:0
Write
Rabbit 6000 User's Manual
Timed DMA request disabled.
Timed DMA request enabled.
These bits are reserved and should be written with zeros.
Timed DMA request transfers one byte per request.
This bit combination is reserved and should not be used.
Timed DMA request triggers transfers until current descriptor is
complete. DMA channel fetches the next descriptor if appropriate.
This bit combination is reserved and should not be used.
Timed DMA request supplied to DMA Channel 0.
Timed DMA request supplied to DMA Channel 1.
Timed DMA request supplied to DMA Channel 2.
Timed DMA request supplied to DMA Channel 3.
Timed DMA request supplied to DMA Channel 4.
Timed DMA request supplied to DMA Channel 5.
Timed DMA request supplied to DMA Channel 6.
Timed DMA request supplied to DMA Channel 7.
Timed DMA request supplied to DMA Channel 8.
Timed DMA request supplied to DMA Channel 9.
Timed DMA request supplied to DMA Channel 10.
Timed DMA request supplied to DMA Channel 11.
Timed DMA request supplied to DMA Channel 12.
Timed DMA request supplied to DMA Channel 13.
Timed DMA request supplied to DMA Channel '4.
Timed DMA request supplied to DMA Channel 15.
The eight LSBs of the limit value for the DMA timed request timer are
stored.
digi.com
(DTRCR)
(Address = 0x0115)
Description
(DTRDLR)
(Address = 0x0116)
Description
270
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