Rabbit 6000 User Manual page 162

interrupts but the timers themselves cannot. They have the option of being cascaded from Timer A12 to
provide a larger range of frequencies.
The individual Timer A capabilities are summarized in the table below. There is a bit in the control/status
register to disable all 12 timers globally.
Timer
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
There is one interrupt vector for Timer A and a common interrupt priority. A common status register
(TACSR) has bits for Timers A1–A7 that indicate if the output pulse for that timer has taken place since the
last read of the status register. These bits are cleared when the status register is read. No bit will be lost.
Either it will be read by the status register read or it will be set after the status register read is complete. If a
bit is on and the corresponding interrupt is enabled, an interrupt will occur when priorities allow. However, a
separate interrupt is not guaranteed for each bit with an enabled interrupt. If the bit is read in the status regis-
ter, it is cleared and no further interrupt corresponding to that bit will be requested. It is possible that one bit
will cause an interrupt, and then one or more additional bits will be set before the status register is read. After
these bits are cleared, they cannot cause an interrupt. The proper rule to follow is for the interrupt routine to
handle all bits that it sees set.
Rabbit 6000 User's Manual
Cascadable
Interrupt
from
None Yes
A1 Yes
A1 Yes
A1 Yes
A1 Yes
A1 Yes
A1 Yes
A12 No
A12 No
A12 No
A12 No
None No
digi.com
Associated Peripheral
Parallel Ports D–E, Timers
B–C
Serial Port E
Serial Port F
Serial Port A
Serial Port B
Serial Port C
Serial Port D
Input Capture
Pulse-Width Modulator
Quadrature Decoder
Timer B, Timer C
Timers A8–A11
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