Rabbit 6000 User Manual page 25

When the clock doubler is used and there is no subsequent division of the clock, the output clock will be
asymmetric, as shown in Figure 2.3.
Figure 2.3 Effect of Clock Doubler
The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters,
temperature, and voltage. The times given above are for a core supply voltage of 1.8 V and a temperature
of 25°C. The values increase or decrease by 1% for each 5°C increase or decrease in temperature. The
doubled clock is created by xor'ing the delayed and inverted clock with itself. If the original clock does
not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle
of the built-in oscillator can be as asymmetric as 52%/48%, the clock generated by the clock doubler will
exhibit up to a 4% variation in period on alternate clocks. The memory access time is not affected because
the memory bus cycle is 2 clocks long and includes both a long and a short clock, resulting in no net change
due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be
affected slightly.
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Rabbit 6000 User's Manual 25