20.2.4 Interrupts
In the asynchronous mode, a serial port interrupt will be generated whenever any of the following
occurs:
• A byte is available in the receive buffer.
• A byte is moved from the transmit buffer to the transmitter.
• The transmitter becomes idle.
These occurrences correspond to bits 7, 3, and 2 of the Serial Port Status Registers.
In the HDLC mode, interrupts are also generated by the reception of an end-of-frame (with abort,
valid CRC, or CRC error), at the end of a transmission of a CRC, by an abort sequence, or by a
closing flag.
The serial port interrupt vectors are located in the IIR as follows:
• Serial Port E at offset 0x1C0
• Serial Port F at offset 0x1D0
Each of them can be set as Priority 1, 2, or 3 in SxCR, where x is E – F for the two serial ports.
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