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HD151TS207SS
2
I
C Controlled Register Bit Map (cont.)
Table4 CPU Clock Power Management Truth Table
Signal
Pin
PWRDWN#
CPU[2:0]
1
CPU[2:0]
0
CPU[2:0]
0
Note:
1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 )
Table5 SRC Clock Power Management Truth Table
Signal
Pin
Pin
PWRDWN#
PCI_STOP#
SRC
1
1
SRC
1
0
SRC
1
0
SRC
0
X
SRC
0
X
Note:
1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA
Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 )
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 )
Byte3 Control Register
Bit
Description
7
PCI_Stop control
6
PCI_6 Output enable
5
PCI_5 Output enable
4
PCI_4 Output enable
3
PCI_3 Output enable
2
PCI_2 Output enable
1
PCI_1 Output enable
0
PCI_0 Output enable
Rev.1.00, Apr.25.2003, page 9 of 38
PWRDWN#
Tristate Bit
Byte2[5:3]
X
0
1
PCI_STOP#
PWRDWN#
Tristate Bit
Tristate Bit
Byte2[6]
Byte2[7]
X
X
0
X
1
X
X
0
X
1
Contents
0 = Enabled, all stoppable PCI
and SRC clocks are stopped.
1 = Disabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Non-Stop
Note
Outputs
Byte1[5:3] = 1
Running
Driven @ Iref x2
See Note1
Tristate
Non-Stop
Stoppable
Outputs
Outputs
Byte1[7] = 1
Byte1[7] = 0
Running
Running
Running
Driven @
Iref x6
Running
Tristate
Driven @
Driven @
Iref x2
Iref x2
Tristate
Tristate
Type
Default
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Note
See Note1
See Note1
Note
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