Renesas HD151TS207SS Specification Sheet page 12

HD151TS207SS
2
I C Controlled Register Bit Map (cont.)
Byte9 Control Register
Bit Description
7 SSC2 Enable Bit
6 SSC1 Enable Bit
5 Clock Frequency Control
Bit4
4 Clock Frequency Control
Bit3
3 Clock Frequency Control
Bit2
2 Clock Frequency Control
Bit1
1 Clock Frequency Control
Bit0
0 Frequency Select Mode Bit
Rev.1.00, Apr.25.2003, page 12 of 38
Contents
B6[2] = 0 or B9[7] = 1 : SSC2 =OFF
B6[2] = 1 & B9[7] = 0 : SSC2 = ON
B6[2] = 0 or B9[6] = 1 : SSC1 = OFF
B6[2] = 1 & B9[6] = 0 : SSC1 = ON
Latched input PCIF_1 at Power ON
Latched input DOT48 at Power ON
Latched input PCIF_0 at Power ON
Latched input FS_A at Power ON
Latched input FS_B at Power ON
0 = Freq. is selected by latched input
FS_A and FS_B
2
1 = Freq. is selected by I C B9[5:1]
Type Default Note
RW 0
RW 0
RW X See
Table
6
RW X
RW X
RW X
RW X
RW 0