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HD151TS207SS
2
I
C Controlled Register Bit Map (cont.)
Table3 FS_A and FS_B pin Input level
Logic Level
0 (Low)
1 (High)
Byte1 Control Register
Bit
Description
7
Allow control of SCR with assertion
of PCI_STOP#
6
SRC Output enable
5
Reserved
4
Reserved
3
Reserved
2
CPU2 Output enable
1
CPU1 Output enable
0
CPU0 Output enable
Byte2 Control Register
Bit
Description
7
SRC_Pwrdwn drive mode
6
SRC_Stop drive mode
5
CPU2_Pwrdwn drive mode
4
CPU1_Pwrdwn drive mode
3
CPU0_Pwrdwn drive mode
2
Reserved
1
Reserved
0
Reserved
Rev.1.00, Apr.25.2003, page 8 of 38
Min Voltage
0.70V
Contents
0 = Free running
1 = Stopped with
PCI_STOP#
0 = Disabled (tristate)
1 = Enabled
0 = Disabled (tristate)
1 = Enabled
0 = Disabled (tristate)
1 = Enabled
0 = Disabled (tristate)
1 = Enabled
Contents
0 = Driven in power down,
1 = Tristate
0 = Driven when stopped,
1 = Tristate
0 = Driven in power down,
1 = Tristate
0 = Driven in power down,
1 = Tristate
0 = Driven in power down,
1 = Tristate
Max Voltage
0.35V
Type
Default
Note
RW
0
See
Table5
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Type
Default
Note
RW
0
See
Table5
RW
0
RW
0
See
Table4
RW
0
RW
0
RW
0
RW
0
RW
0
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