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HD151TS207SS
Block Diagram
3.3 V VDD_48
XTAL
14.318 MHz
OSC
PWRDWN#/SAFE_F#
PCI_STOP#
VTT_PWRGD#
TEST_CLK#
*MODE
*SEL100_200
*SEL66_48
*SEL48_24
*SEL33_25
*FS_4/3/2A/B
SCLK
SDATA
* : Latched Input pin.
Rev.1.00, Apr.25.2003, page 6 of 38
VSS_48
3.3 V VDD_A
VSS_A
CK2
1/M2
PLL2
SSC2
For
CPU
1/N2
Input
CK1
1/M1
PLL1
Clock
For
Select
SSC1
SRC
3V66
PCI
1/N1
CK0
1/M0
USB
PLL
1/N0
Control Logic
VSS_IREF
6× 3.3V VDD
6×VSS
VCO2
Clock
Select
Clock
VCO1
Delay
Divider
Control
Stop
Control
VCO0
IREF
REF[1:0]
(14.318MHz)
CPU[2:0]
CPU[2:0]#
SRC
SRC#
PCI[6:0]
PCIF[2:0]
3V66_0/RESET#
3V66[3:1]
3V66_4/VCH
USB_48
DOT_48
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