Renesas HD74LV2GT14A Datasheet
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Renesas HD74LV2GT14A Datasheet

Renesas HD74LV2GT14A Datasheet

Triple inverters with schmitt-trigger inputs / cmos logic level shifter
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HD74LV2GT14A
Triple Inverters with Schmitt-trigger Inputs /
CMOS Logic Level Shifter
Description
The HD74LV2GT14A has triple inverters with Schmitt-trigger inputs in an 8 pin package. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic
1.8 V or 2.5 V CMOS logic
All inputs V
(Max.) = 5.5 V (@V
IH
All outputs V
(Max.) = 5.5 V (@V
O
Output current ±6 mA (@V
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
HD74LV2GT14AUSE SSOP-8 pin
Rev.2.00, Oct.16.2003, page 1 of 9
5.0 V CMOS logic (@V
CC
3.3 V CMOS logic (@V
= 0 V to 5.5 V)
CC
= 0 V)
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
Package Code
TTP-8DBV
(Previous ADE-205-666A (Z))
= 5.0 V)
= 3.3 V)
CC
= 4.5 V to 5.5 V)
CC
Package
Abbreviation
US
REJ03D0141–0200Z
Rev.2.00
Oct.16.2003
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)

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Summary of Contents for Renesas HD74LV2GT14A

  • Page 1 CMOS Logic Level Shifter Description The HD74LV2GT14A has triple inverters with Schmitt-trigger inputs in an 8 pin package. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply.

  • Page 2: Function Table

    HD74LV2GT14A Outline and Article Indication • HD74LV2GT14A SSOP-8 Function Table Input A H : High level L : Low level Rev.2.00, Oct.16.2003, page 2 of 9 Index band Lot No. Y M W T 1 4 Marking Output Y Y : Year code...

  • Page 3: Pin Arrangement

    HD74LV2GT14A Pin Arrangement Absolute Maximum Ratings Item Symbol Supply voltage range Input voltage range *1, 2 Output voltage range Input clamp current Output clamp current Continuous output current Continuous current through or I or GND Maximum power dissipation at Ta = 25°C (in still air)

  • Page 4: Recommended Operating Conditions

    HD74LV2GT14A Recommended Operating Conditions Item Symbol Supply voltage range Input voltage range Output voltage range Output current Operating free-air temperature T Note: Unused or floating inputs must be held high or low. Rev.2.00, Oct.16.2003, page 4 of 9 Unit Conditions —...

  • Page 5: Electrical Characteristic

    HD74LV2GT14A Electrical Characteristic Ta = –40 to 85°C Item Symbol V Input voltage – Output voltage Min to Max Min to Max Input current 0 to 5.5 Quiescent supply current Output leakage current I Input capacitance Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.

  • Page 6: Switching Characteristics

    HD74LV2GT14A Switching Characteristics = 3.3 ± 0.3 V Ta = 25°C Item Symbol Propagation — delay time — 10.0 = 5.0 ±0.5 V Ta = 25°C Item Symbol Propagation — delay time — Operating Characteristics = 50 pF Item Symbol...

  • Page 7: Test Circuit

    HD74LV2GT14A Test Circuit Input Output Pulse generator Note: C includes probe and jig capacitance. Rev.2.00, Oct.16.2003, page 7 of 9...
  • Page 8 HD74LV2GT14A Waveforms Vref Input Output Notes: 1. Input waveform : PRR 2. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct.16.2003, page 8 of 9 Vref INPUTS Vref 3.3±0.3 2.5 V 3.0 ns 5.0±0.5 3.0 ns...

  • Page 9: Package Dimensions

    HD74LV2GT14A Package Dimensions (0.5) (0.5) + 0.1 8 0.2 0.05 Rev.2.00, Oct.16.2003, page 9 of 9 (0.5) Package Code JEDEC JEITA Mass (reference value) Unit: mm TTP–8DBV 0.010 g...
  • Page 10 Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

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